TW201535642A - 包含高密度無凸塊建立層及較小密度核心或無核心基底之積體電路封裝 - Google Patents

包含高密度無凸塊建立層及較小密度核心或無核心基底之積體電路封裝 Download PDF

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TW201535642A
TW201535642A TW104112066A TW104112066A TW201535642A TW 201535642 A TW201535642 A TW 201535642A TW 104112066 A TW104112066 A TW 104112066A TW 104112066 A TW104112066 A TW 104112066A TW 201535642 A TW201535642 A TW 201535642A
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conductive contacts
microelectronic
microelectronic die
component
dielectric material
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TW104112066A
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TWI637472B (zh
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Oswald Skeete
Ravi Mahajan
John Guzek
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Intel Corp
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Abstract

在一些實施例中，提出積體電路封裝包含高密度無凸塊建立層及較小密度核心或無核心基底。針對此，介紹一種設備，具有第一元件，其包括具有主動表面及至少一側之微電子晶粒、與該至少一微電子晶粒側相鄰之密封材料，其中該密封材料包括與該微電子晶粒主動表面實質上平面的至少一表面、設置在該微電子晶粒主動表面及該密封材料表面的至少一部分上之第一介電質材料層、設置在該第一介電質材料層上之複數建立層以及設置在該第一介電質材料層及該些建立層上並與該微電子晶粒主動表面電接觸之複數導電跡線；與該第一元件耦合之第二元件，該第二元件包括基底，其具有複數介電質材料層以及將上表面上的導電接點與下表面上的導電接點導電性耦合之導電跡線，在該上表面上的該些導電接點與該第一元件之該些 導電跡線導電性耦合。亦揭露其他實施例並主張其之專利權。

Description

包含高密度無凸塊建立層及較小密度核心或無核心基底之積體電路封裝
本發明主要有關於積體電路封裝設計的領域，詳言之，包括高密度無凸塊建立層及較小密度核心或無核心基底之積體電路封裝。
隨著電晶體尺寸縮小且有更多功能包含在微電子裝置中，亦需縮減晶粒對封裝基底互連之幾何。目前，晶粒使用常稱為覆晶式連結之焊料連合連結來連接至封裝基底。隨著凸塊間距縮減，因為覆晶凸塊間之空間的填補困難而使傳統覆晶程序變得越來越複雜。
100‧‧‧第一積體電路封裝元件
102‧‧‧微電子晶粒
104‧‧‧微電子晶粒主動表面
106‧‧‧密封材料
108‧‧‧微電子封裝核心
110‧‧‧第一介電質材料層
112‧‧‧建立層
114‧‧‧導電跡線
116‧‧‧導電接點
200‧‧‧第二積體電路封裝元件
202‧‧‧基底核心
204‧‧‧上建立層
206‧‧‧下建立層
208‧‧‧上表面
210‧‧‧下表面
212‧‧‧上導電接點
214‧‧‧下導電接點
216‧‧‧導電跡線
218‧‧‧嵌入式構件
220‧‧‧上間距
222‧‧‧下間距
300‧‧‧積體電路封裝
302‧‧‧填料材料
400‧‧‧電子用具
402‧‧‧處理器
404‧‧‧記憶體控制器
406‧‧‧系統記憶體
408‧‧‧輸入/輸出控制器
410‧‧‧網路控制器
412‧‧‧輸入/輸出裝置
在附圖中例示性而非限制性圖解本發明之實施例，圖中類似參考符號係指類似之元件，且其中：第1圖為根據本發明之一範例實施例的包括高密度無 凸塊建立層之第一封裝元件的剖面圖；第2圖為根據本發明之一範例實施例的包括較小密度核心或無核心基底之第二封裝元件的剖面圖；第3圖為根據本發明之一範例實施例的積體電路封裝之上視圖；以及第4圖為適合用於實施根據本發明之一範例實施例的積體電路封裝之範例電子用具的區塊圖。
【發明內容與實施方式】
在下述說明中，為了解釋，提出各種特定細節以提供本發明之詳盡的了解。然而，對熟悉該項技藝者而言，在沒有這些特定細節的情形下實行本發明為顯而易見者。在其他例子中，以區塊圖的形式顯示結構與裝置，以避免混淆本發明。
整份說明書中對於「一實施例」之參照意指連同該實施例所述之特定特徵、結構或特性包括在本發明之至少一實施例中。因此，在整份說明書中各處之「在一實施例中」用語的出現並非皆指相同的實施例。此外，在一或更多實施例中可以任何適當的方式結合特定特徵、結構或特性。
第1圖為根據本發明之一範例實施例的包括高密度無凸塊建立層之第一封裝元件的剖面圖。如所示，第一積體電路封裝元件100包括一或更多微電子晶粒102、微電子晶粒主動表面104、密封材料106、微電子封裝核心 108、第一介電質材料層110、建立層112、導電跡線114及導電接點116。
微電子晶粒102意圖代表任何種類的積體電路晶粒。在一實施例中，微電子晶粒102為多核心微處理器。微電子晶粒102包括主動表面104，其含有操作微電子晶粒102必須之電子連結。
藉由密封材料106將微電子晶粒102保持固定在至少一側上。密封材料106包括與主動表面104實直上平面的至少一表面。在一實施例中，主動表面104放置在一固持板上，而密封材料106設置在微電子晶粒102周圍。密封材料106可延伸到微電子晶粒102之背側(與主動表面104相反)。
微電子封裝核心108可包括在第一積體電路封裝元件100中，以於建立程序期間提供機械支撐及穩定性。微電子封裝核心108可具有其中設置有微電子晶粒102的開口。在一實施例中，微電子封裝核心108不包括在第一積體電路封裝元件100中，且可更廣泛地使用密封材料106。
第一介電質材料層110設置在主動表面104及密封材料106的至少一部分上。使用習知程序方法將建立層112接續設置在第一介電質材料層110上。
導電跡線114設置在第一介電質材料層110及建立層112上且與主動表面104電接觸。導電接點116與導電跡線114耦合，並允許第一積體電路封裝元件100藉由例如 焊料連結導電性耦合至第二積體電路封裝元件200，容後敘述。在一實施例中，導電接點116包括焊料凸塊。在另一實施例中，導電接點116包括焊墊(land)。
第2圖為根據本發明之一範例實施例的包括較小密度核心或無核心基底之第二封裝元件的剖面圖。如所示，第二積體電路封裝元件200包括一或更多基底核心202、上建立層204、下建立層206、上表面208、下表面210、上導電接點212、下導電接點214、導電跡線216、嵌入式構件218、上間距220及下間距222。
第二積體電路封裝元件200與第一積體電路封裝元件100耦合以形成積體電路封裝。第二積體電路封裝元件200可包括基底核心202以提供機械支撐。可採用習知處理方法來形成上建立層204及下建立層206。在一實施例中，基底核心202不包括在第二積體電路封裝元件200中，且可僅單獨利用建立層，例如多層有機基底。
上導電接點212設置在上表面208上。上導電接點212允許第二積體電路封裝元件200例如藉由焊料連結導電性耦合至第一積體電路封裝元件100。在一實施例中，上導電接點212包括焊料凸塊。在另一實施例中，上導電接點212包括焊墊。
下導電接點214設置在下表面210上。下導電接點214允許第二積體電路封裝元件200例如藉由插槽連結導電性耦合至其他裝置，例如印刷電路板。在一實施例中，下導電接點214包括焊墊柵陣列。在另一實施例中，下導 電接點214包括球柵陣列。在另一實施例中，下導電接點214包括針柵陣列。
導電跡線216路由經過第二積體電路封裝元件200，以導電性耦合上導電接點212及下導電接點214。
嵌入式構件218可包括在第二積體電路封裝元件200的基底中。在一實施例中，嵌入式構件218包括至少一記憶體裝置。在另一實施例中，嵌入式構件218包括至少一離散構件，如電容器、電感器、電阻器、邏輯裝置或類似者。
將第二積體電路封裝元件200設計成從上間距220傳送信號至下間距222。在一實施例中，上間距220細密如能在第一積體電路封裝元件100及第二積體電路封裝元件200之間形成焊料結合連結。在一實施例中，上間距220為從約80至約130微米。在一實施例中，下間距222為從約400至約800微米。
第3圖為根據本發明之一範例實施例的積體電路封裝之上視圖。如所示，積體電路封裝300包括與第二封裝元件200耦合的複數第一封裝元件100。雖顯示包括四個第一封裝元件100，可包括任何數量。在一實施例中，十六個第一封裝元件100耦合第二封裝元件200。填料材料302，如環氧化物，可流入第一封裝元件100與第二封裝元件200之間。填料材料302可實質上填補導電接點116與導電接點212之間的連結(例如焊料結合連結，未圖示)間之空間。
第4圖為適合用於實施根據本發明之一範例實施例的積體電路封裝之範例電子用具的區塊圖。電子用具400意圖代表任何各種的傳統與非傳統電子用具、膝上型電腦、桌上型電腦、手機、無線通訊訂戶單元、無線通訊電話架構元件、個人數位助理、機上盒或可因本發明之教示而受益的其他電子用具。根據所示之範例實施例，電子用具400可包括一或更多處理器402、記憶體控制器404、系統記憶體406、輸入/輸出控制器408、網路控制器410及輸入/輸出裝置412，如第4圖中所示般耦合。電子用具400之處理器402或其他積體電路構件可包含如前述作為本發明之一實施例的兩元件式封裝。
處理器402可代表任何各種控制邏輯，包括但不限於微處理器、可編程邏輯裝置(PLD)、可編程邏輯陣列(PLA)、特定應用積體電路(ASIC)、微控制器等等之一或更多，雖本發明不限於此態樣。在一實施例中，處理器402為英特爾®相容之處理器。處理器402可具有指令集，含有可由例如應用或操作系統引發之複數機器級指令。
記憶體控制器404可代表任何種類的晶片組或控制邏輯，其將系統記憶體406與電子用具400之其他構件接介。在一實施例中，處理器402與記憶體控制器404之間的連結可為點對點序列鏈結。在另一實施例中，記憶體控制器404可稱為北橋。
系統記憶體406可代表用來儲存處理器402已使用或 將使用之資料與指令的任何種類之記憶體裝置。典型地，雖本發明不限於此態樣，系統記憶體406由動態隨機存取記憶體(DRAM)所構成。在一實施例中，系統記憶體406由倫巴斯(Rambus)DRAM(RDRAM)所構成。在另一實施例中，系統記憶體406由雙資料率同步DRAM(DDRSDRAM)所構成。
輸入/輸出(I/O)控制器408可代表任何種類之晶片組或控制邏輯，其將I/O裝置412與電子用具400之其他構件接介。在一實施例中，I/O控制器408可稱為南橋。在另一實施例中，I/O控制器408可符合由PCI特別興趣群組於2003年4月15日發佈之周邊構件互連快速(PCI Express)TM基礎規格修訂版1.0a。
網路控制器410可代表任何種類的裝置，其允許電子用具400與其他電子用具或裝置通訊。在一實施例中，網路控制器410可符合美國電機暨電子工程師學會(IEEE)802.11b標準(於1999年9月16日通過，輔助ANSI/IEEE Std 802.11，1999版本)。在另一實施例中，網路控制器410可為乙太網路介面卡。
輸入/輸出裝置412可代表任何種類的裝置、周邊裝置或構件，其提供輸入給電子用具400或處理來自電子用具400之輸出。
在上述說明中，為了解釋，提出各種特定細節以提供本發明之詳盡的了解。然而，對熟悉該項技藝者而言，在沒有這些特定細節之一些的情形下實行本發明為顯而易見 者。在其他例子中，以區塊圖的形式顯示習知的結構與裝置。
以最基本的形式描述方法之許多部分，但可添加程序至方法之任何或自其刪除程序，且可添加資訊至所述訊息之任何或自其刪除資訊，而不背離本發明之基本範疇。在本發明之範疇與精神能預期到發明概念之任何各種變化。針對此，特定所示範例實施例並非提供來限制而只是用來說明本發明。因此，本發明之範疇並非由上述之特定範例而係僅由下列申請專利範圍的明語所決定。
100‧‧‧第一積體電路封裝元件
102‧‧‧微電子晶粒
104‧‧‧微電子晶粒主動表面
106‧‧‧密封材料
108‧‧‧微電子封裝核心
110‧‧‧第一介電質材料層
112‧‧‧建立層
114‧‧‧導電跡線
116‧‧‧導電接點

Claims (18)

  1. 一種設備，包含：複數第一元件，各包括：微電子晶粒，具有主動表面及至少一側，密封材料，與該至少一微電子晶粒側相鄰，其中該密封材料包括與該微電子晶粒主動表面實質上平面的至少一表面，第一介電質材料層，其形成與該微電子晶粒主動表面及該密封材料表面的至少一部分實質上連續、直接的界面，複數建立層，設置在該第一介電質材料層上，以及複數導電跡線，設置在該第一介電質材料層及該些建立層上，並與該微電子晶粒主動表面電接觸；以及第二元件，與該複數第一元件耦合，該第二元件包括無核心的多層有機基板，以將上表面上的導電接點與下表面上的導電接點導電性耦合，在該上表面上的該些導電接點與該複數第一元件之該些導電跡線導電性耦合。
  2. 如申請專利範圍第1項之設備，進一步包含該複數第一元件包括具有多個開口之微電子封裝核心，其中設置有多個該微電子晶粒。
  3. 如申請專利範圍第1項之設備，其中在該第二元件之該下表面上的該些導電接點包含焊墊柵陣列。
  4. 如申請專利範圍第1項之設備，其中在該第二元 件之該下表面上的該些導電接點包含球柵陣列。
  5. 如申請專利範圍第1項之設備，其中在該第二元件之該上表面上的該些導電接點包含凸塊。
  6. 如申請專利範圍第1項之設備，進一步包含在該第一元件與該第二元件間之環氧填料。
  7. 一種電子用具，包含：網路控制器；系統記憶體；以及處理器，其中該處理器包括：複數第一元件，各包括：微電子晶粒，具有主動表面及至少一側，密封材料，與該至少一微電子晶粒側相鄰，其中該密封材料包括與該微電子晶粒主動表面實質上平面的至少一表面，第一介電質材料層，設置在該微電子晶粒主動表面及該密封材料表面的至少一部分上，複數建立層，其形成與該第一介電質材料層實質上連續、直接的界面，複數導電跡線，設置在該第一介電質材料層及該些建立層上，並與該微電子晶粒主動表面電接觸；以及第二元件，與該複數第一元件耦合，該第二元件包括無核心的多層有機基板，以將上表面上的導電接點與下表面上的導電接點導電性耦合，在該上表面上的該些導 電接點與該複數第一元件之該些導電跡線導電性耦合；以及至少一記憶體元件，嵌於該第二元件之該無核心的多層有機基板內。
  8. 如申請專利範圍第7項之電子用具，進一步包含該複數第一元件包括具有多個開口之微電子封裝核心，其中設置有多個該微電子晶粒。
  9. 一種設備，包含：複數第一元件，各包括：微電子晶粒，具有主動表面及至少一側，密封材料，與該至少一微電子晶粒側相鄰，其中該密封材料包括與該微電子晶粒主動表面實質上平面的至少一表面，第一介電質材料層，其形成與該微電子晶粒主動表面及該密封材料表面的至少一部分實質上連續、直接的界面，複數建立層，設置在該第一介電質材料層上，以及複數導電跡線，設置在該第一介電質材料層及該些建立層上，並與該微電子晶粒主動表面電接觸；第二元件，與該複數第一元件耦合，該第二元件包括無核心的多層有機基板，以將上表面上的導電接點與下表面上的導電接點導電性耦合之導電跡線，在該上表面上的該些導電接點與該複數第一元件之該些導電跡線導電性耦 合；以及至少一記憶體元件，嵌於該第二元件之該無核心的多層有機基板內。
  10. 如申請專利範圍第9項之設備，其中該複數第一元件包含四個第一元件。
  11. 如申請專利範圍第9項之設備，其中該複數第一元件包含十六個第一元件。
  12. 如申請專利範圍第9項之設備，其中在該第二元件之該上表面上的該些導電接點包含從約80至約130微米之間距。
  13. 如申請專利範圍第9項之設備，其中在該第二元件之該下表面上的該些導電接點包含從約400至約800微米之間距。
  14. 如申請專利範圍第9項之設備，進一步包含該複數第一元件包括具有開口之微電子封裝核心，其中設置有該微電子晶粒。
  15. 如申請專利範圍第9項之設備，其中在該第二元件之該下表面上的該些導電接點包含焊墊柵陣列。
  16. 如申請專利範圍第9項之設備，其中在該第二元件之該下表面上的該些導電接點包含球柵陣列。
  17. 如申請專利範圍第9項之設備，其中在該第二元件之該上表面上的該些導電接點包含凸塊。
  18. 如申請專利範圍第9項之設備，進一步包含在該複數第一元件與該第二元件間之環氧填料。
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WO2009042463A1 (en) 2009-04-02
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US9941245B2 (en) 2018-04-10
TWI637472B (zh) 2018-10-01
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