TW201527093A - 預施用之底部塡料 - Google Patents

預施用之底部塡料 Download PDF

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Publication number
TW201527093A
TW201527093A TW103130351A TW103130351A TW201527093A TW 201527093 A TW201527093 A TW 201527093A TW 103130351 A TW103130351 A TW 103130351A TW 103130351 A TW103130351 A TW 103130351A TW 201527093 A TW201527093 A TW 201527093A
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Taiwan
Prior art keywords
polymer
layer
underfill
polymer region
underfill structure
Prior art date
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TW103130351A
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English (en)
Inventor
麥可Ｋ 嘉拉夫
愛德加多 安宙爾斯
大衛 夫摩恩
艾文Ｖ 杜布爾
廣志 張
安帕馬 奇貝
傑佛瑞Ｍ 卡佛特
Original Assignee
羅門哈斯電子材料有限公司
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Application filed by 羅門哈斯電子材料有限公司 filed Critical 羅門哈斯電子材料有限公司
Publication of TW201527093A publication Critical patent/TW201527093A/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/06—Interconnection of layers permitting easy separation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B27/08—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/18—Layered products comprising a layer of synthetic resin characterised by the use of special additives
    • B32B27/20—Layered products comprising a layer of synthetic resin characterised by the use of special additives using fillers, pigments, thixotroping agents
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/28—Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42
    • B32B27/281—Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42 comprising polyimides
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/30—Layered products comprising a layer of synthetic resin comprising vinyl (co)polymers; comprising acrylic (co)polymers
    • B32B27/308—Layered products comprising a layer of synthetic resin comprising vinyl (co)polymers; comprising acrylic (co)polymers comprising acrylic (co)polymers
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/32—Layered products comprising a layer of synthetic resin comprising polyolefins
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/34—Layered products comprising a layer of synthetic resin comprising polyamides
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/36—Layered products comprising a layer of synthetic resin comprising polyesters
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    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/38—Layered products comprising a layer of synthetic resin comprising epoxy resins
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • B32B27/40—Layered products comprising a layer of synthetic resin comprising polyurethanes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
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    • B32B2250/00—Layers arrangement
    • B32B2250/24—All layers being polymeric
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B2264/10—Inorganic particles
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    • B32B2307/70—Other properties
    • B32B2307/748—Releasability
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
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Abstract

可用作為預施用之底部填充材料之底部填充結構包含具有第一聚合物區域及第二聚合物區域之聚合物層，其中該第二聚合物區域包含無機填料。包含晶片或晶粒及基板的電子總成係使用此種多層結構預施用之底部填料形成。

Description

預施用之底部填料
本發明大致上係有關於電子封裝領域，及更明確言之係有關於預施用之底部填料領域。
其中積體電路(IC)晶片大致上倒置及使用可焊互連體接合至基板之覆晶技術近年來在半導體封裝方面快速成長。針對此項技術要求的關鍵驅動因素乃I/O連結的增加，其允許更高速度的及更短的連結，結果導致改良之信號完整性。占有覆晶IC晶片與基板間之空間的底部填充材料乃覆晶封裝體之可信度關鍵。底部填充材料支撐電氣連接，保護該等電氣連接免受環境影響，及減少覆晶連接上的熱機械應力。一般而言，以聚合物為主之底部填充材料具有與晶片及基板組件諸如焊料連結點不同的熱膨脹係數(CTE)。此CTE不匹配可能導致造成裝置故障的熱機械應力，諸如當該裝置經歷溫度週期循環時。為了減少此CTE不匹配，底部填充材料典型地含有無機填料，諸如二氧化矽。
將該底部填料分注至基板上之晶片邊緣，及允許該底部填料在毛細作用下在該晶片與基板間之間隙 流動已經成為將底部填料結合於封裝體內之最常見方法。某些情況下，毛細流動可能是緩慢的，諸如當高含量之填料添加至底部填充材料時；及/或毛細流動不完全而導致封裝體內的空洞，及也可能在該底部填料中之聚合物與填料間之非均質問題，原因在於毛細流動期間填料沈降原故。隨著晶片大小的增加及/或在覆晶晶粒上之該等互連結構之節距大小的縮小，此項問題可能變得益發嚴重。
另一種底部填充方法為無流式底部填充(NUF)方法，其中該底部填料係分配送至該基板上，及然後，該晶片/晶粒係置於該底部填料頂上。但此種方法仍有某些問題，諸如捕困於基板上之晶片/晶粒上之可焊特徵(諸如焊料凸塊)和接合墊間之填料粒子，結果導致互連失敗。
晶圓層級底部填充(WLUF)方法乃又另一替代辦法，其中該底部填料可施用至有凸塊晶圓上，或施用至沒有焊料凸塊及隨後進行凸塊過程之晶圓上。底部填充材料可藉多種技術諸如膜積層、旋塗、或網版印刷法而施用至晶圓。類似NUF方法，該WLUF方法面臨了避免晶圓上之可焊特徵與基板上之接合墊間之填料被捕困的挑戰。
美國專利第6,861,285號描述一種方法，其中複數個底部填充層係施用至有凸塊晶圓，至少一層底部填充層含有填充材料，及至少一層底部填充層不含或實質上不含填充材料，其中各底部填充材料層係個別地施用。含有填料之底部填充層首先施用至晶圓上。在已經施用期 望數目之此等經填充之底部填充層後，然後使用化學及/或機械方法從凸塊頂部去除該底部填充材料，及暴露出該等凸塊頂面。此等方法包括研磨或碾磨、乾蝕刻或濕蝕刻、化學機械研磨、反應離子蝕刻、雷射銑削、及雷射燒蝕。其次，不含或實質上不含填充材料的底部填充材料層係施用至該經填充之底部填充層表面及施用至焊料凸塊之暴露頂面上方。最後，晶圓接合至基板，其中焊料凸塊與基板上相對應的接合墊接觸。該專利案描述之方法要求化學及/或機械移除步驟，於該期間焊料凸塊容易受損，結果導致裝置可能高比率故障。仍然需要有於IC總成(assembly)之製造中施用底部填充材料之改良方法。
本發明提供一種底部填充結構，其依序地包含：頂膜層；聚合物層，及底膜層，其中該聚合物層包含第一聚合物區域及第二聚合物區域，其中該第二聚合物區域包含無機填料。較佳地，該第一聚合物區域不含無機填料。此種多區域底部填充結構係以單一步驟施用至基板。
本發明進一步提供一種方法，包含：提供如前述之底部填充結構；從該底部填充結構去除底膜；積層底部填充結構至其上具有複數個互連結構之組件之表面，使得該底部填充結構係被壓在該等互連結構間，其中該第二聚合物區域之高度係小於或等於該等互連結構之高度；及去除該頂膜層。較佳地，該第二聚合物區域之高度係低於該等互連結構之高度。於一個具體實施例中，該聚 合物層之高度係低於該等互連結構之高度。較佳地，本發明進一步包含：將該等互連結構之頂部與於基板之表面上的複數個傳導性接合墊對齊以形成單元；及電氣連接該等互連結構與該等傳導性接合墊。加熱(其造成互連結構至少部分地熔解以便接合該等互連結構與該等接合墊)及熱超音波接合乃電氣連接該等互連結構與該等傳導性接合墊之適當方法。
本發明也提供一種方法，包含：提供如前述之底部填充結構；從該底部填充結構去除底膜；積層該底部填充結構至具有複數個傳導性接合墊之基板之表面，使得該第一聚合物區域係位在該基板表面正上方；及去除頂膜層。較佳地，本發明進一步包含：將該等傳導性接合墊與於組件之表面上的複數個互連結構之頂面對齊以形成單元；及電氣連接該等互連結構與該等傳導性接合墊。加熱(其造成該等互連結構至少部分地熔解以便接合該等互連結構與該等接合墊)及熱超音波接合乃電氣連接該等互連結構與該等傳導性接合墊之適當方法。
10‧‧‧頂膜層
15‧‧‧緩衝層
17‧‧‧頂膜部分
18a、18b、18c‧‧‧凱佛特小丘
20‧‧‧第一聚合物區域、第一區域
30‧‧‧第二聚合物區域、第二區域
31‧‧‧無機填料
40‧‧‧底膜層
50‧‧‧組件表面
55‧‧‧組件表面
60‧‧‧焊料凸塊
65‧‧‧金屬柱
75‧‧‧輥輪
80‧‧‧基板
85‧‧‧傳導性接合墊
PL‧‧‧聚合物層
第1A圖及第1B圖為本發明之底部填充結構之替代具體實施例之剖面示意圖。
第2圖為顯示將本發明之底部填充結構配置至具有焊料凸塊之晶圓上之積層方法之示意圖。
第3A圖及第3B圖為顯示將本發明之底部填充結構配置至具有金屬柱互連結構之晶圓上之另一種積 層方法之示意圖。
第4圖為例示將本發明之底部填充結構積層至具有金屬柱互連結構之基板上之示意圖。
第5A圖至第5C圖為顯示使用本發明之底部填充結構之替代積層方法及所得之電子總成之示意圖。
第6圖為本發明之底部填充結構之剖面顯微視圖。
如本說明書全文中使用，除非上下文另行明白指示，否則下列縮寫須具有下列意義：℃=攝氏度數；g=公克；kg=公斤；μm=μ=微米；mm=毫米；min.=分鐘；DI=去離子；mol=莫耳；及rpm=每分鐘之轉數。除非另行載明，否則全部數量皆為重量百分比(wt%)及全部比值為重量比。全部數值範圍皆為包含邊值且可以任何順序組合，除了顯然此等數值範圍係限於加總至100%處。於附圖中，類似之元件符號係指相似的元件。冠詞「一(a)」、「一(an)」、及「該」係指單數及複數。「烷基」係指直鏈、分支鏈及環狀烷基。「芳基」係指芳香族碳環及芳香族雜環。術語「(甲基)丙烯酸酯」係指丙烯酸酯及甲基丙烯酸酯兩者。同理，術語「(甲基)丙烯酸系」係指丙烯酸系及甲基丙烯酸系兩者。
將須瞭解當一個元件係稱作為在另一個元件「上方」時，該元件可直接地位在另一個元件上方，或它們之間可存在有介入元件。相反地，當一個元件係稱作 為在「在另一元件正上方」時，它們之間不存在介入元件。
也將須瞭解雖然術語第一、第二、第三等可用於本文中描述各種元件、組件、區域、層、部分或區段，但此等元件、組件、區域、層、部分或區段不應受此等術語所限。此等術語僅係用以區別一個元件、組件、區域、層、部分或區段與另一個元件、組件、區域、層、部分或區段。因此，在不背離本發明之教示下，第一元件、組件、區域、層、部分或區段也可命名為第二元件、組件、區域、層、部分或區段。
再者，相對術語，諸如「下」或「底」及「上」或「頂」可用於本文中描述一個元件與另一個元件的關係，如附圖中例示。將須瞭解相對術語係意圖涵蓋裝置除了附圖中描繪之定向之外之不同的定向。舉例言之，若於附圖之一圖中之裝置被翻轉，則被描述為在其它元件「下」側的元件將變成在其它元件「上」側。因此，係取決於圖的具體定向而決定範例術語「下」涵蓋「下」及「上」之兩個方向。同理，若於附圖之一圖中之裝置被翻轉，則被描述為在其它元件「下方」或「之下」的元件將變成在其它元件「上方」。因此，範例術語「下方」或「之下」涵蓋上方及下方之兩個方向。
本發明提供可用以於電氣總成中形成預施用之底部填料的一種乾膜結構。本結構依序地包含：頂膜層；聚合物層，及底膜層，其中該聚合物層包含第一聚合物區域及第二聚合物區域，其中該第二聚合物區域包含無 機填料。較佳地，該第一聚合物區域不含無機填料。該結構可視需要地包含一或多層額外材料之層，諸如緩衝層、離型層等。較佳地，該結構包含緩衝層，及更佳地該緩衝層係設置於該頂膜層與該聚合物層間。視需要地，該結構可包括設置於該頂膜層與該聚合物層間之離型層。
於本結構之一個具體實施例中，頂膜層係在聚合物層之第一聚合物區域上，及較佳地緩衝層係設置於頂膜層與第一聚合物區域間。第1A圖例示本發明之一個具體實施例之剖面示意圖，依序地具有頂膜層10、視需要的緩衝層15、聚合物層PL及底膜40，其中聚合物層PL由在第二聚合物區域30上之第一聚合物區域20所組成，而且第二聚合物區域30包含無機填料31。於第1A圖中，頂膜層10係在聚合物層之第一聚合物區域20上，及該聚合物層之第二聚合物區域30係在底膜40之正上方。於一替代具體實施例中，頂膜層係在第二聚合物區域上，及較佳地緩衝層係設置於該頂膜層與該第二聚合物區域間。第1B圖例示本發明之此一替代具體實施例之剖面示意圖，其依序地具有頂膜層10、視需要的緩衝層15、由在第一聚合物區域20上之包含無機填料31的第二聚合物區域30所組成的聚合物層PL，其中第一聚合物區域20係在底膜層40上。第1A圖及第1B圖之任一結構可視需要地含有設置於聚合物層PL與底膜層40間之離型層(圖中未顯示)。於使用時，在該結構積層至表面之前，從底部填充結構去除底膜，及於積層至表面之後，接著去除頂膜層然後以於表面 上提供聚合物層來作為預施用之底部填料。
頂膜層之作用係於儲存及處理期間保護聚合物層，及於積層期間協助將聚合物層定位於互連結構間。頂膜層具有足夠的薄膜完整性，因而頂膜層能夠藉由撕離而從該聚合物層去除。由於頂膜層係藉由諸如撕離而從該底部填充結構去除，故頂膜層與聚合物層間之黏著性典型地為低度至中等。廣泛多種聚合物可用作為頂膜層，只要聚合物須符合前述標準，包括自由基聚合聚合物、接枝共聚物、逐階成長聚合聚合物等。用作為頂膜層的有用聚合物層包括下列之共聚物：聚烯烴類；聚烯烴共聚物類；聚氯乙烯；聚氯乙烯共聚物類；聚偏二氯乙烯；聚胺基甲酸酯類；聚胺基甲酸酯共聚物類；聚(甲基)丙烯酸酯類；及聚(甲基)丙烯酸酯共聚物類。較佳聚烯烴類包括聚乙烯、聚丙烯、聚丁烯、聚異丁烯、及聚異戊間二烯。彈性體乃作為頂膜層有用的另一類較佳聚合物料。此等彈性體包括，但不限於：聚烯烴彈性體；乙烯乙酸乙烯酯；聚醚嵌段醯胺類；聚丙烯酸系橡膠、乙烯丙烯橡膠；乙烯丙烯二烯橡膠；聚異丁烯聚丁二烯；聚矽氧-胺基甲酸酯共聚物類；聚丁二烯-聚胺基甲酸酯共聚物類；苯乙烯-嵌段共聚物；苯乙烯-丁二烯共聚物；及聚氯乙烯彈性體。聚烯烴彈性體為發明所屬技術領域中眾所周知，及典型地為乙烯與另一種α-烯烴之共聚物。此外，較佳為頂膜層係足夠可彎曲以變形，但於積層期間不會造成互連結構的變形。頂膜層可具有任何適當厚度，諸如5至250微米，及較佳地10 至150微米。
視需要地，緩衝層係設置於頂膜層與聚合物層間。雖然不欲受理論所限，但緩衝層係在積層期間作為頂膜層與互連結構間之緩衝或墊層，允許頂膜層在積層期間之移動，但不會造成互連結構之變形。足夠可彎性允許頂膜層在積層期間之移動或於積層期間變形，但不會造成互連結構之變形的任何聚合物料皆可用作為緩衝層。緩衝層也可用以改良頂膜層與聚合物層間之黏著性。較佳為緩衝層為黏著性材料。發明所屬技術領域中已知之廣泛多種黏著性材料可用作為緩衝層，但限制條件為黏著性材料為可撕離且非永久性。較佳地，黏著性材料為壓力敏感性黏著劑(PSA)。壓力敏感性黏著劑乃發明所屬技術領域中眾所周知及典型地包含彈性體，諸如橡膠、(甲基)丙烯酸酯類、或聚矽氧類。當使用緩衝層時，較佳於從結構去除頂膜層時，緩衝層仍然保持與頂膜層一起，且無緩衝層殘餘物留在聚合物層上。在頂膜層去除之後，留在該聚合物層上的任何緩衝層殘餘物可藉由與適當去除劑(諸如，適合的有機溶劑)接觸而去除。較佳地，緩衝層係設置於頂膜層與聚合物層間，及更佳地PSA層係設置於頂膜層與聚合物層間。當用於本發明時，緩衝層之厚度並不重要，但典型地係於5至100微米及較佳地10至50微米之範圍。緩衝層之優點為可修飾頂層與聚合物層間之黏合能。
於一較佳具體實施例中，PSA膠帶用於本結構以形成頂膜層及緩衝層。PSA膠帶係由直接設置於聚合 物膜上之PSA層所組成。PSA膠帶之聚合物膜用作為本結構中之頂膜層，而PSA層之功能係作為緩衝層。廣泛多種PSA膠帶為市面上可得，且可用於本發明。特別有用的PSA膠帶為背磨膠帶。例舉之PSA膠帶為以商品名BG膠帶(得自林德公司(Lintec Corp.))、BG-HTCR100-PET(得自AI技術公司)、埃克羅斯(ICROSTM)膠帶(得自三井化學公司(Mitsui Chemicals))電夾(ELEGRIPTM)膠帶(得自電氣化學公司(Denka))出售者，以及得自東洋黏膠技術公司(Toyo Adtec)、古河電氣公司(Furukawa Electric)、及其它供應商之背研膠帶。較佳地，膠帶具有UV光敏感黏著劑層，該層於曝光適當UV輻射之前具有對表面相當強的黏著性，而且於曝光適當UV輻射之後具有相對弱的黏著性。亦即，當曝光於UV輻射時，膠帶變成更容易離型。因此，當採用具有UV敏感黏著劑之薄膜時，於頂膜去除步驟中可採用UV輻射曝光步驟。
本底部填充結構之聚合物層係由複數個聚合物區域所組成。該聚合物層包含至少兩個聚合物區域，即第一聚合物區域及第二聚合物區域，其中該第二聚合物區域包含無機填料。較佳為第一聚合物區域不含無機填料。較佳地，聚合物層係由兩個聚合物區域所組成。將須瞭解可使用多於兩個聚合物區域，但此等額外聚合物區域可能增加製程之成本。聚合物層可由具有至少兩個區別的區域的單一聚合物層組成，或者另外，聚合物層可由複數個個別聚合物層組成，其中此等複數個個別聚合物層形成 至少兩個區別的區域。各個聚合物區域可由單一聚合物層組成或可由複數個個別聚合物層組成。較佳為聚合物層包含兩層個別的聚合物層，各個個別的聚合物層形成區別的聚合物區域。發明所屬技術領域中具有通常知識者將瞭解藉由使用複數個個別聚合物層(其中該等層具有不同的無機填料含量)可達成於第二聚合物區域內之無機填料之梯度。
聚合物層可包含有用於作為底部填料的任何適合的聚合物。第一聚合物區域典型地包含一或多種聚合物、一或多種交聯劑、一或多種熱固化劑、及視需要地一或多種，其係選自於由下列各者所組成組群之添加劑：助熔劑、流動添加劑、軟化劑、溶劑、消泡劑、衝擊改質劑、界面活性劑、黏著促進劑、及其混合物。任何適合的聚合物、交聯劑、熱固化劑及視需要地添加劑皆可用於第一聚合物區域。有用於作為底部填料的任何聚合物可適合的地用於該第一聚合物區域。較佳地，聚合物為環氧樹脂，及更佳為環氧單體與二官能胺單體之聚合物。進一步較佳地係使用二官能環氧單體。可使用從三官能環氧單體生成的聚合物層，但限制條件為該三官能環氧單體係占用以形成該聚合物之單體總重之5wt%，及較佳地，3wt%。形成該聚合物為有用的環氧單體之範例包括，但不限於：雙酚A之二縮水甘油醚；雙酚F之二縮水甘油醚；雙酚S之二縮水甘油醚；蒽之二縮水甘油醚；二環戊二烯之二縮水甘油醚；萘之二縮水甘油醚；聯苯之二縮水甘油醚；丙 二醇之二縮水甘油醚；及二丙二醇之二縮水甘油醚。用於形成環氧/胺聚合物為的有用胺類包括，但不限於：1,8-二胺基萜烷；2,6-二胺基-2,6-二甲基-5-苯基庚-3-醇；2,6-二胺基-2,5,6-三甲基庚-3-醇；二-對-胺基苯甲酸丙二醇酯；及寡聚合性二胺聚四亞甲基氧化物-二-對-胺基苯甲酸酯。適當交聯劑為具有選自於羧酸、羥基、及胺的二或多個官能基之任何芳香族材料。較佳交聯劑包括酚系硬化劑，諸如酚醛清漆樹脂類及二酚聯苯類。適當酚醛清漆樹脂類包括，但不限於，酚型酚醛清漆樹脂、甲酚型酚醛清漆樹脂、及可溶(甲階)型酚醛清漆樹脂。例舉性酚系硬化劑為彼等以商品名DL-92、MEH 7800-4S、MEH 7851SS及MEH 7500得自明和塑膠工業公司(Meiwa Plastic Industries)販售者。交聯劑可以0至70wt%，較佳地5至50wt%，及更佳地5至30wt%之量存在。適合的的熱固化劑包括，但不限於，氮或磷化合物之鹽類。較佳固化劑為：六氟磷酸四丁基鏻、四苯基硼酸四苯基鏻、四苯基硼酸四丁基鏻、六氟磷酸四乙基鏻、四氟硼酸四丁基鏻；咪唑鹽類諸如彼等以庫里卓(CUREZOLTM)品牌得自空氣產品公司(Air Products)者；三芳基膦類諸如三苯基膦；及三級胺類諸如苄基二甲基胺及二氰基二醯胺。熱固化劑可以0至10wt%，較佳地0至5wt%，及更佳地0至3wt%之量存在。較佳地，第一聚合物區域包含助熔劑。適合的助熔劑為含有羧酸、酚或胺官能基之材料。助熔劑可以0至50wt%，較佳地0.01至20wt%，及更佳地0.01至5wt%之量存在於 第一聚合物區域。進一步較佳地形成第一聚合物區域之聚合物也作為助熔劑。作為助熔劑之較佳聚合物典型地包含第二胺部分，其中此種聚合物係以0.1至70wt%，更佳地30至70wt%，及甚至更佳地50至70wt%之量存在於第一聚合物區域。
第二聚合物區域典型地包含一或多種聚合物、一或多種交聯劑、一或種個熱固化劑、無機填料、及視需要地一或多種選自於由下列各者所組成組群之添加劑：助熔劑、流動添加劑、軟化劑、消泡劑、衝擊改質劑、界面活性劑、黏著促進劑、溶劑、及其混合物。任何適合的聚合物、交聯劑、熱固化劑、無機填料、及視需要地添加劑皆可用於第二聚合物區域。有用於作為底部填料為的任何聚合物可適合地用於第二聚合物區域。較佳地，聚合物為環氧樹脂，及更佳地為環氧單體與二官能胺單體之聚合物。進一步較佳地係使用二官能胺單體。可使用從三官能環氧單體生成的聚合物層，但限制條件為聚合物中之三官能環氧單體係占所使用之單體總重之5wt%，及較佳為3wt%。有用於形成聚合物的例舉環氧單體包括，但不限於：雙酚A之二縮水甘油醚；雙酚F之二縮水甘油醚；雙酚S之二縮水甘油醚；蒽之二縮水甘油醚；二環戊二烯之二縮水甘油醚；萘之二縮水甘油醚；聯苯之二縮水甘油醚；丙二醇之二縮水甘油醚；及二丙二醇之二縮水甘油醚。用於形成環氧/胺聚合物的有用胺類包括，但不限於：1,8-二胺基萜烷(或有譯為1,8-二胺基薄荷烷)；2,6-二胺基-2,6-二 甲基-5-苯基庚-3-醇；2,6-二胺基-2,5,6-三甲基庚-3-醇；二-對-胺基苯甲酸丙二醇酯；及寡聚合性二胺聚四亞甲基氧化物-二-對-胺基苯甲酸酯。適當交聯劑為具有選自於羧酸、羥基、及胺的二或多個官能基之任何芳香族材料。較佳交聯劑包括酚系硬化劑，諸如酚醛清漆樹脂類及二酚聯苯類。適當酚醛清漆樹脂類包括，但不限於，酚型酚醛清漆樹脂、甲酚型酚醛清漆樹脂、及可溶(甲階)型酚醛清漆樹脂。例舉性酚系硬化劑為彼等以商品名DL-92、MEH 7800-4S、MEH 7851SS及MEH 7500得自明和塑膠工業公司販售者。適合的的熱固化劑包括，但不限於，氮或磷化合物之鹽類。較佳固化劑為：六氟磷酸四丁基鏻、四苯基硼酸四苯基鏻、四苯基硼酸四丁基鏻、六氟磷酸四乙基鏻、四氟硼酸四丁基鏻；咪唑鹽類諸如彼等以庫里卓(CUREZOLTM)品牌得自空氣產品公司(Air Products)。熱固化劑可以0至3wt%，較佳地0至2wt%，及更佳地0.01至1.5wt%之量存在。用於第二聚合物區域之固化劑可與用於第一聚合物區域之固化劑相同或相異。任何適合的溶劑皆可用於第二聚合物區域。較佳地，第二聚合物區域包含助熔劑。適合的助熔劑為含有羧酸、酚或胺官能基之材料。助熔劑可以0至20wt%，較佳地0.01至15wt%，及更佳地0.01至10wt%之量存在於第二聚合物區域。進一步較佳為形成第二聚合物區域之聚合物也作為助熔劑。作為助熔劑之較佳聚合物典型地包含第二胺部分(moiety)，其中此種聚合物係以0至50wt%，更佳地30至50wt%，及甚至更 佳地20至50wt%之量存在於第二聚合物區域。較佳選用於第一聚合物區域之聚合物與選用於第二聚合物區域之聚合物為可相容，亦即，當加熱時(諸如，當互連結構係電氣連接至接合墊時)，視需要地於壓力存在下，兩個區別的聚合物區域將形成整體聚合物區域。
無機填料係用以降低聚合物層的總熱膨脹係數(CTE)，及因而降低底部填料的總熱膨脹係數(CTE)。本發明所使用的無機填料為非傳導性且為惰性，亦即，其將不與聚合物層反應或不安定化聚合物層。定量無機填料用在聚合物層以獲得接近用於矽對矽結合之組件(以矽晶圓為例，例如矽)之相對較低CTE，或介於組件(例如矽)之相對較低CTE與有機基板(諸如電路板，例如FR4)之相對較高CTE間的該底部填料之CTE。熱膨脹係數的妥當選擇乃該電子總成製造及隨後使用期間之應力遷移所需。該第一聚合物區域可視需要地包含無機填料。當填料存在於第一聚合物區域時，此種填料之含量係低於無機填料於第二聚合物區域之含量。若使用，以第一聚合物區域中之材料總重為基準，第一聚合物區域中之無機填料之含量係40wt%，較佳地30wt%，及更佳地20wt%。第一聚合物區域較佳係不含無機填料。第二聚合物區域包含40wt%無機填料，較佳地50wt%，及更佳地60wt%。較佳地，無機填料為二氧化矽、金屬氧化物、或陶瓷。適合的陶瓷無機填料為結晶氧化物、氮化物、或碳化物。較佳無機填料係選自氧化矽、氧化鋁、氧化鋯、氧化鈹、氧化鈰、氧化鋅、 氮化矽、氮化鋁、氮化硼、及碳化矽；及更佳地氧化矽、氧化鋁、氧化鋯、氮化矽、氮化鋁、氮化硼、及碳化矽。可使用無機填料之混合物。無機填料可具有任何適當形狀及大小。較佳地，無機填料具有球體形狀或實質上球體形狀。此種球形最小化表面積，且允許聚合物區域種有更高載荷之填料。較佳無機填料具有一種大小，諸如粒徑大小，該大小將不妨礙第二聚合物區域被互連結構穿透。較佳為無機填料具有0.005至10微米之平均粒徑，更佳地0.01至5微米，及又更佳地0.01至3微米。無機填料可視需要地以黏著促進劑處理以修飾填料粒子的表面化學，例如允許無機填料粒子與用在聚合物區域內之聚合物或交聯劑反應。修飾填料的表面化學可改良斷裂韌性，且可改良填料於聚合物區域之分散性。
一般而言，第一聚合物區域及第二聚合物區域各自可具有任何適當厚度。較佳地，第二聚合物區域之厚度係大於第一聚合物區域之厚度，及更佳地，第二聚合物區域之厚度係遠大於第一聚合物區域之厚度。典型地，第一聚合物區域具有於0.1至10微米，及更佳地0.1至5微米之範圍之厚度。典型地，雖然廣泛多種厚度可用於本底部填充結構，第二聚合物區域具有於5至150微米，及更佳地10至100微米之範圍之厚度。
由於頂膜層及底膜層兩者係在電子總成形成之前從本底部填充結構去除，底部填充結構中之唯一臨界維度為聚合物層之厚度。由於取決於所使用的特定結構 而使互連結構之高度有顯著改變，本發明之結構中之聚合物層之厚度並無特定範圍。聚合物層之總厚度(亦即，第一與第二聚合物區域之組合厚度)可大於、等於、或小於用以形成電子總成之互連結構之高度。第二聚合物區域之高度是關鍵的，且係等於或小於互連結構之高度，及較佳係小於互連結構之高度。第一聚合物區域其也用作為助熔劑功能，可覆蓋互連結構頂部。若聚合物層之高度係遠大於互連結構之高度，則會有聚合物層將沿著基板滲出或蠕變爬上晶粒側壁之風險。也可能將防止互連結構與其電氣連接的傳導性墊間的良好接觸。若聚合物層之高度係遠低於互連結構之高度，則在組件與基板組裝之後，聚合物層與基板或組件間可保留有非期望的間隙。互連結構之頂部與該聚合物層之頂面間之高度差異須足夠以引起於電子總成之組裝期間，當組件與基板接觸及加熱而焊接該組件至該基板(亦即，電氣連接互連結構至傳導性接合墊)時，互連結構及底部填料之擴散。於此組裝之後，聚合物層須填補組件之表面與基板之表面間之空間。
於本底部填充結構中之底膜層典型地係於製造、儲藏及隨後加工處理期間，用作為聚合物層及乾膜底部填充結構之任何其它層的撐體。概略言之，底膜層係諸如藉由撕離而從乾膜(聚合物層)去除，及典型地係在本底部填充結構積層至表面之前去除。據此，底膜層與聚合物層間之黏著性典型地為低度至中等以允許容易分離。概略言之，底膜層係在頂膜層之前被去除，故底膜層與聚合 物層間之黏著性比起頂膜層與聚合物層間之黏著性相對較低。用於底膜層之特定材料可有廣泛改變，及使用的特定材料並不重要。底膜層之材料可為剛性或撓性，且典型地呈卷形或板形。適合的底膜層材料包括，但不限於：聚酯諸如聚對苯二甲酸伸乙酯(PET)；紙；尼龍；玻璃；乙酸纖維素；聚烯烴；聚醯亞胺；聚胺基甲酸酯；聚(甲基)丙烯酸酯；金屬板；環氧積層物；經銅塗覆之纖維板；等。材料諸如PET、紙等可以各種方式塗覆。舉例言之，PET可經樹脂塗覆、焰處理或靜電放電處理、或滑移處理。用作為底膜之紙典型地為經樹脂塗覆，諸如聚乙烯塗覆之紙或經聚乙烯醇塗覆之紙。較佳地，底膜層為聚烯烴，及更佳地為聚乙烯。雖然底膜層典型地具有5至250微米之厚度，但底膜層之確切厚度並無特定限制，只要可支撐底部填充結構之其它各層即可。
視需要地，離型層可設置於底膜層與聚合物層間。離型層典型地係用當底膜層與聚合物層間之黏著性相對過高時，使得底膜層不易從聚合物層去除而又不會造成聚合物層或底部填充結構之其它層的損壞。使用的任何離型層須使得底膜層可從聚合物層撕離。當使用離型層時，較佳在底膜層從底部填充結構去除之時底膜層仍然留在底部填充結構，且無任何離型層殘餘物留在聚合物層上。較佳係不使用離型層。
本發明之底部填充結構可藉由提供底膜諸如PET膜，及塗覆含無機填料之聚合物料(經填充材料)之 層至膜頂面上而形成。含無機填料之聚合物層可使用狹縫模具、輥上刀(knife over roll)、或藉由熟諳發明所屬技術領域之人士已知之另一種適合的塗覆方法塗覆，及然後在典型地在進一步加工處理之前乾燥。若有所需，可額外含填料之聚合物層沈積以達成期望厚度之含無機填料區域。其次，比起經填充之材料層，含有較少無機填料含量及較佳不含無機填料(無填充材料層)之聚合物料層係藉由凹版塗法或發明所屬技術領域中具通常知識者已知之其它適合的方法塗覆至經填充材料層上，及然後典型地在進一步加工處理之前乾燥。另外，未經填充之聚合物料之層可藉由積層而設置於經填充之聚合物料之頂上。可用超過一層未經填充之聚合物層以達成期望厚度之未經填充之聚合物區域。然後，頂膜層係使用壓力，及視需要地藉由加熱而積層至未經填充之聚合物層之表面上。當緩衝層係用在本底部填充結構中時，較佳為緩衝層藉由發明所屬技術領域中使用的任何適當方法首先塗覆至頂膜層上，及然後含緩衝層之頂膜層係使用壓力及視需要地藉由加熱而積層至未經填充之聚合物層。
廣泛多種乾膜積層技術為發明所屬技術領域中所已知，及此等技術中之任一者係適用以將本底部填充結構積層至表面，諸如熱輥積層、真空積層、濕積層、及前述之組合等。較佳係使用真空積層。第2圖例示使用第1A圖之底部填充結構之熱輥積層技術。首先，底膜層40使用任何適合的方法而從底部填充結構去除(圖中未顯 示步驟)，其次底部填充結構積層至具有焊料凸塊(互連結構)60配置於其表面上之組件50之表面上，利用從一對相對配置的熱輥輪75施加壓力，一根輥輪係設置於該組件下方及施加壓力至該組件之後表面，及另一根輥輪係設置於底部填充結構上方及施加壓力至頂膜部分17。輥輪75內之箭頭所示輥輪轉動之方向。來自輥輪75之壓力在焊料凸塊60間推送聚合物層PL。聚合物層PL係由第一聚合物區域20及第二聚合物區域30組成，其中該第二聚合物區域包含無機填料。聚合物層PL之總高度可為小於(圖中顯示)、等於(圖中未顯示)、或大於(圖中未顯示)焊料凸塊60之高度。於離開輥輪75之後，頂膜部分17(包含頂膜層及視需要的緩衝層)係使用任何適合的方法從結構移除，結果導致預施用之底部填料(聚合物層PL)設置於組件50之表面上的焊料凸塊60間。
第3A圖例示使用第1A圖之底部填充結構之真空積層技術。首先，底膜層40係使用任何適合的方法(圖中未顯示步驟)從底部填充結構去除，其次底部填充結構係積層至具有金屬柱(互連結構)65設置於其表面上的組件55之表面。於真空積層機器(圖中未顯示)內之矽氧橡膠隔膜可用以使用加熱及壓力而將底部填充結構壓向與黏合至組件55之表面上。真空室內的真空可用以將隔膜下拉至組件表面，及壓力也可施加於隔膜後方(第3A圖中以箭頭所示)。施加於隔膜後方的任何壓力結合真空下拉一起作用而在金屬柱65間推送聚合物層PL。聚合物層PL係由第一 聚合物區域20及第二聚合物區域30組成，其中該第二聚合物區域包含無機填料。聚合物層PL(第一聚合物區域20+第二聚合物區域30)之總高度可為小於(圖中顯示)、等於(圖中未顯示)、或大於(圖中未顯示)金屬柱65之高度，而第二聚合物區域30之高度係小於金屬柱65之高度。將氣氛導入真空室後，頂膜部分17(包含頂膜層及視需要的緩衝層)係使用任何適合的方法從該結構移除，結果導致預施用之底部填料(聚合物層PL)設置於組件55之表面上的金屬柱65間。第3B圖例示類似第3A圖顯示之方法，但聚合物層PL之高度係大於金屬柱65之高度，而第二聚合物區域30之高度係小於金屬柱65之高度。於第3B圖中，第一聚合物區域20覆蓋金屬柱65頂部。
如前文參照第2圖及第3圖所討論，聚合物層之總高度(h)係小於、等於、或大於底部填充結構積層至其上的該表面上之互連結構之高度，而第二聚合物區域之高度係小於或等於互連結構之高度，及較佳地，係小於互連結構之高度。第4圖例示第3A圖之較佳積層結構之放大圖，其中相似的元件符號係指類似的元件。頂膜部分17係由彈性體頂膜層與緩衝層(PSA)組成。於第4圖中，聚合物層PL與頂膜部分17之總高度(h)係小於金屬柱65之高度。總高度h係充分地接近金屬柱65之高度，使得頂膜部分17係被金屬柱所變形但不會被金屬柱所刺穿。此種頂膜層中之變形稱作為凱佛特(Calvert)小丘(nubbin)，如18a、18b、及18c顯示。金屬柱65不會被積層方法變形或被頂 膜部分17變形。雖然不欲受理論所限，但相信頂膜部分17的可彎性，及特別頂膜部分17之緩衝層的可彎性允許此積層而不會實質上造成互連結構之變形。發明所屬技術領域具有通常知識者將瞭解當第一聚合物區域之高度使其覆蓋互連結構之頂部時，可減少凱佛特小丘之高度或甚至消除凱佛特小丘的存在。
本發明之底部填充結構可積層至多種基板。典型地，第1A圖之底部填充結構積層至具有互連結構之組件(主動裝置)，使得包含無機填料之第二聚合物區域係相鄰該組件表面。適合的組件包括但不限於，積體電路等。本底部填充結構可用於廣泛多種互連結構上，諸如焊料凸塊、金屬柱等。互連結構可由焊料組成，諸如於焊料凸塊之例，或由帶有可焊接帽的非焊料組成。用以形成焊料凸塊之焊料實例包括，但不限於，錫、錫-鉛、錫-銀、錫-鉍、錫-銅、錫-銀-銅等。金屬柱之實施例為銅柱。金屬柱具有可焊接帽部分，其中此可焊接帽可為任何適合的焊料。金屬柱也可包括一或多層金屬層，諸如配置於該金屬與可焊接帽層間之鎳層。取決於組件之設計，此等互連結構具有廣泛多種尺寸。適合的基板包括印刷電路板(PCB)、封裝基板等。舉例言之，覆晶可安裝於封裝基板上，及所得封裝體安裝於PCB上，或另外覆晶可直接安裝於PCB上。
於底部填充結構積層至表面之後，去除頂膜層連同任何視需要的緩衝層。於一個具體實施例中，底 部填充結構係積層至具有互連結構的組件，諸如第4圖所示。去除頂膜部分17之後，互連結構(金屬柱)65之上部係暴露於聚合物表面上方，諸如第4圖所示，以於組件55上提供預施用之底部填料。其次，該組件安裝至基板。第5A圖顯示得自第4圖之具有預施用之底部填料的組件之另一具體實施例，其中第二聚合物區域30具有小於金屬柱65之高度的高度，及其中第一聚合物區域20覆蓋金屬柱之頂部，及其中該組件被倒置及就緒準備妥安裝至基板80之表面上的傳導性接合墊85。互連結構65之頂部係對齊傳導性接合墊85，且互連結構65與傳導性接合墊85接觸，如第5A圖中之箭頭所示而形成單元。
第5B圖例示形成電氣總成之替代方法。於第5B圖中，得自第1B圖之底部填充結構已經積層至基板80，諸如電路板基板，於基板之表面上的傳導性接合墊85上方。去除頂膜之後，組件55表面上之互連結構65之頂面係對齊傳導性接合墊85，且如第5B圖中之箭頭所示接觸而形成單元。
於第5A圖及5B兩者中，聚合物層之第二區域30係與組件(主動裝置)相鄰，而具有較低無機填料含量，且較佳地不含無機填料之第一區域20係與具有傳導性接合墊的組件55相鄰。該組件之互連結構與安裝基板上的傳導性接合墊接觸而形成單元後，該單元係置於電氣連接互連結構與接合墊之條件下。此等條件包括，但不限於，熱超音波接合及加熱該單元，典型地施加壓力至組件、該 基板或兩者以至少部分地熔解互連結構，及電氣連接(焊接)互連結構至傳導性接合墊。於此加熱步驟期間，預施用之底部填料(聚合物層)進一步固化(聚合)。於本乾膜結構中使用相當薄的第一聚合物區域之優點為：在焊接(或熱超音波接合)步驟之後，形成整體(或單一)主體區域，亦即，第一及第二聚合物區域形成整體主體區域。雖然不欲受理論所限，但相信此種整體主體區域具有遍布主體之實質上均勻濃度之無機填料。亦即，整體主體區域實質上不含無機填料之濃度梯度，且較佳地不含此種濃度梯度。整體主體結構之形成至少部分地係借助於針對第一及第二聚合物區域選擇彼此可相容之聚合物。第6圖為本發明之底部填充結構之剖面顯微圖，顯示互連結構焊接至接合墊，該接合墊係由具有實質上均勻濃度之無機填料的整體主體底部填充材料所包圍。亦即，第6圖中並無可檢測之未經填充之聚合物區域。
對於組件妥善接線至基板具有關鍵性的底部填料之助熔性能可能因含量高之無機填料而被減弱。負責助熔的配方組件因高含量之無機填料之存在所致而濃度減低。又，顯著填料捕集可能出現在導電接點，導電接點係在接合過程期間因高濃度之無機填料而形成。由於無機填料為非傳導性，故此種捕集的填料可能嚴重衰減電氣效能。傳導性填料會造成非期望的短路發生。本底部填充結構解決了改良助熔議題，且減少了及較佳地不會出現使用習知底部填料辦法所遭逢的填料捕集問題。
實施例1-未經填充之聚合物材料之製備：於裝配有過頂攪拌器、溫度計及冷凝器之有夾套的3公升之反應器中加入2000.0公克之(11.3莫耳)雙酚A之二縮水甘油醚(DER 332，得自陶氏化學公司(Dow Chemical Company)，EEW：177)及545.7公克之丙二醇單甲基醚(PGME)。將溶液加熱至50℃，及允許攪拌10分鐘以確保徹底混合。於充分攪拌之後，以攪拌添加一份182.8公克(4.3莫耳)之1,8-薄荷烷二胺(普利明(Primine)MD，得自陶氏化學公司)，及將所得混合物加熱至100℃。一旦於100℃安定化之後，將混合物經攪拌1小時，隨後進一步將熱升高至130℃及允許材料又攪拌4小時。反應完成後，降低溫度，及將b-段聚合物滴至4公升之玻璃瓶內儲存。
於聚合反應之後，將15.98公克之雙酚A之二縮水甘油醚/普利美(Primene)MD/PGME b-段化聚合物加合物與12.23公克之酚系硬化劑(MEH 7851SS(OH當量重：210)，得自明和塑膠工業公司)，3.32公克之額外PGME及6.24公克之乙酸正丁酯組合。混合物於雙行星式混合器中以2000rpm旋轉5分鐘以徹底組合該等成分。於此混合物中添加0.17公克之流動添加劑(堤果流(Tegoflow)370)，0.75公克之韌化劑(BTA 753ER)，11.25公克之具有環氧官能基之軟化劑(EXA 4850-150，EEW：440)。所得材料再度於雙行星式混合器內以2000rpm旋轉5分鐘。最後，加入0.07公克之催化劑(六氟磷酸四丁基鏻)。所得材料再度於雙行星式混合器中以2000rpm旋轉2分鐘。此外，為了確保全 部成分皆完全分散於聚合物基體內，所得材料可通過三輥磨機兩次，製造自由流動的黏稠液體。
實施例2-未經填充之聚合物材料之製備：於玻璃小瓶中，添加0.28公克之助熔劑(1,4-二羥基2-羧基萘甲酸，得自蘇凱化學工業公司(Sugai Chemicals Industries))連同10公克之適合的溶劑(例如1,3-二氧雜環戊烷)。將玻璃小瓶振搖，直到助熔劑溶解於溶劑中。然後，將此溶液移至用以於高速混合機中混合之容器中。2.50公克之雙酚A之二縮水甘油醚(DER 332，得自陶氏化學公司，EEW：177)及3.28公克之EHGE-普利美MD加合物添加至容器中。為了製造EHGE-普利美MD加合物，將124.0份(0.66莫耳)之乙基己基縮水甘油基醚(EHGE)[得自赫席翁特用化學品公司(Hexion Specialty Chemicals)]於氮氣下及於周圍溫度攪動，添加至56.7份(0.33莫耳)之1,8-甲烷二胺(PMD，得自陶氏化學公司)。將混合物加熱至75℃歷時2小時，接著於140℃加熱歷時2小時。然後，將最終混合物於真空下(30毫米汞柱)於80℃又維持2小時以去除任何揮發物，而獲得產物PMD/EHGE加合物，如下式顯示。
含有1,4-二羥基2-羧基萘甲酸、1,3-二氧雜環戊烷、DER 332及EHGE-普利美MD加合物之混合物之容器載荷於高速混合機中，及於2000rpm混合3分鐘。然後，將混合物置於玻璃盤中，及送進設定於100℃之烤爐內歷時30分鐘至1小時以去除溶劑。然後從烤爐內移出玻璃盤，及以玻璃瓶收集混合物。
實施例3-未經填充之聚合物材料之製備：於玻璃小瓶中，添加0.76公克之助熔劑(1,4-二羥基2-羧基萘甲酸，得自蘇凱化學工業公司(Sugai Chemicals Industries))連同10公克之適合的溶劑(例如1,3-二)。將玻璃小瓶振搖，直到助熔劑溶解於該溶劑中。然後，將此溶液移至用以於高速混合機中混合之容器。將8.0公克之雙酚A之二縮水甘油醚(DER 332，得自陶氏化學公司，EEW：177)及6.35公克之烯丙基酚甲階酚醛清漆樹脂(MEH 8000H，得自明和塑膠工業公司)添加至容器。然後，將容器載荷於高速混合機中，及於2000rpm混合3分鐘。然後，將混合物置於玻璃盤中，及送進設定於100℃之烤爐內歷時30分鐘至1小時以去除溶劑。然後，從烤爐移出玻璃盤，及以玻璃瓶收集混合物。
實施例4-未經填充之聚合物材料之製備：各種未經填充之聚合物材料係經由重複實施例1之程序製備，但雙酚A係以表1中所列的一莫耳當量之二官能環氧單體置換。
實施例5-未經填充之聚合物材料之製備：各種未經填充之聚合物材料係經由重複實施例1之程序製備，但使用表2中報告的環氧單體、胺交聯劑及酚系硬化劑(得自明和塑膠工業公司)。
實施例6-經填充之聚合物材料之製備：於裝配有過頂攪拌器、溫度計及冷凝器之有夾套的3公升之反應器中加入2000.0公克(11.3莫耳)之雙酚A之二縮水甘油醚(DER 332，得自陶氏化學公司，EEW：177)及537.6公克之PGME。將此材料加熱至50℃，及允許攪拌10分鐘以確保徹底混合。於充分攪動之後，攪拌添加一份145.2公克(3.4莫耳)之1,8-薄荷烷二胺(普利明(Primine)MD，得自 陶氏化學公司)，及將所得混合物加熱至100℃。一旦於100℃安定化之後，混合物經攪拌1小時，隨後將熱進一步升高至130℃及允許材料又攪拌4小時。反應完成後，降低溫度，及將b-階聚合物滴至4升玻璃瓶內儲存。
於聚合反應之後，將7.72公克之雙酚A之二縮水甘油醚/普利美MD/PGME b-段聚合物加合物與5.95公克之酚系硬化劑(MEH 7851SS(OH當量重：210)得自明和塑膠工業公司)，5.92公克之額外PGME及7.46公克之乙酸正丁酯組合。將混合物於雙行星式混合器中以2000rpm旋轉5分鐘以徹底組合該等成分。於此混合物中添加0.22公克之流動添加劑(堤果流370)，0.92公克之韌化劑(BTA 753ER)，4.32公克之具有環氧官能基之軟化劑(EXA 4850-150，EEW：440)，及0.13公克之縮水甘油氧基三甲氧基矽烷。所得材料再度於雙行星式混合器內以2000rpm旋轉5分鐘。於此混合物中添加27.27公克之熔合二氧化矽，及將所得混合物於雙行星式混合器中以2000rpm旋轉10分鐘。於溶劑去除之後，以固體為基準，二氧化矽之含量為60wt%。最後，加入0.09公克之催化劑(六氟磷酸四丁基鏻)。所得材料再度於雙行星式混合器中以2000rpm旋轉2分鐘。為了確保二氧化矽完全分散於聚合物基體內，所得材料通過三輥磨機兩次，製造自由流動的黏稠液體，大半不含粒子聚集體。
實施例7-經填充之聚合物之製備：藉由重複實施例6之程序，但係使用表3中報告的環氧單體、胺 交聯劑及酚系硬化劑(得自明和塑膠工業公司)而製備各種經填充之聚合物材料。
實施例8-經填充之聚合物材料之製備：藉由重複實施例6及7之程序但，係以表4中報告之用量使用下列填料而製備各種經填充之聚合物材料。
實施例9-底部填充結構之製備：得自實施例6之填充聚合物料係使用狹縫模具於PET載膜(底膜)上塗覆。此塗覆層以110℃峰溫通過多階段式烤爐以逐出溶劑而獲得乾膜。然後，得自實施例1之未經填充之聚合物材料係使用經選擇以達成期望膜厚度之下拉桿而施用至經填充之聚合物材料上。然後，將此總成置於習用烤爐中，及暴露於110℃峰溫之多步驟式乾燥法以驅逐去除未經填充之聚合物材料中之溶劑。然後，此總成係使用熱輥層合機，以未經填充之聚合物材料黏著至背研膠帶上的黏著層而積層至具有PSA層之背研膠帶(頂膜層)。將PET載膜(底膜)撕離，及使用真空層合機將經填充之聚合物材料之暴露表面積層至晶圓上。
實施例10-底部填充結構之製備：重複實施例9之程序，但係使用實施例2之未經填充之聚合物。
實施例11-底部填充結構之製備：重複實施例9之程序，但係使用實施例3之未經填充之聚合物。
17‧‧‧頂膜部分
18a、18b、18c‧‧‧凱佛特小丘
20‧‧‧第一聚合物區域、第一區域
30‧‧‧第二聚合物區域、第二區域
55‧‧‧組件表面
65‧‧‧金屬柱
PL‧‧‧聚合物層

Claims (14)

  1. 一種底部填充結構，依序地包含：頂膜層；聚合物層；及底膜層，其中該聚合物層包含第一聚合物區域及第二聚合物區域，其中該第二聚合物區域包含無機填料。
  2. 如申請專利範圍第1項所述之底部填充結構，其中，該第二聚合物區域進一步包含包含可固化聚合物、交聯劑、及固化劑之層。
  3. 如申請專利範圍第1項所述之底部填充結構，其中，以該第二聚合物區域之總重為基準，該無機填料係以40wt%之含量存在於該第二聚合物區域。
  4. 如申請專利範圍第1項所述之底部填充結構，其中，該頂膜層與該聚合物層間設置有黏著劑層。
  5. 如申請專利範圍第1項所述之底部填充結構，其中，該頂膜層係由彈性體組成。
  6. 如申請專利範圍第1項所述之底部填充結構，其中，該頂膜層為選自於聚烯烴類、聚酯類、聚胺基甲酸酯類、聚(氯乙烯)、聚(偏-氯亞乙烯)、乙烯基乙酸乙烯酯、及聚(甲基)丙烯酸酯類中之一種聚合物。
  7. 如申請專利範圍第1項所述之底部填充結構，其中，該底膜層係選自於聚酯、聚醯胺、聚醯亞胺、聚烯烴、聚丙烯酸酯、聚胺基甲酸酯、及金屬。
  8. 如申請專利範圍第1項所述之底部填充結構，其中，該第一聚合物區域包含可固化聚合物、交聯劑、及固化劑。
  9. 如申請專利範圍第8項所述之底部填充結構，其中，該第一聚合物區域進一步包含無機填料，該無機填料之含量係小於該第二聚合物區域中之該無機填料之含量。
  10. 如申請專利範圍第8項所述之底部填充結構，其中，該第一聚合物區域不含無機填料。
  11. 一種方法，包含：提供如申請專利範圍第1項所述之底部填充結構；從該底部填充結構去除該底膜；積層該底部填充結構至其上具有複數個互連結構之組件之表面，使得該底部填充結構係被壓在複數個互連結構間，其中該第二聚合物區域之高度係小於或等於該互連結構之高度；及去除該頂膜層。
  12. 如申請專利範圍第11項所述之方法，進一步包含：將該等互連結構之頂部與於基板之表面上的複數個傳導性接合墊對齊以形成單元；及使得該等互連結構電氣連接該等互連結構與該等傳導性接合墊。
  13. 一種方法，包含：提供前述該底部填充結構；從該底部填充結構去除該底膜；積層該底部填充結構至具有複數個傳導性接合墊之基板的表面，使得該第一聚合物區域係直接位在該基板之該表面上方；及去除該頂膜層。
  14. 如申請專利範圍第13項之方法，進一步包含：將該等 傳導性接合墊與於組件之表面上的複數個互連結構對齊以形成單元；及加熱該單元以熔解該等互連結構而電氣連接該等互連結構與該等傳導性接合墊。
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