TW201521187A - 用於降低電晶體陣列中之寄生漏電之技術 - Google Patents

用於降低電晶體陣列中之寄生漏電之技術 Download PDF

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TW201521187A
TW201521187A TW103134869A TW103134869A TW201521187A TW 201521187 A TW201521187 A TW 201521187A TW 103134869 A TW103134869 A TW 103134869A TW 103134869 A TW103134869 A TW 103134869A TW 201521187 A TW201521187 A TW 201521187A
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conductor
conductors
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transistors
drain
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Stephan Riedel
David Gammie
Boon Hean Pui
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Abstract

一種操作一裝置之方法，該裝置係包含：一第一導體層，其界定複數個源極導體，其各與一各別群組的電晶體相聯結，及複數個汲極導體，其各與一各別電晶體相聯結；一半導體層，其界定該等源極與汲極導體之間的半導體通路；一第二導體層，其界定複數個閘極導體，其各與一各別組的電晶體相聯結，及一或多個儲存電容器導體，其電容性耦合至汲極導體以供一各別組的電晶體用；該方法係包含：使用閘極導體以將電晶體切換於接通與關斷狀態之間；及使用儲存電容器導體以降低一或多個半導體層的導電率(conductivity)，其在接通狀態中將各電晶體的汲極導體連接至除了與該電晶體相聯結者外的源極及/或汲極導體。

Description

用於降低電晶體陣列中之寄生漏電之技術
本發明係有關用於降低電晶體陣列中之寄生漏電之技術。
具增加密度(每單位面積的電晶體數)的電晶體陣列例如係用來生產日益增高解析度的顯示裝置。已經觀察到：例如用於控制顯示裝置之電晶體陣列的效能係會受到經由提供電晶體用的半導通路之半導體層未與相同電晶體相聯結的導體之間的漏電流所影響。
一旨在降低如是漏電流之技術係涉及將半導體層圖案化藉以消除或降低未與相同電晶體相聯結的導體之間的半導層中之漏電路徑。
發明人已經認識到在提供一用於將半導體層圖案化的需求予以降低抑或消除以降低寄生漏電流之替代性技術時所面臨的挑戰。
本文據此提供一操作一包含一陣列的電晶體之裝置之方法，其中該裝置係包含：一第一導體層，其界定複數個源極導體，各源極導體與一各別群組的電晶體相聯 結，及複數個汲極導體，其各與一各別電晶體相聯結；一半導體層，其界定該等源極與汲極導體之間的半導體通路以供該陣列的電晶體用；一第二導體層，其界定複數個閘極導體，其各與一各別組的電晶體相聯結，及一或多個儲存電容器導體，其電容性耦合至汲極導體的至少一部分以供一各別組的電晶體用；其中該方法係包含：使用閘極導體以將電晶體切換於接通與關斷狀態之間；及使用儲存電容器導體以降低半導體層的一或多個部分之導電率(conductivity)，其在接通狀態中將各電晶體的汲極導體連接至除了與該電晶體相聯結者外的源極及/或汲極導體。
根據一實施例，各汲極導體係包含一由一線導體被連接至一汲極電極之墊導體，且其中該一或多個儲存電容器導體係組構以在各墊導體的周邊處重疊於半導體層之一周邊部分的整體。
亦據此提供一包含一陣列的電晶體之裝置，其中該裝置包含一第一導體層，其界定複數個源極導體，各源極導體與一各別群組的電晶體相聯結，及複數個汲極導體，其各與一各別電晶體相聯結；及一半導體層，其提供半導體通路以供該陣列的電晶體用；其中各源極導體係組構以經由半導體層設置於與該源極導體相聯結之群組的汲極導體與所有其他源極導體之間的所有傳導路徑之間。
根據一實施例，與一源極導體相聯結之群組的汲極導體係延伸於一第一方向，且各源極導體係包含在與源極導體相聯結之群組的汲極導體之相對側上延伸於該第一 方向之兩個線導體。
根據一實施例，各源極導體係包含進一步的導體，其在與源極導體相聯結之汲極導體之間的區中連接該等兩個線導體。
根據一實施例，裝置進一步包含複數個閘極導體，各閘極導體係電容性耦合至用於一各別組的電晶體之半導通路，且亦電容性耦合至用於具有電容性耦合至一相鄰閘極導體的半導通路之另一組的電晶體之汲極導體的一部分；且其中各源極導體包含在與相同源極導體相聯結之相同群組的電晶體中延伸於相鄰電晶體的汲極導體之間的一或多個部分。
根據一實施例，各源極導體係整體地涵蓋與源極導體相聯結的汲極導體。
亦據此提供一用於操作一包含一陣列的電晶體之裝置之裝備，其中該裝置係包含：一第一導體層，其界定複數個源極導體，各源極導體與一各別群組的電晶體相聯結，及複數個汲極導體，其各與一各別電晶體相聯結；一半導體層，其界定該等源極與汲極導體之間的半導體通路以供該陣列的電晶體用；一第二導體層，其界定複數個閘極導體，其各與一各別組的電晶體相聯結，及一或多個儲存電容器導體，其電容性耦合至汲極導體的至少一部分以供一各別組的電晶體用；其中該裝備係組構以將不同電壓施加至閘極導體以使電晶體切換於接通與關斷狀態之間；及進一步組構以將一電壓施加至儲存電容器導體，其 係降低半導體層的一或多個部分之導電率(conductivity)，其在接通狀態中將各電晶體的汲極導體連接至除了與該電晶體相聯結者外的源極及/或汲極導體。
根據一實施例，各汲極導體係包含一由一線導體被連接至一汲極電極之墊導體，且其中該一或多個儲存電容器導體係組構以在各墊導體的周邊處重疊於半導體層之一周邊部分的整體。
2,4,40,42,62,62a,62b‧‧‧源極導體
2a,2b,4a,4b‧‧‧導體線
2c,4c‧‧‧連接部分
6,8,10,12,44,46,48,50,64‧‧‧汲極導體
6a,6b,6c,6d,44a,46a,48a,50a‧‧‧汲極墊導體
6c,8c,10c,12c,44b,46b‧‧‧汲極電極部分
14‧‧‧傳導性間層互連件
16‧‧‧閘極線導體
18‧‧‧COM線導體
20‧‧‧孔
26,36‧‧‧半導體層
28‧‧‧閘極介電層
30‧‧‧絕緣體層
32‧‧‧像素電極
40a,40b,42a,42b‧‧‧線導體
40c,42c‧‧‧隔離部分
52,60a,60b,60c‧‧‧閘極導體
54,68‧‧‧間層互連件
60‧‧‧閘極線
64a-64f‧‧‧實質圓形島導體
70‧‧‧往內徑向突部
72‧‧‧往外徑向延伸的突部
74,76‧‧‧交錯狀指
80‧‧‧驅動器積體電路(IC)
82‧‧‧邏輯區塊
84‧‧‧記憶體區塊
86‧‧‧閘極驅動器區塊
88‧‧‧源極驅動器區塊
100‧‧‧高電壓產生器
L‧‧‧通路長度
W‧‧‧半導通路的長度
本發明的實施例係參照附圖僅藉由範例詳細地描述於下文，其中：圖1顯示用於根據本發明的一實施例之一電晶體陣列的源極及汲極導體之一組態，並顯示用於根據本發明的一實施例之一電晶體陣列的儲存電容器導體之一組態；圖2顯示經過圖1的線A-A之橫剖面；圖3至10顯示用於根據本發明的其他實施例之一電晶體陣列的源極及汲極導體之其他組態；及圖11示意性顯示用於控制被施加至圖1至10任一者中的源極及汲極導體之電壓之裝備，及用於產生被施加至圖1及2中的共同電極線之電壓之裝備。
電晶體陣列係可包含一經圖案化的導體層，其界定：一陣列的獨立源極導體及一陣列的獨立汲極導體。各源極導體界定用於一各別直行的電晶體之源極電極，並在該陣列的邊緣處提供各別線的電晶體之各電晶體之間的一 傳導性連接。各汲極導體係界定用於一各別電晶體的汲極電極。汲極導體亦可提供相對大面積導體墊，其形成與電晶體陣列的其他傳導元件之儲存電容器，諸如共同電極(COM)線。電晶體陣列可進一步包含一有機半導體層，其提供源極導體與汲極導體之間的半導通路。電晶體陣列可進一步包含另一經圖案化的導體層，其界定一陣列的閘極導體，各閘極導體係界定用於一個別橫列的電晶體(其中一橫列係表示在實質地垂直於上述電晶體直行的一方向作延伸之一線的電晶體)之閘極電極。一操作電晶體陣列的方法係可包含將一接通電壓依順序施加至閘極導體的各者(同時將一關斷電壓施加至所有其他閘極導體)；且同時一閘極導體係為“接通”，將各別電壓施加至源極導體以在與“接通”閘極導體相聯結之橫列的電晶體中於電晶體的汲極導體處達成所欲電位。理想上，當一閘極導體“接通”時被施加至任何源極導體的電壓係並未實質地影響與其他“關斷”閘極導體相聯結之電晶體及/或與相同“接通”閘極導體相聯結但與不同源極導體相聯結之電晶體的汲極導體處之電位。
圖1及2顯示用於更良好地隔離任何電晶體以及與不同源極及/或閘極導體相聯結的電晶體之技術的兩範例。
圖1示意性顯示由一半導體層26及一閘極介電層28所分隔之一電晶體陣列的兩個導體層之圖案化，其中半導體層26提供電晶體的半導通路，閘極介電層28將閘極導 體電容性耦合至半導通路。一下經圖案化的導體層係經由一平面化層24被形成於一基材(諸如一塑膠基材，例如PEN或PET)上。下經圖案化導體層係界定一組的源極導體2、4及一組的汲極導體6、8、10、12。
上導體層係界定以交替順序作配置之一組的閘極線導體16、及一組的COM線導體18。閘極導體16係重疊(經由閘極介電層28)於用以在其彼此緊鄰處連接源極及汲極導體之半導體層的部分。
用於一各別電晶體之各汲極導體係包含：(a)最緊鄰(典型小於約20微米)於與電晶體相聯結的源極導體之一汲極電極部分6c、8c、10c、12c；(b)一汲極墊導體6a、6b、6c、6d，其提供一相對大面積導體以供與COM導體18的一者作良好電容性耦合；及(c)一狹窄線導體，其將汲極電極連接至汲極導體墊。
傳導性間層互連件14將各汲極墊導體(經由鋪設的COM線導體中之一各別孔20)連接至被經由一絕緣體層30鋪設於上經圖案化導體層上之另一經圖案化的導體層所界定之一各別的像素電極32。像素電極32可例如用來控制一電泳光學顯示媒體(未圖示)的各別像素部分之輸出。
各COM線導體18係組構以整體地重疊於用於一各別橫列的電晶體之汲極墊導體，且亦重疊於涵蓋汲極墊導體的周邊之半導體層的周邊部分之整體。根據本發明的一實施例之電晶體陣列的操作係涉及將一經由一場效應顯著地降低半導體層26的埋設部分的電導之電壓同時地施加 至所有COM線導體18(包括在一接通狀態中相鄰於任何閘極線導體之COM線導體)。根據一範例，被施加至COM線導體之電壓係與被施加至閘極線導體之“關斷”電壓為相同。半導體層的這些部分之電導的此降低係用來更良好地隔離一電晶體的汲極導體以及(a)除與該電晶體相聯結者外之源極導體，以及亦包括(b)用於與相同源極導體(但與一不同閘極導體)相聯結的其他電晶體之汲極導體。在此範例中，隨著閘極線16依順序被“接通”，一“關斷”電壓係同時被連續施加至所有COM線18。
尚且，各源極導體係包含(a)兩個導體線2a、2b、4a、4b，其(i)平行地延伸於與源極導體相聯結的電晶體之汲極導體的相對側上，及(ii)在電晶體陣列的邊緣處被連接至相同的各別終端；及(b)連接部分2c、4c，其用以在與源極導體相聯結之電晶體的汲極導體之間的區中連接兩導體線。在圖1及2所示的簡單範例中，連接部分2c、4c亦為最緊鄰於汲極導體之源極導體的部分(源極電極部分)。藉由將各源極導體設置成各別直行的電晶體之汲極導體任一側上的兩導體線係用來更良好地隔離那些汲極導體以及與其他直行的電晶體相聯結之源極導體。更詳細來說，源極導體的此組態係可例如藉由降低從汲極導體至以一不同電壓被驅動的一鄰近源極導體(亦即用於一鄰近直行的電晶體之一源極導體)之電荷洩漏而導致汲極導體更良好地充電至所欲的電位(例如諸如將一電泳顯示媒體的各別像素部分切換至一不同狀態所需要之電位)。
尚且，藉由將用於一各別直行的電晶體之各源極導體設置成為在陣列邊緣處被連接至相同終端且被連接部分2c、4c以間隔連接至彼此之兩平行線導體係具有下列額外優點：即使在兩源極線導體有一者失效之事件中，該直行的電晶體各者之源極電極在陣列的邊緣處仍連接至各別源極終端。
圖3示意性顯示用於使汲極導體隔離於彼此之一替代性技術。圖3的電晶體陣列之部份特徵係在於與閘極導體52相同程度地缺乏COM線導體。取而代之，藉由對於各電晶體組構汲極導體44、46、48、50使其包含一被電容性耦合至與該電晶體相聯結的閘極導體相鄰之一閘極導體之汲極墊導體(44a、46a、48a、50a)，而達成所需要的儲存電容。對於各電晶體的汲極導體墊係經由一線導體被連接至最緊鄰(亦即小於約20微米)於源極導體40之一汲極電極部分44b、46b。類似於圖1及2所示的配置，間層互連件54將汲極墊導體經由閘極線導體52中的一各別孔連接至一個別鋪設的像素導體。
在圖3中，用於各直行的電晶體之源極導體40、42係包含平行延伸於與源極導體相聯結之各別直行的電晶體的相對側上之兩線導體(40a及40b、42a及42b)。此配置係用來更良好地隔離各汲極導體以及與相鄰直行的電晶體相聯結之源極導體。
在圖3中，用於一各別直行的電晶體之各源極導體40係組構以具有隔離部分40c，其延伸於(i)具有與一閘極 導體52電容性耦合的一半導通路之一電晶體的汲極電極部分44b、46b、以及(ii)與相同閘極導體電容性耦合之汲極導體墊(用於相同直行的電晶體中之一相鄰電晶體)之間。這些隔離部分40c係在供直行的電晶體延伸之方向實質地延伸於汲極導體墊的整體長度；並用來更良好地隔離該直行的電晶體中之各汲極導體以及相同直行的電晶體中之相鄰汲極導體。
圖4示意性顯示的組態係與圖3所示者相同，差異在於：隔離部分40c、42c從與用以界定源極電極部分的源極線呈相對之兩源極線導體的一者、亦即最緊鄰於汲極導體之源極導體的部分作延伸。
在圖5示意性顯示的配置中：一下圖案化導體層再度界定用於該陣列的電晶體之源極及汲極導體；但用於各個各別直行的電晶體之源極導體係組構成為用以界定用於各電晶體的一實質圓形孔之相對寬線導體62a、62b；且用於各電晶體的汲極導體係被界定成一實質圓形島導體64a-64f，其整體地設置於各別孔內並被定心於各別孔的中心。圖5的對角散線(diagonal hashing)顯示出對於各電晶體之環狀半導通路的區位。間層互連件68提供經由閘極導體60a、60b、60c中的各別孔從汲極導體64至一各別鋪設的像素導體(未圖示)之傳導性連接。圖5所示的配置亦用來更良好地隔離汲極導體墊以及(a)與相同源極導體相聯結之相鄰的汲極導體(亦即相同直行的電晶體中之電晶體的汲極導體)及(b)與相鄰直行的電晶體相聯結之源極導體。
圖6示意性顯示對於圖5所示者之一類似配置，差異在於其採用角度性結構。源極導體62係界定實質正方形或矩形孔，且實質正方形或矩形源極導體各被整體地設置於一各別孔內。
圖7示意性顯示的配置係與圖5示意性顯示者相同，差異在於汲極導體以及源極導體62a、62b中的孔皆組構以增大電晶體的W：L比值；其中L係為通路長度(亦即源極與汲極導體之間的最短距離)，且W係為其中源極及汲極導體被此最短距離所分隔之半導通路的長度。在圖6中，藉由將島汲極導體及用以界定孔之源極導體的部分作圖案化使得導汲極導體包括延伸至由源極導體界定的類似往內徑向突部70所界定的空間中之往外徑向延伸的突部72，而增大W：L比值。
圖8示意性顯示的配置係與圖7示意性顯示者相同，差異在於導汲極導體及源極導體62a62b中的孔皆具有一實質正方形或矩形，而非一實質圓形的形狀。利用與圖8相同的方式藉由源極及汲極導體的邊緣處之互補突部達成W：L比值的增大。
圖9及10示意性顯示的配置係類似於圖5至8所顯示者，差異在於：藉由將島汲極導體及源極導體作圖案化使得兩者導體皆界定主要延伸於島汲極導體中心周圍之交錯狀指74、76，而達成W：L比值的增大。
在圖5至10所示的各配置中，各汲極導體係經由間層互連件68被連接至一各別像素導體；且不同於圖1及3 所示的配置，與各TFT相聯結的像素導體係具有直接設置於閘極線上方之至少一部分，其用來控制該TFT的半導通路之電導(例如接通與關斷狀態之間)。為了實質地消除用於各TFT的像素導體與閘極導體之間的任何電容性耦合，一傳導性篩網層(未圖示)係設置於用以界定閘極線60之傳導層與一用以界定該陣列的像素導體之頂傳導層之間。篩網層係為一實質連續層，差異在於其界定用於汲極導體與各別像素導體之間的間層互連件68之孔。
半導體層36可為一連續未圖案化的層，其延伸於電晶體陣列的整體足跡上方，或者上述技術可與半導體層的一些圖案化作組合使用。例如，半導體層可利用用以界定閘極導體線及/或COM導體線之導體層作為一罩幕藉由雷射燒蝕被圖案化。在任一實例中，上述技術可以半導體層的較少或毫無圖案化達成至少相同程度的隔離(寄生漏電路徑之降低)。當另行例如藉由雷射燒蝕進行半導體層的圖案化時，半導體層26需要較少或毫無圖案化係可具有產生較少的有害碎屑或是橫越電晶體陣列的隔離量而言呈現較小變異之優點。尚且，在一頂閘極電晶體陣列的實例中，完全消除半導體圖案化步驟係會具有縮短半導體沉積與鋪設閘極介電質沉積之間的等待時間之優點。此等待時間的降低係會藉由降低半導體層的臨界部份(亦即形成與閘極介電層的臨界介面之部份)潛在地曝露於有害碎屑、濕氣或空器之時間長度而導致更好效能。
圖11顯示用於控制被施加至源極導體及閘極導 體的電壓之裝備的一範例。該裝備係包括一驅動器積體電路(IC)80。單晶片驅動器IC 80係包含一閘極驅動器區塊86，一源極驅動器區塊88，一邏輯區塊82及一記憶體區塊84。邏輯區塊82的功能係包括：驅動器IC 80與一主處理單元(MPU)之間的介面作用；將資料轉移至及轉移自記憶體84；協調閘極及源極驅動器區塊施加至閘極及源極導體之信號；及控制輸出資料至源極驅動器之轉移。驅動器IC 80可包括其他區塊。圖11亦示意性顯示一高電壓產生器100，其用於產生一共同“關斷”電壓以供同時施加至圖1及2的裝置中之所有COM線18。在此範例中，COM線18直接從高電壓功率產生器被驅動。
除了上文明述的修改外，熟悉該技藝者將瞭解可在本發明的範圍內作出所描述實施例的不同其他修改。
申請人據此獨立地揭露本文所描述的各個個別特徵以及二或更多個如是特徵的任何組合，只要如是特徵或組合能夠整體鑑於熟悉該技藝者的常見一般知識以本說明書為基礎被實行即可，而無關乎如是特徵或特徵的組合是否解決本文所揭露的任何問題，且不限於申請專利範圍的範疇。申請人係表明本發明的範圍可由任何如是個別特徵或特徵的組合所組成。
2a,2b,4a,4b‧‧‧導體線
2c,4c‧‧‧連接部分
8,10,12‧‧‧汲極導體
6a,6b,6c‧‧‧汲極墊導體
6c,10c,12c‧‧‧汲極電極部分
14‧‧‧傳導性間層互連件
16‧‧‧閘極線導體
18‧‧‧COM線導體
20‧‧‧孔

Claims (9)

  1. 一種操作一包含一陣列的電晶體之裝置之方法，其中該裝置係包含：一第一導體層，其界定複數個源極導體，各源極導體與一各別群組的電晶體相聯結，及複數個汲極導體，其各與一各別電晶體相聯結；一半導體層，其界定該等源極與汲極導體之間的半導體通路以供該陣列的電晶體用；一第二導體層，其界定複數個閘極導體，其各與一各別組的電晶體相聯結，及一或多個儲存電容器導體，其電容性耦合至該等汲極導體的至少一部分以供一各別組的電晶體用；其中該方法係包含：使用該等閘極導體以將該等電晶體切換於接通與關斷狀態之間；及使用該等儲存電容器導體以降低該半導體層的一或多個部分之導電率(conductivity)，其在該接通狀態中將各電晶體的該汲極導體連接至除了與該電晶體相聯結者外的源極及/或汲極導體。
  2. 如請求項1之方法，其中各汲極導體係包含一由一線導體被連接至一汲極電極之墊導體，且其中該一或多個儲存電容器導體係組構以在各墊導體的周邊處重疊於該半導體層之一周邊部分的整體。
  3. 一種包含一陣列的電晶體之裝置，其中該裝置包含一第一導體層，其界定複數個源極導體，各該等源極導體與一各別群組的電晶體相聯結，及複數個汲極導體，其各與一各別電晶體相聯結；及一半導體層，其提供半導體 通路以供該陣列的電晶體用；其中各源極導體係組構以經由該半導體層設置於與該源極導體相聯結之該群組的汲極導體與所有其他源極導體之間的所有傳導路徑之間。
  4. 如請求項3之裝置，其中與一源極導體相聯結之該群組的汲極導體係延伸於一第一方向，且各源極導體係包含在與該源極導體相聯結之該群組的汲極導體之相對側上延伸於該第一方向之兩個線導體。
  5. 如請求項4之裝置，其中各源極導體係包含進一步的導體，其在與該源極導體相聯結之汲極導體之間的區中連接該等兩個線導體。
  6. 如請求項4之裝置，其中該裝置進一步包含複數個閘極導體，各閘極導體係電容性耦合至用於一各別組的電晶體之該等半導通路，且亦電容性耦合至用於具有電容性耦合至一相鄰閘極導體的半導通路之另一組的電晶體之該等汲極導體的一部分；且其中各源極導體包含在與該相同源極導體相聯結之該相同群組的電晶體中延伸於相鄰電晶體的該等汲極導體之間的一或多個部分。
  7. 如請求項3之裝置，其中各源極導體係整體地涵蓋與該源極導體相聯結的該等汲極導體。
  8. 一種用於操作一包含一陣列的電晶體之裝置之裝備，其中該裝置係包含：一第一導體層，其界定複數個源極導體，各源極導體與一各別群組的電晶體相聯結，及複數個汲極導體，其各與一各別電晶體相聯結；一半導體 層，其界定該等源極與汲極導體之間的半導體通路以供該陣列的電晶體用；一第二導體層，其界定複數個閘極導體，其各與一各別組的電晶體相聯結，及一或多個儲存電容器導體，其電容性耦合至該等汲極導體的至少一部分以供一各別組的電晶體用；其中該裝備係組構以將不同電壓施加至該等閘極導體以使該等電晶體切換於接通與關斷狀態之間；及進一步組構以將一電壓施加至該等儲存電容器導體，其係降低該半導體層的一或多個部分之導電率(conductivity)，其在該接通狀態中將各電晶體的該等汲極導體連接至除了與該電晶體相聯結者外的源極及/或汲極導體。
  9. 如請求項8之裝備，其中各汲極導體係包含一由一線導體被連接至一汲極電極之墊導體，且其中該一或多個儲存電容器導體係組構以在各墊導體的周邊處重疊於該半導體層之一周邊部分的整體。
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