TW201430973A - 用於具有晶粒對中介層晶圓第一接合的半導體裝置封裝的方法和系統 - Google Patents

用於具有晶粒對中介層晶圓第一接合的半導體裝置封裝的方法和系統 Download PDF

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TW201430973A
TW201430973A TW102141435A TW102141435A TW201430973A TW 201430973 A TW201430973 A TW 201430973A TW 102141435 A TW102141435 A TW 102141435A TW 102141435 A TW102141435 A TW 102141435A TW 201430973 A TW201430973 A TW 201430973A
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Taiwan
Prior art keywords
interposer
die
wafer
interposer wafer
bonding
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TW102141435A
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TWI575621B (zh
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Michael G Kelly
Ronald Patrick Huemoeller
Won-Chul Do
David Jon Hiner
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Amkor Technology Inc
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Abstract

用於一具有一晶粒至中介層晶圓第一接合的半導體裝置封裝之方法及系統係被揭示，並且可包含接合複數個包括電子裝置的半導體晶粒至一中介層晶圓，以及在該晶粒與該中介層晶圓之間施加一種底膠填充材料。一種模製材料可被施加以囊封該晶粒。該中介層晶圓可被薄化以露出直通矽晶穿孔(TSV)，並且金屬接點可被施加至該露出的TSV。該中介層晶圓可被單一化以產生包括該半導體晶粒以及一中介層晶粒的組件。該晶粒可利用一黏著膜而被置放在該中介層晶圓上。該中介層晶圓可利用下列的一或多個而被單一化：一雷射切割製程、反應性離子蝕刻、一鋸開技術、以及一電漿蝕刻製程。該晶粒可利用一質量回焊或是一熱壓縮製程而被接合至該中介層晶圓。

Description

用於具有晶粒對中介層晶圓第一接合的半導體裝置封裝的方法和系統 【相關申請案之交互參照/納入參考】
此申請案係參考到2012年11月15日申請的美國申請案序號13/678,046(代理人文件編號25032US01)、2012年11月15日申請的美國申請案序號13/678,058(代理人文件編號25031US01)、以及2012年11月15日申請的美國申請案序號13/678,012(代理人文件編號25963US01)。
以上所引用的申請案的每一個茲在此以其整體納入作為參考。
本發明的某些實施例係有關於半導體晶片封裝。更明確地說，本發明的某些實施例係有關於一種用於具有晶粒至中介層晶圓第一接合的半導體裝置封裝之方法及系統。
半導體封裝係保護積體電路或晶片免於物理性損壞以及外部的應力。此外，其可以提供一導熱路徑以有效率地移除在一晶片中所產生的熱，並且例如亦提供電連接至其它例如是印刷電路板的構件。用於半導體封裝的材料通常包括陶瓷或塑膠，並且外觀形狀尺寸已經從陶瓷扁平封裝及雙排型封裝進步到尤其是針柵陣列及無引線的晶片載體封裝。
透過此種系統與如同在本申請案的其餘部分中參考圖式所闡述的本發明比較，習知及傳統的方法的進一步限制及缺點對於具有此項技術的技能者而言將會變成是明顯的。
本發明的一態樣為一種用於半導體封裝之方法，該方法係包括：接合包括電子裝置的複數個半導體晶粒至一中介層晶圓；在該複數個半導體晶粒以及該中介層晶圓之間施加一底膠填充材料；施加一模製材料以囊封該複數個半導體晶粒；薄化該中介層晶圓以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；單一化該中介層晶圓以產生分別包括該複數個半導體晶粒中的一或多個以及一中介層晶粒的複數個組件；以及接合該複數個組件中的一或多個至一或多個封裝基板。
本發明的另一態樣為一種用於半導體封裝之方法，該方法係包括：在一晶粒至中介層晶圓第一接合製程中產生一半導體封裝，該製程包括：接合包括電子裝置的複數個半導體晶粒至一中介層晶圓的一正面側；在該複數個半導體晶粒以及該中介層晶圓之間施加一底膠填充材料；施加一模製材料以囊封該複數個半導體晶粒；薄化該中介層晶圓以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；單一化該中介層晶圓以產生分別包括該複數個半導體晶粒中的一或多個以及一中介層晶粒的複數個組件；以及接合該複數個組件中的一或多個至一或多個封裝基板。
本發明的另一態樣為一種用於半導體封裝之方法，該方法係包括：在一晶粒至中介層晶圓第一接合的製程中產生一半導體封裝，該製程包括：接合包括電子裝置的複數個半導體晶粒至一中介層晶圓的一正面 側；在該複數個半導體晶粒以及該中介層晶圓之間施加一底膠填充材料；施加一模製材料以囊封該複數個半導體晶粒；薄化該中介層晶圓以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；利用一電漿蝕刻製程來單一化該中介層晶圓，以產生分別包括該複數個半導體晶粒中的一或多個以及一中介層晶粒的複數個組件；以及接合該複數個組件中的一或多個至一或多個封裝基板。
100‧‧‧封裝
101‧‧‧晶粒
103‧‧‧封裝基板
105‧‧‧被動元件
107‧‧‧中介層
109‧‧‧微凸塊
111‧‧‧焊料球
113‧‧‧蓋子
115‧‧‧直通矽晶穿孔(TSV)
117‧‧‧背面凸塊
118‧‧‧熱介面材料
119‧‧‧墊
121‧‧‧動態隨機存取記憶體(DRAM)(晶粒)
123‧‧‧金屬互連
125‧‧‧底膠填充材料
127‧‧‧中介層
129‧‧‧黏著層
131‧‧‧金屬墊
150‧‧‧封裝
201‧‧‧中介層晶圓
201A‧‧‧中介層晶粒
203A-203C‧‧‧晶粒
205‧‧‧微凸塊
207‧‧‧直通矽晶穿孔(TSV)
209‧‧‧前側墊
210‧‧‧底膠填充材料
211‧‧‧模製材料
213‧‧‧背面凸塊
215‧‧‧封裝基板
219‧‧‧接觸墊
221‧‧‧蓋子
225‧‧‧黏著劑
227‧‧‧焊料球
301A、301B、303、305、307、309、311、313、315‧‧‧步驟
401‧‧‧晶舟
403‧‧‧夾子
405‧‧‧晶粒
407‧‧‧中介層
501‧‧‧晶舟
505‧‧‧晶粒
507‧‧‧中介層
509‧‧‧真空密封環
511‧‧‧真空通道
513‧‧‧閥
515‧‧‧真空源
601‧‧‧載體晶圓
603‧‧‧晶圓
605‧‧‧背面凸塊
607‧‧‧聚合物層
609A‧‧‧頂端夾頭
609B‧‧‧底部夾頭
611‧‧‧膜框架
701‧‧‧頂端晶粒
703‧‧‧微凸塊
705‧‧‧底部晶粒
707‧‧‧接觸墊
709‧‧‧底膠填充層
圖1A是描繪根據本發明的一範例實施例的一種被配置有一晶粒到晶圓第一接合之積體電路封裝之概要圖。
圖1B是描繪根據本發明的一範例實施例的一種被配置有一晶粒至中介層晶圓第一接合以及堆疊的晶粒的積體電路封裝之概要圖。
圖1C-1E係描繪根據本發明的一範例實施例的用於利用一黏著膜來接合多個晶粒的範例步驟。
圖2A-2F係描繪在根據本發明的一範例實施例的一種晶粒至中介層晶圓第一接合結構中的範例步驟。
圖3是描繪在根據本發明的一範例實施例的一種晶粒至中介層晶圓第一接合製程中的範例步驟之概要圖
圖4是描繪根據本發明的一範例實施例的一機械式平坦化裝置之圖。
圖5是描繪根據本發明的一範例實施例的一真空平坦化裝置之圖。
圖6A-6E係描繪根據本發明的一範例實施例的用於脫黏具有大的背面凸塊的晶圓之範例步驟。
圖7是描繪根據本發明的一範例實施例的利用一圖案化的底膠填充層的晶粒接合之圖。
本發明的某些特點可見於一種用於一具有一晶粒至中介層(interposer)晶圓第一接合的半導體裝置封裝之方法及系統。本發明的範例特點可包括接合複數個包括電子裝置的半導體晶粒至一中介層晶圓，以及在該複數個半導體晶粒與該中介層晶圓之間施加一種底膠填充材料。一種模製材料可被施加以囊封該複數個半導體晶粒。該中介層晶圓可被薄化以露出直通矽晶穿孔(TSV)，並且金屬接點可被施加至該露出的TSV。該中介層晶圓可被單一化以產生複數個分別包括該複數個半導體晶粒中的一或多個以及一中介層晶粒的組件。該複數個組件中的一或多個可被接合到一或多個封裝基板。該複數個晶粒可被置放在該中介層晶圓上以供利用一黏著膜的接合。該中介層晶圓可利用下列的一或多個而被單一化：一雷射切割製程、反應性離子蝕刻、一鋸開技術、以及一電漿蝕刻製程。該底膠填充材料可利用一毛細管底膠填充製程來加以施加。該複數個半導體晶粒可以利用一質量回焊製程或是一熱壓縮製程而被接合至該中介層晶圓。該一或多個額外的晶粒可利用一質量回焊製程或是一熱壓縮製程而被接合至該複數個半導體晶粒。該模製材料可包括一種聚合物。該一或多個額外的晶粒可包括用於耦接至該複數個半導體晶粒的微凸塊。
圖1A是描繪根據本發明的一範例實施例的一種被配置有一晶粒到晶圓第一接合之積體電路封裝之概要圖。參照圖1A，其係展示有一種封裝100，其包括晶粒101、一封裝基板103、被動元件105、一中介層107、 焊料球111、一蓋子113、以及熱介面材料118。
該晶粒101可包括已經從一或多個半導體晶圓分開的積體電路晶粒。例如，該晶粒101可包括像是數位信號處理器(DSP)、網路處理器、電源管理單元、音訊處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器以及特殊應用積體電路之電路。此外，該晶粒101可包括微凸塊109，以用於提供在該晶粒101中的電路以及在該中介層107的表面上的接觸墊之間的電性接觸。
該中介層107可包括一例如是矽晶圓的半導體晶圓，其係具有提供從該中介層107的一表面至相對的表面之導電的路徑之直通矽晶穿孔(TSV)115。該中介層107亦可包括用於達成電性及機械的接觸至該封裝基板103之背面凸塊117。在另一範例情節中，該中介層107可包括玻璃或是一種有機積層材料，其任一種都可以能夠有例如是500x500mm的數量級之大的面板格式。
該封裝基板103可包括一用於該中介層107、晶粒101、被動元件105以及蓋子113之機械式的支承結構。該封裝基板103例如可包括在底表面上的焊料球111，以用於提供電性接觸至外部的裝置及電路。該封裝基板103亦可包括在一種非導電材料中之導電的線路，以用於經由墊來提供從該焊料球至該晶粒101的導電的路徑，該墊係被配置以接收該中介層107上的背面凸塊117。此外，該封裝基板103可包括用於接收該焊料球111的墊119。該墊119例如可包括一或多種凸塊下的金屬，以用於在該封裝基板103以及該焊料球111之間提供一適當的電性及機械的接觸。
例如，該被動元件105可包括像是電阻器、電容器及電感器 的電性元件，其可以提供功能給在該晶粒101中的元件及電路。該被動元件105可包括可能是難以整合在該晶粒101中的積體電路內之元件，例如是高值的電容器或電感器。在另一範例情節中，該被動元件105可包括一或多個晶體振盪器，以用於提供一或多個時脈信號至該晶粒101。
該蓋子113可提供氣密密封給在藉由該蓋子113以及該封裝基板103所界定的凹處內的元件。一熱介面可被產生，以用於經由該熱介面材料118將熱從該晶粒101傳出至該蓋子113，該熱介面材料118亦可作用為一黏著劑。
在一範例情節中，當該中介層仍然是一整個中介層晶粒的晶圓的部分時，該封裝100可藉由第一接合該晶粒101至該中介層107來加以製造，並且可利用一質量回焊或是熱壓縮製程來加以接合。該具有附接的晶粒101的中介層晶圓可加以處理以供進一步組裝。例如，該中介層晶圓可被薄化，並且該背面凸塊117可加以沉積。再者，在一模製製程被利用以囊封在該中介層晶圓中之個別的中介層晶粒上的晶粒101之前，一種毛細管底膠填充材料可被設置在該晶粒101以及該中介層之間。
一包括該晶粒101以及該中介層晶圓的組件可被單一化，並且該單一化的組件接著可利用質量回焊或是熱壓縮的任一種而被接合至該封裝基板103。該蓋子113可被置放在該接合的組件上，以提供氣密密封並且保護該電路不受外部環境的影響。最後，電性測試可以在該接合製程後來加以執行，以驗證是否達成適當的電連接並且沒有短路或開路存在。
圖1B是描繪根據本發明的一範例實施例的一種被配置有一晶粒至中介層晶圓第一接合以及堆疊的晶粒的積體電路封裝之概要圖。參 照圖1B，其係展示有一種封裝150，其包括該晶粒101、封裝基板103、被動元件105、中介層107、以及動態隨機存取記憶體(DRAM)121的一堆疊。例如，該晶粒101、封裝基板103、被動元件105以及中介層107可以是實質如同相關圖1A所述者，但是對於不同的晶粒101以及DRAM 121的堆疊係具有不同的電連接。
該DRAM 121可包括晶粒的一堆疊，以用於提供一高密度的記憶體給在該晶粒101中的電路或是在該封裝150外部的電路。該DRAM 121可以是前後地加以堆疊並且因此包括用於在該個別的晶粒之間提供電連接的TSV。
在一範例情節中，當該中介層107仍然處於晶圓形式時，亦即在單一化成為個別的中介層晶粒之前，該封裝150可藉由第一接合該晶粒101以及該DRAM 121至該中介層107來加以製造。該晶粒101以及該DRAM 121可利用質量回焊或是熱壓縮製程來加以接合。該中介層晶圓以及接合的晶粒在被接合至該封裝基板103之前可被單一化為個別有功能的晶粒/中介層晶粒之組件。再者，一毛細管底膠填充製程可以為了機械及絕緣之目的而接在該接合製程之後。電性測試可以在該接合製程後加以執行，以驗證是否達成適當的電連接並且沒有短路或開路存在。
圖1C-1E係描繪根據本發明的一範例實施例的用於利用一黏著膜來接合多個晶粒的範例步驟。參照圖1C，其係展示有複數個晶粒121以及一黏著層129。該複數個晶粒121的每一個都可包括金屬互連123，以用於後續的接合至其它晶粒。在另一範例情節中，該金屬互連123例如可包括微凸塊或是銅柱。
該黏著膜129例如可包括一黏著帶，該複數個晶粒121可被接合至該黏著帶，即如同在圖1C中所繪者。該黏著膜129可以是一種用於附接多個晶粒至在一晶圓內之其它晶粒的暫時性黏著劑。例如。該中介層127可包括一晶圓之個別的中介層晶粒(在此情形中，該中介層127係包括一“中介層晶圓”)。在一範例情節中，該複數個晶粒121可以暫時被置放在該黏著膜129上。儘管圖1C係描繪該複數個晶粒121為由三個晶粒所構成，但是更多或較少的晶粒(包含單一晶粒)也是可能的而且被思及。
如同由圖1D中的底膠填充材料125所描繪的，在利用該黏著膜129來接合該複數個晶粒121至該中介層127之前，一種選配的底膠填充材料125亦可被設置在該中介層晶圓127上。該底膠填充材料125例如可用於後續的熱壓縮接合製程，並且可容許有在一後續的熱壓縮接合製程期間透過一快速固化之瞬間的底膠填充。此可以改善接合良率，因為相較於用在該晶粒121的每一個之一個別的置放及底膠填充製程，單一底膠填充製程可被利用於該複數個晶粒121。該複數個晶粒121可以面朝上地加以置放，因而該金屬互連123可耦接至一接收的晶粒。
如同在圖1D及1E中所示，在該黏著膜129上的複數個晶粒121接著可被置放在該中介層127上，其中在該黏著膜129上的複數個晶粒121之最初的設置可以致能細微的控制該複數個晶粒121和該中介層127的間隔與對準。該中介層127可包括用於接收該金屬互連123的金屬墊131。一旦該複數個晶粒121被設置在該中介層127上，一熱壓縮接合製程可以為了在該金屬互連123以及金屬墊131之間適當的電性及機械的接合來加以執行。一旦接合後，該黏著膜129可被移除，此係產生在圖1E中所示的結構。
圖2A-2F係描繪在根據本發明的一範例實施例的一種晶粒至中介層晶圓第一接合結構中的範例步驟。參照圖2A，其係展示有一中介層晶圓201以及複數個晶粒203A-203C。該晶粒203A-203C可包括已經從一或多個半導體晶圓分開的積體電路晶粒。例如，該晶粒203A-203C可包括像是數位信號處理器(DSP)、網路處理器、電源管理單元、音訊處理器、RF電路、無線基頻系統單晶片(SoC)處理器、感測器、以及特殊應用積體電路之電路。此外，該晶粒203A-203C可包括微凸塊205，以用於在該晶粒203A-203C中的電路以及在該中介層晶圓201的表面上的前側墊209之間提供電性接觸。
該中介層晶圓201可包括複數個個別的中介層晶粒，該複數個中介層晶粒的每一個可耦接至一或多個例如是晶粒203A-203C的晶粒。該中介層晶圓201亦可包括用於提供電性接觸至該晶粒203A-203C的前側墊209。再者，該中介層晶圓201可包括直通矽晶穿孔(TSV)207，以用於在該中介層晶圓201已經被薄化後提供從該中介層的一表面至另一表面之導電的路徑。
該晶粒203A-203C可被置放在該中介層晶圓201上，並且例如利用一熱壓縮接合技術來加以接合。在另一範例情節中，一質量回焊製程可被利用來接合該晶粒203A-203C。一種非導電膏(NCP)亦可被利用以協助形成該接合。此外，一毛細管底膠填充接著可被施加，並且可填入在該晶粒203A-203C以及該中介層晶圓201之間的容積內。圖2B係描繪該晶粒203A-203C利用底膠填充材料210而被接合至該中介層晶圓201。
如同在圖2C中所繪，在該晶粒203A-203C之間的空間可被 填入以一種模製材料211。該模製材料211例如可包括一種聚合物材料，其可提供一非導電的結構支撐給被接合至該中介層晶圓201的晶粒，其係在後續的處理步驟中以及在被切割成為個別的封裝時保護該晶粒。在一範例情節中，該中介層晶圓201例如可利用一背面拋光或研磨而被薄化，以露出該TSV。
在另一範例情節中，該中介層晶圓201可被薄化至一其中該TSV仍然稍微被覆蓋的厚度，其接著可選擇性地在覆蓋該TSV的區域中被蝕刻。一保護層接著可沉積在其餘的矽之上，並且該露出的TSV的一拋光可加以執行以用於改善至該TSV的接觸。此外，為了與該背面凸塊213更佳的接觸，金屬墊可沉積在該拋光後的TSV上。
在該中介層晶圓201已經被薄化之後，如同在圖2D中所示，該背面凸塊213可加以沉積，以用於在該TSV以及接著接合的基板(例如是封裝基板)之間達成接觸。
該模製的組件接著可利用一例如是反應性離子蝕刻、電漿蝕刻(例如一感應耦合電漿)、雷射切割、或是機械鋸的切割技術而被單一化。在一範例情節中，該模製的組件可以部分地加以切割，並且利用機械式地將該晶粒拉開而分開。
如同在圖2E中所繪，包括該晶粒203A-203B及中介層晶粒201A之被單一化的模製的晶粒/中介層之組件接著可經由該背面凸塊213而被接合至該封裝基板215。該封裝基板215可包括接觸墊219，以用於和在該中介層晶粒201A上的背面凸塊213達成接觸並且用於焊料球227之後續的設置，即如同在圖2F中所示者。
此外，該蓋子221可被置放在該封裝組件上，其中係和一在該封裝基板215的表面處之黏著劑225做成氣密密封，該蓋子221亦可包括一種熱介面材料。於是，該蓋子221可以為了散熱之目的而接觸到該晶粒203A及203B的頂表面。該焊料球227例如可包括金屬球體，以用於和一印刷電路板達成電性及機械的接觸。
圖3是描繪在根據本發明的一範例實施例的一種晶粒至中介層晶圓第一接合製程中的範例步驟之概要圖。參照圖3，其係展示有一種晶粒至中介層晶圓製程，其係開始於一晶粒至中介層晶圓附接及底膠填充步驟301A。該一或多個晶粒例如可利用一熱壓縮接合技術而被接合。在下一個晶粒至中介層晶圓附接及底膠填充步驟301B中，額外的晶粒亦可被接合至該第一接合的晶粒，例如由圖1B中所示的DRAM堆疊121或是如同在圖1A中所示的中介層晶圓所描繪者。
一毛細管底膠填充製程可在該接合製程之後被利用，其可以提供在接點之間的一絕緣的阻障，並且可以填入在該晶粒以及該中介層晶圓之間的容積內。應注意到的是，該製程並不限於一熱壓縮技術。於是，例如一質量回焊製程亦可被利用。熱壓縮接合技術在40微米的間距或更小下可能是有利的，並且白凸塊，亦即高介電係數的介電層脫層可利用熱壓縮接合而被消除。此外，平坦度可以在熱壓縮接合下加以改善，此係產生較少的因為過大的間隙所造成之開路連接。
在背面加工步驟305中薄化該中介層基板以露出該TSV之前，一模製步驟303於是可先被利用以封裝該晶粒/中介層組件。此外，背面接點可被施加至在該中介層晶圓中之露出的TSV。
在單一化步驟307中，該模製的晶粒/中介層晶圓組件接著可被單一化為複數個在中介層晶粒上之模製的晶粒之組件。單一化例如可經由雷射切割、電漿蝕刻、反應性離子蝕刻、或是一鋸開技術來加以執行。
該單一化的組件接著可在步驟309中利用該沉積的背面接點而被附接至封裝基板。該晶粒/中介層/封裝基板的組件接著可受到一回焊步驟311，其中該中介層晶粒至封裝基板的接點可被回焊，此係產生適當的電氣及物理接觸。此接著可以是在該中介層晶粒以及該封裝基板之間的容積內之一毛細管底膠填充製程，此係在該接點之間提供一絕緣材料並且填充該空隙以拒斥污染。
最後，該接合的封裝可受到一最終的測試步驟315，以用於評估在該接合的晶粒中的電子電路的效能並且測試在該接合製程中所完成的電性接點。
圖4是描繪根據本發明的一範例實施例的一機械式平坦化裝置之圖。參照圖4，其係展示有一晶舟401、夾子403、複數個晶粒405、以及一中介層407。該晶舟401可包括一剛性支承結構，其中一晶粒/中介層組件可藉由該夾子403而被置放且保持在適當的地方。該晶舟401可以是能夠承受用於處理該晶粒/中介層組件的高溫，例如是超過200℃。
該複數個半導體晶粒405在被置放在該晶舟401中之前，例如可經由一熱壓縮接合技術而被接合至該中介層407。隨著該晶舟401、複數個半導體晶粒405、以及中介層407的溫度增高，在該夾子403於該組件的外部邊緣提供一向下的力之下，包括該複數個半導體晶粒405以及中介層407的一組件之曲率可能會變平。隨著該曲率接近零，在橫向的方向上 增大的長度可藉由滑動在該夾子403之下而被容納。此外，該晶舟401係結合該夾子403之向下的力來提供機械式的支撐，藉此平坦化該組件。
該晶舟401以及夾子403可以允許該部分組裝的封裝以正常的方式加熱，但是當該晶粒/中介層組件已經在增高的溫度下變成平坦時，該晶舟401以及夾子403係抵抗翹曲的正常發展，此係保持該部分組裝的封裝，在加熱期間使其變平並且接著隨著溫度上升而維持該矽中介層的該平坦度。
圖5是描繪根據本發明的一範例實施例的一真空平坦化裝置之圖。參照圖5，其係展示有一晶舟501、複數個晶粒505、一中介層507、真空密封環509、真空通道511、一閥513、以及一真空源515。
在一範例情節中，該晶舟501可包括一真空系統，以將包括該複數個半導體晶粒505以及中介層507之部分組裝的封裝變平。該真空機械式的系統係允許該部分組裝的封裝以正常的方式加熱，但是當該部分組裝的封裝已經變成平坦時，該真空機械式的系統係抵抗翹曲的正常發展，此係在加熱期間保持該部分組裝的封裝處於一變平的形態並且接著隨著溫度增高而維持該矽中介層507的該平坦度。
該真空可以在室溫或是稍微升高的溫度下，利用該真空源515經由該閥513以及真空通道511而被施加，並且可利用該高溫的密封環509來加以保持，因而該真空機械式的晶舟501可以行進通過一標準的回焊爐並且仍然維持充分的真空，以維持中介層矽的頂表面之平面性。
圖6A-6E係描繪根據本發明的一範例實施例的用於脫黏具有大的背面凸塊的晶圓之範例步驟。參照圖6A，其係展示有一載體晶圓 601、一具有背面凸塊605的晶圓603、以及一聚合物層607。
例如，該晶圓603可包括一電子裝置或有功能的晶圓或是一中介層晶圓，其可包括在脫黏製程中可能容易受損的大的背面凸塊605。於是，該聚合物層607可被施加以在脫黏製程期間保護該背面凸塊605。例如，該聚合物層607可包括一種抗蝕材料或是一黏著膜或帶，其可被施加在該晶圓603的背面凸塊605之上。
例如利用一真空技術之後續的夾頭附著至該載體晶圓601以及該聚合物層607的頂表面係被展示在圖6B中。該頂端夾頭609A可被移動在一橫向的方向上，同時該底部夾頭609B可被移動在相反的方向上，以分開該載體晶圓601與該晶圓603。該聚合物層607可以致能一適當的真空密封至該表面，其中當真空直接施加至該背面凸塊605時，其可能是一劣質的密封。
圖6C係展示在從該載體晶圓601脫黏後之產生的結構。當該載體晶圓601仍然附接至該頂端夾頭609A時，從該載體晶圓601剩下的任何黏著劑殘留物都可在一清洗製程中加以移除。
例如在圖6D中所示，在該背面凸塊605面朝上的情形下，該被清洗後的結構接著可被黏貼至一膜框架611。該聚合物層607接著可以用化學或是熱的方式來加以移除，而接著是一表面清洗，此係產生例如在圖6E中所示之接合的晶圓603。該膜框架611可以致能進一步處理以及便於該接合的晶圓603的傳輸。
圖7是描繪根據本發明的一範例實施例的利用一圖案化的底膠填充層的晶粒接合之圖。參照圖7，其係展示有一具有微凸塊703的頂 端晶粒701以及一包括接觸墊707及一底膠填充層709的底部晶粒705。
在一範例情節中，該微凸塊703例如可包括銅柱，並且可對應於在該底部半導體晶粒705中的接觸墊707。儘管該底部半導體晶粒705被展示為單一晶粒，但是在另一範例情節中，其可包括一整個晶圓的晶粒，其中相對於單一晶粒，複數個頂端晶粒701係被接合至一中介層晶圓705。該底膠填充層709可包括一種施加至該底部晶粒705的頂表面之聚合物，例如是頂端晶粒701之下一層級的晶粒將會被接合至該頂表面。該聚合物可包括一再保護或是預先施加的底膠填充，其將會流動且接合至兩個晶粒表面，此係除去對於後續的底膠填充製程之需求。
再者，該底膠填充層709可利用微影技術或是雷射剝蝕而被圖案化，以在該底部晶粒705中露出適當的接觸墊707，例如是藉由在該底膠填充層709中形成井。該露出的墊可被利用以將該頂端晶粒701對準到該底部晶粒705。該晶粒例如可利用一熱壓縮或是質量回焊技術而被接合。一助焊劑浸漬(flux dip)可被利用以助於焊料從一表面至另一表面的潤濕，並且該底膠填充可以“快速固化”並且密封至該頂端及底部晶粒表面兩者。再者，該底膠填充可以在該接合製程期間，在該微凸塊703以及接觸墊707之下到處流動。
在本發明的一實施例中，一種用於一具有一晶粒至中介層晶圓第一接合的半導體裝置封裝100、150之方法及系統係被揭示。就此點而言，本發明的特點可包括接合複數個包括電子裝置的半導體晶粒101、121、203A-203C、405、505、701至一中介層晶圓127、201以及在其中晶圓603包括一中介層晶圓的實例中的中介層晶圓603，以及施加一種底膠填充材料 210、217、709在該複數個半導體晶粒101、121、203A-203C、405、505、701以及該中介層晶圓之間。一種模製材料211、303可被施加以囊封該複數個半導體晶粒101、121、203A-203C、405、505、701。
該中介層晶圓127、201、以及在其中晶圓603包括一中介層晶圓的實例中的中介層晶圓603可被薄化以露出直通矽晶穿孔(TSV)，並且金屬接點213、707可被施加至該露出的TSV。該中介層晶圓127、201、以及在其中晶圓603包括一中介層晶圓的實例中的中介層晶圓603可被單一化以產生複數個組件100、150，該複數個組件100、150分別包括該複數個半導體晶粒101、121、203A-203C、405、505、701中的一或多個以及一中介層晶粒107、201A、407、507、705。該複數個組件中的一或多個可被接合到一或多個封裝基板103。該複數個晶粒101、121、203A-203C、405、505、701可被置放在該中介層晶圓127、201、以及在其中晶圓603包括一中介層晶圓的實例中的中介層晶圓603上，以供利用一黏著膜611的接合。
該中介層晶圓127、201、以及在其中晶圓603包括一中介層晶圓的實例中的中介層晶圓603可利用下列的一或多個而被單一化：一雷射切割製程、反應性離子蝕刻、一鋸開技術、以及一電漿蝕刻製程。該底膠填充材料210、217、709可利用一毛細管底膠填充製程來加以施加。該複數個半導體晶粒101、121、203A-203C、405、505、701可利用一質量回焊製程或是一熱壓縮製程而被接合至該中介層晶圓127、201、以及在其中晶圓603包括一中介層晶圓的實例中的中介層晶圓603。
該一或多個額外的晶粒101、121、203A-203C、405、505、701可利用一質量回焊製程或是一熱壓縮製程而被接合至該複數個半導體 晶粒101、121、203A-203C、405、505、701。該模製材料211、303可包括一種聚合物。該一或多個額外的晶粒101、121、203A-203C、405、505、701可包括用於耦接至該複數個半導體晶粒101、121、203A-203C、405、505的微凸塊。
儘管本發明已經參考某些實施例來加以敘述，但是將會被熟習此項技術者所理解的是可以完成各種的改變並且可以用等同物來加以取代，而不脫離本發明的範疇。此外，可以對於本發明的教示完成許多修改以適配一特定的情況或材料，而不脫離其範疇。因此，所欲的是本發明並不受限於該揭露的特定實施例，而是本發明將會包含所有落在所附的申請專利範圍的範疇內之實施例。
201‧‧‧中介層晶圓
203A-203C‧‧‧晶粒
205‧‧‧微凸塊
207‧‧‧直通矽晶穿孔(TSV)
209‧‧‧前側墊

Claims (20)

  1. 一種用於半導體封裝之方法，該方法係包括：接合包括電子裝置的複數個半導體晶粒至一中介層晶圓；在該複數個半導體晶粒以及該中介層晶圓之間施加一底膠填充材料；施加一模製材料以囊封該複數個半導體晶粒；薄化該中介層晶圓以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；單一化該中介層晶圓以產生分別包括該複數個半導體晶粒中的一或多個以及一中介層晶粒的複數個組件；以及接合該複數個組件中的一或多個至一或多個封裝基板。
  2. 根據申請專利範圍第1項之方法，其係包括設置該複數個晶粒在該中介層晶圓上，以供利用一黏著膜的接合。
  3. 根據申請專利範圍第1項之方法，其係包括利用下列的一或多個來單一化該中介層晶圓：一雷射切割製程、反應性離子蝕刻、一鋸開技術以及一電漿蝕刻製程。
  4. 根據申請專利範圍第1項之方法，其中該底膠填充材料利用一毛細管底膠填充製程而被施加。
  5. 根據申請專利範圍第1項之方法，其係包括利用一質量回焊製程來接合該複數個半導體晶粒至該中介層晶圓。
  6. 根據申請專利範圍第1項之方法，其係包括利用一熱壓縮製程來接合該複數個半導體晶粒至該中介層晶圓。
  7. 根據申請專利範圍第1項之方法，其係包括利用一質量回焊製程來接 合一或多個額外的晶粒至該複數個半導體晶粒。
  8. 根據申請專利範圍第1項之方法，其係包括利用一熱壓縮製程來接合該一或多個額外的晶粒至該複數個半導體晶粒。
  9. 根據申請專利範圍第1項之方法，其中該模製材料包括一聚合物。
  10. 根據申請專利範圍第1項之方法，其中該一或多個額外的晶粒包括用於耦接至該複數個半導體晶粒的微凸塊。
  11. 一種用於半導體封裝之方法，該方法係包括：在一晶粒至中介層晶圓第一接合製程中產生一半導體封裝，該製程包括：接合包括電子裝置的複數個半導體晶粒至一中介層晶圓的一正面側；在該複數個半導體晶粒以及該中介層晶圓之間施加一底膠填充材料；施加一模製材料以囊封該複數個半導體晶粒；薄化該中介層晶圓以露出直通矽晶穿孔(TSV)；施加金屬接點至露出的該TSV；單一化該中介層晶圓以產生分別包括該複數個半導體晶粒中的一或多個以及一中介層晶粒的複數個組件；以及接合該複數個組件中的一或多個至一或多個封裝基板。
  12. 根據申請專利範圍第11項之方法，其係包括設置該複數個晶粒在該中介層晶圓上，以供利用一黏著膜的接合。
  13. 根據申請專利範圍第11項之方法，其係包括利用下列的一或多個來 單一化該中介層晶圓：一雷射切割製程、反應性離子蝕刻、一鋸開技術以及一電漿蝕刻製程。
  14. 根據申請專利範圍第11項之方法，其中該底膠填充材料利用一毛細管底膠填充製程而被施加。
  15. 根據申請專利範圍第11項之方法，其係包括利用一質量回焊製程來接合該複數個半導體晶粒至該中介層晶圓。
  16. 根據申請專利範圍第11項之方法，其係包括利用一熱壓縮製程來接合該複數個半導體晶粒至該中介層晶圓。
  17. 根據申請專利範圍第11項之方法，其係包括利用一質量回焊製程來接合一或多個額外的晶粒至該複數個半導體晶粒。
  18. 根據申請專利範圍第11項之方法，其係包括利用一熱壓縮製程來接合該一或多個額外的晶粒至該複數個半導體晶粒。
  19. 根據申請專利範圍第18項之方法，其中該模製材料包括一種聚合物。
  20. 一種用於半導體封裝之方法，該方法係包括：在一晶粒至中介層晶圓第一接合的製程中產生一半導體封裝，該製程包括：接合包括電子裝置的複數個半導體晶粒至一中介層晶圓的一正面側；在該複數個半導體晶粒以及該中介層晶圓之間施加一底膠填充材料；施加一模製材料以囊封該複數個半導體晶粒；薄化該中介層晶圓以露出直通矽晶穿孔(TSV)； 施加金屬接點至露出的該TSV；利用一電漿蝕刻製程來單一化該中介層晶圓，以產生分別包括該複數個半導體晶粒中的一或多個以及一中介層晶粒的複數個組件；以及接合該複數個組件中的一或多個至一或多個封裝基板。
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