CN108400086B - 形成用于接合晶圆的集成电路结构的方法及所产生的结构 - Google Patents

形成用于接合晶圆的集成电路结构的方法及所产生的结构 Download PDF

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CN108400086B
CN108400086B CN201810083233.0A CN201810083233A CN108400086B CN 108400086 B CN108400086 B CN 108400086B CN 201810083233 A CN201810083233 A CN 201810083233A CN 108400086 B CN108400086 B CN 108400086B
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metal pillar
inhibitor layer
wetting inhibitor
layer
wetting
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CN108400086A (zh
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马克塔·G·法罗
坦雅·A·安塔哪莎瓦
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GlobalFoundries Inc
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GlobalFoundries Inc
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Abstract

本发明涉及形成用于接合晶圆的集成电路结构的方法及所产生的结构，其针对用于接合晶圆的集成电路结构及其形成方法。该IC结构可包括：位于衬底上方的金属柱，该金属柱包括上表面；位于该金属柱的该上表面的周缘周遭的湿化抑制剂层；以及位于该金属柱的该上表面上方的焊接材料，该焊接材料位于该湿化抑制剂层内并且受其限制。该金属柱的侧壁可无该焊接材料。该方法可包括：形成位于衬底上方的金属柱，该金属柱具有上表面；形成位于该金属柱的该上表面的周缘周遭的湿化抑制剂层；以及形成位于该湿化抑制剂层内并且受其限制的该金属柱的该上表面上方的焊接材料。

Description

形成用于接合晶圆的集成电路结构的方法及所产生的结构
技术领域
本发明涉及集成电路结构，并且更尤指形成用于接合诸晶圆的集成电路结构的方法，该等集成电路结构包括上方有焊接材料的金属柱，其中该金属柱的侧壁无该焊接材料，本发明还与所产生的结构有关。
背景技术
一种用于将个别芯片接合至封装衬底(substrate)的现有方法为可崩陷受控芯片连接(collapsible controlled chip connection；C4)，亦称为焊球(或焊块)封装。此互连封装将焊球用于在诸晶圆之间形成实体及电气两连接。另一现有方法包括位于一片晶圆上用以接合另一晶圆的柱体互连结构。由于电迁移效能增强，已发现柱体互连结构优于焊球封装。另外，相比于接合程序期间完全熔化的诸焊球之间的间距，柱体互连结构容许该等柱体互连结构之间的间距更紧密。在柱体互连技术中，柱体上方仍可使用少量焊料。然而，此技术的一项难处在于柱体互连结构的侧壁可能出现焊料湿化(solder wetting)。此侧壁湿化会造成相邻柱体互连结构之间出现焊料桥接或短路。再者，侧壁湿化可能在晶圆制作及使用寿命期间造成额外的损耗。
发明内容
本发明的第一态样针对用于接合诸晶圆的集成电路结构。该集成电路结构可包括：位于衬底上方的金属柱，该金属柱包括上表面；位于该金属柱的该上表面的周缘周遭的湿化抑制剂层；以及位于该金属柱的该上表面上方的焊接材料，该焊接材料位于该湿化抑制剂层内并且受其限制。
本发明的第二态样针对形成用于接合诸晶圆的集成电路结构的方法。该方法可包括：形成位于衬底上方的金属柱，该金属柱具有上表面；形成位于该金属柱的该上表面的周缘周遭的湿化抑制剂层；以及形成位于该湿化抑制剂层内并且受其限制的该金属柱的该上表面上方的焊接材料。
本发明的前述及其它特征将由以下本发明的具体实施例的更特定说明而显而易见。
附图说明
本发明的具体实施例将搭配下列图式详述，其中相似的名称表示相似的元件，并且其中：
图1至图5根据本发明的具体实施例，展示集成电路结构的截面图。
图6至图7根据本发明的具体实施例，展示集成电路结构的顶视图。
图8至图11根据本发明的具体实施例，展示集成电路结构的截面图。
图12至图15根据本发明的具体实施例，展示集成电路结构的截面图。
注意到的是，本发明的图式并未按照比例。该等图式用意仅在于绘示本发明的典型态样，因而不应该视为限制本发明的范畴。在图式中，相似的编号代表该等图式之间相似的元件。
符号说明：
100、190、200、290、300、390 集成电路(IC)结构
102 衬底
104、108 导电层
106 绝缘体层
110 绝缘体层或钝化层
112 凸块底下金属(UBM)层
114、130、202 光阻
116 开口
120 金属柱
124 上表面
128 湿化抑制剂层
132 周缘
136、138 中央部分
140 焊接材料
142 侧壁。
具体实施方式
本发明涉及集成电路结构，并且更尤指形成用于接合诸晶圆的集成电路结构的方法，该等集成电路结构包括上方有焊接材料的金属柱，其中该金属柱的侧壁无该焊接材料，本发明还与所产生的结构有关。具体而言，根据本发明的集成电路结构包括位于金属柱的上表面的周缘周遭的湿化抑制剂层，藉此定义位于金属柱上方的框体或环体，使得金属柱上方的焊接材料位于湿化抑制剂层内并且受其限制。结果是，沿着金属柱的侧壁没有焊料溢出。与现有集成电路结构相比之下，本发明通过修改金属柱的顶端表面来抑制焊料侧壁流失(runoff)，而不是通过建立疏水或非可湿化金属柱侧壁来抑制。
图1根据本发明的具体实施例，展示初步集成电路(IC)结构100的截面图。IC结构100可包括衬底102。衬底102可包括但不限于硅、锗、硅锗、碳化硅、以及主要由一或多种III-V族化合物半导体所组成者，该等化合物半导体具有由化学式AlX1GaX2InX3AsY1PY2NY3SbY4所定义的组成，其中X1、X2、X3、Y1、Y2、Y3及Y4代表相对比例，各大于或等于零，而且X1+X2+X3+Y1+Y2+Y3+Y4＝1(1为总相对莫耳量)。其它合适的衬底包括具有以下组成的II-VI族化合物半导体：ZnA1CdA2SeB1TeB2，其中A1、A2、B1及B2为各大于或等于零的相对比例，并且A1+A2+B1+B2＝1(1为总莫耳量)。再者，可使衬底102的一部分或整体有应变。尽管所示衬底102为包括单层半导体材料，所强调的是，本发明的教示一样适用于绝缘体上覆半导体(semiconductor-on-insulator；SOI)衬底。如所属技术领域已知，SOI衬底可包括位于另一半导体层(图未示)上的绝缘体层上的半导体层。SOI衬底的半导体层可包括本文中所述半导体衬底材料中任一者。SOI衬底的绝缘体层可包括任何目前已知或以后才开发的SOI衬底绝缘体，诸如但不局限于氧化硅。
上覆(overlying)衬底102可以是导电层104、绝缘体层106、另一导电层108、及另一绝缘体层110。更具体来说，导电层104可布置于衬底102上方。导电层104可包括任何目前已知或以后才发现的导电材料，例如：铜。绝缘体层106可布置于导电层104上方。绝缘体层106可包括任何目前已知或以后才开发的绝缘体层，例如：氧化物或氮化物。导电层108可布置于绝缘体层106上方。导电层108可包括例如铝或铜的导电接垫(图未示)。导电接垫可通过布置于绝缘体层106内的贯孔(图未示)来连接至导电层104。钝化(passivation)层110可布置于导电层108上方。钝化层110可包括数层(未个别图示)，举例如上覆于氮化物层的任选聚合物平坦化层，该氮化物层上覆于氧化物层。层104、106、108、110各可通过沉积来形成。
“沉积”于本文中使用时，可包括适用于待沉积材料的任何目前已知或以后才开发的技术，包括但不局限于例如：化学气相沉积(chemical vapor deposition；CVD)、低压CVD(LPCVD)、等离子增强型CVD(PECVD)、半大气压CVD(SACVD)与高密度等离子CVD(HDPCVD)、快速热CVD(RTCVD)、超高真空CVD(UHVCVD)、有限反应处理CVD(LRPCVD)、有机金属CVD(MOCVD)、溅镀沉积、离子束沉积、电子束沉积、雷射辅助沉积、热氧化作用、热氮化作用、旋涂方法、物理气相沉积(physical vapor deposition；PVD)、原子层沉积(atomic layerdeposition；ALD)、化学氧化作用、分子束磊晶(molecular beam epitaxy；MBE)、镀覆及/或蒸镀。
钝化层110的一部分可例如通过刻蚀来移除，以使其底下的导电层108的一部分曝露。“刻蚀”于本文中使用时，大体上指通过湿式或干式化学手段将材料从衬底、或该衬底上所形成的结构移除。在一些实例中，可希望将材料从衬底的某些区域选择性移除。在此一实例中，掩模可用于防止将材料从衬底的某些区域移除。刻蚀的类别大体上有两种：(i)湿刻蚀及(ii)干刻蚀。湿刻蚀可用以选择性溶解给定材料，并且留下另一材料相对原封不动。湿刻蚀典型为利用诸如酸的溶剂来进行。干刻蚀可使用可产生含能自由基的等离子、或中性带电物种来进行，其在晶圆的表面处起反应或撞击。中性粒子可从所有角度侵袭晶圆，此程序因此为等向性。离子碾压、或溅镀刻蚀从单一方向以稀有气体的含能离子轰击晶圆，因此，此程序属于高度各向异性。反应性离子刻蚀(reactive-ion etch；RIE)在介于溅镀刻蚀与等离子刻蚀中间的条件下运作，并且可用于产生深、窄特征，诸如沟槽。再者，可在钝化层110及受曝露的导电层108上方形成(例如保形沉积)凸块底下金属(under bumpmetallization；UBM)层112。所示UBM层112尽管为单一层，仍要理解的是，UBM层112可包括两层，包括例如钛或钛钨的阻障层及例如铜的晶种层。在一些具体实施例中，可在UBM层112上方形成另一导电层(图未示)，例如包括镍。如所属技术领域已知，UBM层112有助于电镀金属柱，如将于本文中所述者。
可在UBM层112上方例如通过沉积来形成光阻114。再者，光阻114可经受现有的微影及刻蚀程序以在光阻114内形成开口116，使UBM层112的受曝露部分曝露，如图1所示。可在开口116内形成金属柱120。金属柱120可包括例如铜、镍或其组合。“金属柱”于本文中使用时，可指称为包括单一金属、多种金属、或其合金的柱体。金属柱120可使用现有的沉积及/或电镀技术来形成，使得金属柱120在光阻114里的开口116内受到限制。尽管所示金属柱120为单一层，仍要理解的是，金属柱120可包含超过一层，例如一层铜，上覆于一层镍，上覆于另一层铜。金属柱120的形状可以是实质圆柱形，使得金属柱120的上表面为实质圆形或卵形(ovular)。在其它具体实施例中，金属柱120可具有多角形状的上表面。如图1所示，金属柱120可经由UBM层112电连接至导电层108。金属柱120可具有比光阻114的高度更小的高度。金属柱120可包括所具直径大约为25微米(μm)的微型柱体，然而，本文中所述的具体实施例并不受限于此，而且一样适用于所具直径比25μm更大或更小的金属柱120。在此一情况中，本文中所述的例如高度、宽度及厚度等尺寸可从而基于所用金属柱的大小来修改。“大约”于本文中使用时，意味着包括例如所述值10％内的值。
仍请参阅图1，金属柱120的上表面124上方可形成(例如沉积)湿化抑制剂层128。如图所示，亦可在光阻114的上表面(图1中未个别图示)上方形成湿化抑制剂层128。湿化抑制剂层128可包括任何目前已知或以后才开发的介电材料，举例如含有下列至少一者的材料：硅、氧、碳、氮、或氢、以及其组合。在一项实施例中，湿化抑制剂层128可包括例如氧化硅的氧化物、例如氮化硅的氮化物、或其组合。然而，要理解的是，可使用无下列至少一者的介电质：硅、氧、碳、氮或氢。在其它具体实施例中，湿化抑制剂层128可包括氟碳化合物。湿化抑制剂层128的命名原因在于，其沿着金属柱120的侧壁抑制焊接材料湿化，如将于本文中所述者。湿化抑制剂层128可包括大约0.1μm至大约6.0μm的厚度，即高度，或更具体而言，其为大约0.1μm至大约0.5μm。湿化抑制剂层128可包括大约2.0μm至大约6.0μm的宽度，即水平宽度。然而，湿化抑制剂层128并不受限于此一厚度，而且可客制化湿化抑制剂层128的厚度而不脱离本发明的态样。
请参阅图2，可在湿化抑制剂层128上方形成并且图案化另一光阻130，使得将金属柱120的上表面124的周缘132加衬(lining)的湿化抑制剂层128遭由光阻130包覆，并且使湿化抑制剂层128的中央部分136受曝露。如图3所示，湿化抑制剂层128的受曝露的中央部分136(图2)可例如通过刻蚀来移除，以使其底下的金属柱120的上表面124的中央部分138曝露。然而，将金属柱120的上表面124的周缘132加衬的湿化抑制剂层128保持不变。亦即，在刻蚀期间，加衬周缘132的湿化抑制剂层128因遭由光阻130包覆而保持不变，湿化抑制剂层128的中央部分136因未受光阻包覆而遭受移除。再者，可将光阻130移除以使将金属柱120的上表面124的周缘132加衬的湿化抑制剂层128曝露。
如图4所示，可在金属柱120的上表面124上方形成焊接材料140。更具体来说，可从金属柱120的上表面124的受曝露的中央部分138(图3)起电镀焊接材料140。如图所示，焊接材料受金属柱120的上表面124的周缘132周遭的湿化抑制剂层128所限制。焊接材料140可包括任何目前已知或以后才开发的焊接材料，举例如锡、铅、银、或其组合。请参阅图5，可将焊接材料140回焊，使得焊接材料140在金属柱120的上表面124上方的形状实质为球形(或半球形)，并且受周缘132周遭的湿化抑制剂层128所限制。按照这种方式，焊接材料140沿着金属柱120的侧壁142受抑制而免于湿化。亦即，侧壁142无焊接材料140。“实质”于本文中使用时，指对于大部分，大多完全地受指定或任何些微偏差，其提供本发明的相同技术效益。亦如图5所示，光阻114及光阻114上方的湿化抑制剂层128可例如通过刻蚀来移除，以使其底下的UBM层112有部分曝露。再者，UBM层112的受曝露部分可例如通过刻蚀来移除，以使其底下的钝化层110曝露。UBM层112的至少一部分可留在金属柱120下方。另外，IC结构100可经受一或多个表面清洁程序以清洁钝化层110的顶端表面。光阻114、UBM层112的移除程序可在焊料回焊之前或之后进行。
如图5所示焊料回焊之后所产生的IC结构190可包括位于衬底102上方的金属柱120。金属柱120可包括上表面124。湿化抑制剂层128可布置于金属柱120的上表面124的周缘132周遭。焊接材料140可布置于金属柱120的上表面124的中央部分138(图3)上方。焊接材料140可布置于周缘132周遭的湿化抑制剂层128内并且受其限制。图6至图7展示IC结构190的顶视图。如图6所示，湿化抑制剂层128可界定金属柱120上方的环形环(图5)。如图7所示，湿化抑制剂层可界定金属柱120上方的多角框体(图5)。湿化抑制剂层128可界定用于限制焊接材料140并使焊接材料140免于在金属柱120的侧壁142周遭湿化的任何形状。湿化抑制剂层128所界定的框体或环体的形状可通过现有的光微影技术来设计。
图8至图11展示本发明的另一具体实施例。从图8开始，展示初步IC结构200。IC结构200类似于IC结构100(图1)的处在于IC结构200包括衬底102、导电层104、108、绝缘体层106、钝化层110、UBM层112、光阻114及金属柱120。为求扼要，已省略这些结构及其形成过程的冗余阐释。IC结构200有别于IC结构100的处在于未如图1所示在金属柱120的上表面124及光阻114上方形成湿化抑制剂层128，而是在金属柱120及光阻114上方形成光阻202。可将光阻202图案化，使得金属柱120的上表面124的中央部分138遭由光阻202包覆，并且使金属柱120的上表面124的周缘132受曝露。
请参阅图9，可在光阻114、202及金属柱120的受曝露的周缘132上方形成(例如沉积)湿化抑制剂层128。湿化抑制剂层128可包括所述用于湿化抑制剂层128的任何材料。形成湿化抑制剂层128之后，可将光阻202从金属柱120的上表面124的中央部分138移除，以使金属柱120的上表面124的中央部分138曝露。再者，可从金属柱120的受曝露的中央部分138起电镀焊接材料140，使得焊接材料140受湿化抑制剂层128限制，如图10所示。请参阅图11，可将焊接材料140回焊，使得焊接材料140在金属柱120的上表面124上方的形状实质为球形(或半球形)，并且受周缘132周遭的湿化抑制剂层128所限制。按照这种方式，焊接材料140沿着金属柱120的侧壁142受抑制而免于湿化。亦即，侧壁142无焊接材料140。亦如图11所示，可移除光阻114及光阻114上方的湿化抑制剂层128，以使其底下的UBM层112有部分曝露。再者，UBM层112的受曝露部分可例如通过刻蚀来移除，以使其底下的钝化层110曝露。UBM层112的至少一部分可留在金属柱120下方。另外，IC结构200可经受一或多个表面清洁程序以清洁钝化层110的顶端表面。光阻114、UBM层112的移除程序可在焊料回焊之前或之后进行。
如图11所示焊料回焊之后所产生的IC结构290可包括位于衬底102上方的金属柱120。金属柱120可包括上表面124。湿化抑制剂层128可布置于金属柱120的上表面124的周缘132周遭。焊接材料140可布置于金属柱120的上表面124的中央部分138(图10)上方。焊接材料140可布置于周缘132周遭的湿化抑制剂层128内并且受其限制。如本文中所述，湿化抑制剂层128可界定金属柱120上方的环形环或多角框体，端视金属柱120的形状而定。湿化抑制剂层128可界定用于限制焊接材料140并使焊接材料140免于在金属柱120的侧壁142周遭湿化的任何形状。湿化抑制剂层128所界定的框体或环体的形状可通过现有的光微影技术来设计。
图12至图15展示本发明的另一具体实施例。本具体实施例与图1至图4的具体实施例差别在于并非形成光阻130(图2)以界定金属柱120的周缘周遭的湿化抑制剂层128，而是可使用各向异性刻蚀以界定金属柱120的周缘周遭的湿化抑制剂层128。从图12开始，展示初步IC结构300。IC结构300类似于IC结构100(图1)之处在于IC结构300包括衬底102、导电层104、108、绝缘体层106、110、光阻114、金属柱120及湿化抑制剂层128。为求扼要，已省略这些结构及其形成过程的冗余阐释。IC结构300与IC结构100可实质相同，或者，IC结构300与IC结构100的差异可在于可在金属柱120与光阻114的上表面124上方形成比图1的具体实施例所形成者更厚的湿化抑制剂层128。请参阅图13，可在湿化抑制剂层128上进行各向异性等离子刻蚀，使得金属柱120的上表面124的中央部分138受曝露，并且金属柱120的周缘132维持受湿化抑制剂层128包覆。
如图14所示，在各向异性等离子刻蚀之后，可自金属柱120的上表面124的受曝露的中央部分138起通过电镀焊接材料140来形成焊接材料140，使得焊接材料140受湿化抑制剂层128限制。再者，如图15所示，此程序可接续将焊接材料140回焊，使得焊接材料140在形状方面呈实质球形(或半球形)，并且受金属柱120的上表面124的周缘132周遭的湿化抑制剂层128所限制。按照这种方式，焊接材料140沿着金属柱120的侧壁142受抑制而免于湿化。亦即，侧壁142无焊接材料140。亦如图15所示，可移除光阻114及光阻114上方的湿化抑制剂层128，以使其底下的UBM层112有部分曝露。再者，UBM层112的受曝露部分可例如通过刻蚀来移除，以使其底下的钝化层110曝露。UBM层112的至少一部分可留在金属柱120下方。另外，IC结构300可经受一或多个表面清洁程序以清洁钝化层110的顶端表面。光阻114、UBM层112的移除程序可在焊料回焊之前或之后进行。
如图15所示焊料回焊的后所产生的IC结构390可包括位于衬底102上方的金属柱120。金属柱120可包括上表面124。湿化抑制剂层128可布置于金属柱120的上表面124的周缘132周遭。焊接材料140可布置于金属柱120的上表面124的中央部分138(图14)上方。焊接材料140可布置于金属柱120的上表面124的周缘132周遭的湿化抑制剂层128内并且受其限制。如本文中所述，湿化抑制剂层128可界定金属柱120上方的环形环或多角框体，端视金属柱120的形状而定。湿化抑制剂层128可界定用于限制焊接材料140并使焊接材料140免于在金属柱210的侧壁142周遭湿化的任何形状。湿化抑制剂层128所界定的框体或环体的形状可通过现有的光微影技术来设计。
本方法如以上所述，用于制造集成电路芯片。产生的集成电路芯片可由制造商以空白晶圆形式(也就是说，作为具有多个未封装芯片的单一晶圆)、当作裸晶粒、或以封装形式来配送。在已封装的例子中，芯片嵌装于单一芯片封装(诸如塑胶载体，具有粘贴至主机板或其它更高阶载体的引线)中，或多芯片封装(诸如具有表面互连或埋置型互连任一者或两者的陶瓷载体)中。在任一例子中，该芯片接着与其它芯片、离散电路元件、及/或其它信号处理装置整合成下列的部分或任一者：(a)诸如主机板的中间产品，或(b)最终产品。最终产品可以是包括集成电路芯片的任何产品，范围涵盖玩具及其它低阶应用至具有显示器、键盘或其它输入装置、及中央处理器的进阶电脑产品。
本文所用术语的目的仅在于说明特殊具体实施例并且意图不在于限制本发明。如本文中所用，单数形式“一”、“一种”、“一个”、以及“该”的用意在于同时包括复数形式，上下文另有所指除外。将进一步了解的是，“包含”及/或“包括”等词于本说明书中使用时，指明所述特征、整体、步骤、操作、元件及/或组件的存在，但并未排除一或多个其它特征、整体、步骤、操作、元件、组件及/或其群组的存在或新增。“任选”或“供选择地”意为后续所述事件或环境可或可不出现，并且该描述包括出现事件的实例及未出现事件的实例。
本说明书及权利要求书各处近似文句于本文中使用时，可套用来修饰任何定量表征，其许可改变此定量表征，但不会改变与其有关的基本功能。因此，一或多个诸如“约”、“大约”及“实质”的用语所修饰的值并不受限于指定的精确值。在至少一些实例中，该近似语言可对应于仪器测量该值时的精确度。本说明书及权利要求书这里及各处可组合及/或互换范围限制，此类范围乃经识别并且包括其中所含有的子范围，除非内容或文句另有所指。“大约”如应用到范围的特定值时，适用于两值，而且除非另外取决于测量该值的仪器的精确度，否则可表示所述值的+/-10％。“实质”是指对于大部分，大多完全地受指定或任何些微偏差，其提供本发明的相同技术效益。
随附的权利要求书中所有手段或步骤加上功能元件的对应结构、材料、动作及均等者用意在于包括结合如具体主张的其它主张专利权的元件进行任何结构、材料或动作。已为了描述及说明而呈现本发明的说明，但无意于具有彻底性或局限于所揭示形式的揭露。许多修改及变化对于所属领域技术人员将显而易知而不脱离本发明的范畴及精神。选择并说明具体实施例是为了更佳阐释本发明的原理及实际应用，并且如适用于经思考的特定用途，让所属领域技术人员能够理解本发明经各种修改的各项具体实施例。

Claims (15)

1.一种用于接合晶圆的集成电路结构，该集成电路结构包含：
位于衬底上方的金属柱，该金属柱包括上表面；
位于该金属柱的该上表面上方的湿化抑制剂层，其中，位于该湿化抑制剂层上方的光阻受图案化，使得位于该金属柱的该上表面的周缘周遭的该湿化抑制剂层的第一部分受包覆以及位于该金属柱的中央部分上方的该湿化抑制剂层的第二部分受曝露，该湿化抑制剂层的该第二部分受移除以使其底下的该金属柱的该中央部分曝露，且该光阻受移除以使位于该金属柱的该上表面的该周缘周遭的该湿化抑制剂层的该第一部分曝露；以及
位于该金属柱的该上表面上方的焊接材料，该焊接材料位于该金属柱的该上表面的该周缘周遭的该湿化抑制剂层的该第一部分内并且受其限制。
2.如权利要求1所述的集成电路结构，其特征在于，该湿化抑制剂层包括介电质或氟碳化合物。
3.如权利要求1所述的集成电路结构，其特征在于，该湿化抑制剂层定义位于该金属柱上方的环形环或多角框体。
4.如权利要求1所述的集成电路结构，其特征在于，该金属柱包括至少下列一者：铜、镍、或其组合。
5.如权利要求1所述的集成电路结构，其特征在于，该焊接材料包括至少下列一者：锡、银或铜。
6.如权利要求1所述的集成电路结构，其特征在于，该湿化抑制剂层包括2.0微米(μm)至6.0微米的宽度。
7.如权利要求1所述的集成电路结构，其特征在于，该金属柱的侧壁无该焊接材料。
8.一种形成用于将晶圆接合的集成电路结构的方法，该方法包含：
形成位于衬底上方的金属柱，该金属柱具有上表面；
形成位于该金属柱的该上表面上方的湿化抑制剂层；
将位于该湿化抑制剂层上方的光阻图案化，使得位于该金属柱的该上表面的周缘周遭的该湿化抑制剂层的第一部分受包覆以及位于该金属柱的中央部分上方的该湿化抑制剂层的第二部分受曝露；
将该湿化抑制剂层的该第二部分移除以使其底下的该金属柱的该中央部分曝露；
将该光阻移除以使位于该金属柱的该上表面的该周缘周遭的该湿化抑制剂层的该第一部分曝露；以及
形成位于该金属柱的该上表面的该周缘周遭的该湿化抑制剂层的该第一部分内并且受其限制的该金属柱的该上表面上方的焊接材料。
9.如权利要求8所述的方法，其特征在于，所述形成该焊接材料包括：
从该金属柱的该受曝露的中央部分起电镀该焊接材料，使得该焊接材料受该湿化抑制剂层限制；以及
回焊该焊接材料，使得该焊接材料的形状为实质球形。
10.如权利要求8所述的方法，其特征在于，该湿化抑制剂层包括介电质或氟碳化合物。
11.如权利要求8所述的方法，其特征在于，该湿化抑制剂层定义位于该金属柱上方的环形环或多角框体其中至少一者。
12.如权利要求8所述的方法，其特征在于，该金属柱包括至少下列一者：铜、镍、或其组合。
13.如权利要求8所述的方法，其特征在于，该焊接材料包括至少下列一者：锡、银、或铅。
14.如权利要求8所述的方法，其特征在于，该湿化抑制剂层包括2.0微米(μm)至6.0微米的宽度。
15.如权利要求8所述的方法，其特征在于，所述形成位于该金属柱的该上表面的该周缘周遭的该湿化抑制剂层包括：形成该湿化抑制剂层，使得该金属柱的侧壁无该焊接材料。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10490458B2 (en) 2017-09-29 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of cutting metal gates and structures formed thereof
US10943880B2 (en) * 2019-05-16 2021-03-09 Advanced Micro Devices, Inc. Semiconductor chip with reduced pitch conductive pillars
KR20210121336A (ko) 2020-03-26 2021-10-08 삼성전자주식회사 반도체 패키지

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102820290A (zh) * 2011-05-30 2012-12-12 台湾积体电路制造股份有限公司 封装集成电路的连接件设计
TW201430973A (zh) * 2012-11-15 2014-08-01 Amkor Technology Inc 用於具有晶粒對中介層晶圓第一接合的半導體裝置封裝的方法和系統

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0927516A (ja) * 1995-07-12 1997-01-28 Nippondenso Co Ltd 電子部品の接続構造
KR100336769B1 (ko) * 1999-11-04 2002-05-16 박종섭 웨이퍼 레벨의 칩 사이즈 패키지 및 그 제조방법
TW419712B (en) * 1999-11-22 2001-01-21 Ind Tech Res Inst Method of wafer level package and structure thereof
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6740577B2 (en) * 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
US7323406B2 (en) * 2005-01-27 2008-01-29 Chartered Semiconductor Manufacturing Ltd. Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures
JP5345814B2 (ja) * 2008-09-10 2013-11-20 富士通株式会社 実装回路基板及び半導体装置
TWI368979B (en) * 2008-09-16 2012-07-21 Advanced Semiconductor Eng Fabrication method of through-silicon vias
US8637392B2 (en) 2010-02-05 2014-01-28 International Business Machines Corporation Solder interconnect with non-wettable sidewall pillars and methods of manufacture
US8232193B2 (en) * 2010-07-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar capped by barrier layer
US9048135B2 (en) 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
US8941244B1 (en) * 2013-07-03 2015-01-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9190376B1 (en) 2014-05-15 2015-11-17 International Business Machines Corporation Organic coating to inhibit solder wetting on pillar sidewalls
US9324669B2 (en) * 2014-09-12 2016-04-26 International Business Machines Corporation Use of electrolytic plating to control solder wetting
JP2016213238A (ja) * 2015-04-30 2016-12-15 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
CN205200336U (zh) * 2015-12-14 2016-05-04 苏州源硕精密模具有限公司 一种倒装式落料冲孔复合模

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102820290A (zh) * 2011-05-30 2012-12-12 台湾积体电路制造股份有限公司 封装集成电路的连接件设计
TW201430973A (zh) * 2012-11-15 2014-08-01 Amkor Technology Inc 用於具有晶粒對中介層晶圓第一接合的半導體裝置封裝的方法和系統

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