TW201417223A - 半導體裝置之封裝方法、封裝裝置及其製造方法 - Google Patents

半導體裝置之封裝方法、封裝裝置及其製造方法 Download PDF

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Publication number
TW201417223A
TW201417223A TW102136460A TW102136460A TW201417223A TW 201417223 A TW201417223 A TW 201417223A TW 102136460 A TW102136460 A TW 102136460A TW 102136460 A TW102136460 A TW 102136460A TW 201417223 A TW201417223 A TW 201417223A
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Taiwan
Prior art keywords
substrate
integrated circuit
underfill material
mounting region
flow
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TW102136460A
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English (en)
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TWI512913B (zh
Inventor
Tsung-Fu Tsai
Yu-Chang Lin
Ying-Ching Shih
Wei-Min Wu
Yian-Liang Kuo
Chia-Wei Tu
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Taiwan Semiconductor Mfg
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Publication of TW201417223A publication Critical patent/TW201417223A/zh
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Abstract

本揭露係提供封裝裝置及其製造方法，及提供半導體裝置之封裝方法。在一實施例中，封裝裝置包含基材，此基材包含一積體電路安裝區及一預防底部填充材料流動之元件圍繞此積體電路安裝區設置。

Description

半導體裝置之封裝方法、封裝裝置及其製造方法
本揭露實施例係關於半導體裝置之封裝方法，且特別關於一種封裝裝置及其製造方法。
半導體裝置廣泛應用於各項電子產品中，例如個人電腦、手機、數位相機及其他電子設備。通常，可經由依續沉積絕緣層或介電層、導電層及半導體材料層於半導體基材上，並使用微影製程圖案化各材料層，以形成電路元件於半導體基材上，而形成半導體裝置。
半導體工業持續地透過微縮最小元件尺寸來增進各種電子元件(例如電晶體、二極體、電阻器、電容器等)之積體密度，其可使更多的電子元件整合至既定的區域內。在某些應用中，相較於傳統的封裝體，這些微縮的元件亦需尺寸更小的封裝體，降低所使用的面積。
本揭露實施例係提一種封裝裝置，包含：一基材，包含一積體電路晶片安裝區；以及一預防底部填充材料流動之元件，圍繞該積體電路晶片安裝區設置。
本揭露實施例亦提供一種封裝裝置之製造方法，該方法包含：提供一基材，該基材包含一積體電路晶片安裝區； 以及形成一預防底部填充材料流動之元件於基材上並圍繞該積體電路晶片安裝區，其中該防止一底部填充材料流動之元件係用以預防置於積體電路晶片下方之底部填充材料流過該預防底部填充材料流動之元件，其中該積體電路晶片置於該積體電路晶片安裝區上。
本揭露實施例更提供一種半導體裝置之封裝方法，包含：提供一封裝裝置，該封裝裝置包含一基材，該基材包含一積體電路晶片安裝區及一預防底部填充材料流動之元件圍繞該積體電路晶片安裝區；安裝一積體電路晶片至該基材之該積體電路晶片安裝區上；以及充填一底部填充材料至該積體電路晶片下方，其中預防底部填充材料流動之元件防止該底部填充材料流過該封裝基材上之該預防底部填充材料流動之元件。
102‧‧‧基材
104‧‧‧積體電路晶片安裝區
106‧‧‧預防底部填充材料流動之元件
108a‧‧‧積體電路晶片安裝區之第一側
108b‧‧‧積體電路晶片安裝區之第二側
108c‧‧‧積體電路晶片安裝區之第三側
108d‧‧‧積體電路晶片安裝區之第四側
110‧‧‧環
110a‧‧‧內環
110b‧‧‧外環
112‧‧‧圖案
114‧‧‧線路
116‧‧‧重分佈層
118‧‧‧導電區塊
120‧‧‧積體電路晶片
122‧‧‧導電凸塊
124‧‧‧底部填充材料
126‧‧‧針
128‧‧‧針之路徑
130‧‧‧液體底部填充材料之路徑
132‧‧‧絕緣層
134‧‧‧第一層
136‧‧‧第二層
138‧‧‧片材
140‧‧‧隆起區域
142‧‧‧底部填充材料之其他部分
144‧‧‧穿基材通孔
150‧‧‧半導體封裝裝置
152‧‧‧塑模材料
156‧‧‧焊球
158‧‧‧印刷電路板基材
180‧‧‧流程圖
182、184、186‧‧‧步驟
第1圖顯示依照本揭露某些實施例之封裝裝置之上視圖。
第2圖顯示依照其他實施例之封裝裝置之上視圖。
第3圖顯示依照其他實施例之封裝裝置之上視圖。
第4圖顯示依照其他實施例之封裝裝置之上視圖。
第5圖顯示依照某些實施例之封裝裝置之一部分的上視圖。
第6圖顯示依照其他實施例之封裝裝置之一部分的上視圖。
第7圖顯示依照更其他實施例之封裝裝置之一部分的上視 圖。
第8圖顯示第7圖所示之封裝裝置之剖面圖。
第9圖顯示依照某些實施例之充填至裝設於封裝裝置上之積體電路晶片底下之底部填充材料之透視圖。
第10圖顯示依照某些實施例之裝設於封裝裝置上之積體電路晶片之一部分的剖面圖。
第11圖顯示依照某些實施例之半導體封裝裝置之剖面圖。
第12圖顯示依照其他實施例之半導體封裝裝置之剖面圖。
第13圖顯示依照某些實施例之半導體裝置之封裝方法之流程圖。
以下將詳述本揭露實施例之製造及使用。然而，可知的是，這些實施例係提供本發明之概念實施於各種特定內容中。在此所述的這些實施例係僅用以舉例，但並非用以限定本揭露。在本揭露中，除示特別聲明，不同圖示中的對應的參考標號及符號通常係具有相同的對應部分。此外，這些元件比例可能不是以等比例繪示，以使圖示能清楚顯示本揭露實施例。
本揭露實施例係關於半導體裝置之封裝方法。在此，將詳述新穎的用於半導體裝置之封裝裝置，其中此半導體裝置包含預防底部填充材料流動之元件。在此，亦將一併詳述此半導體裝置之製造方法及將其封裝之方法。
首先參見第1圖，其顯示依照本揭露某些實施例之封裝裝置100之上視圖。封裝裝置100包含基材102。在某些實 施例中，基材102包含半導體晶圓，且此半導體晶圓可由絕緣層所覆蓋。基材102可包含或不包含主動元件或電路(未顯示)形成於其中。基材102可包含例如氧化矽覆於單晶矽上。基材102可包含其他導電層或其他半導體元件，例如電晶體、二極體等。或者，亦可以化合物半導體取代矽，化合物半導體可例如為GaAs、InP、Si/Ge或SiC。基材102可包含絕緣層上覆矽(SOI)或絕緣層上覆鍺(GOI)基材。在某些實施例中，基材102包含中介基材。或者，基材102可包含由其他材料或其他型態形成之基材。
需注意的是，本揭露圖示雖僅顯示單一基材102，然而，係有複數個基材102遍佈於晶圓或其他材料之表面，隨後再割成單片。
在某些實施例中，基材102包含晶圓級封裝基材。或者，亦可使用其他種類之基材102。
基材102包含一積體電路安裝區104。隨後，積體電路晶片120(未顯示於第1圖，請參見第5圖)將裝設至積體電路安裝區104中。在某些實施例中，積體電路安裝區104可設置於基材102之中央區域。或者，積體電路安裝區104可設置於基材102之角落或其他區域(未顯示)。
基材102包含一預防底部填充材料流動之元件106圍繞積體電路安裝區104設置。此新穎的預防底部填充材料流動之元件106包含至少一環，圍繞積體電路安裝區104設置。在第1圖中，預防底部填充材料流動之元件106包含一單環，圍繞積體電路安裝區104的周長設置。環110包含單個隆起元件，且 為一連續的環，圍繞積體電路安裝區104的周長設置。
此預防底部填充材料流動之元件106與積體電路安裝區104之第一側108a具有第一距離d1之間隔。此預防底部填充材料流動之元件106與積體電路安裝區104之第二側108b具有第二距離d2之間隔。在某些實施例中，第二距離d2小於第一距離d1。或者，第二距離d2可實質上等同於第一距離d1，或大於第一距離d1。在某些實施例中，預防底部填充材料流動之元件106亦與與積體電路安裝區104之第三側108c及第四側108d具有第二距離d2之間隔。
在某些實施例中，第一距離d1可為800 μm或小於800 μm，第二距離可為400 μm或小於400 μm。或者，第一距離d1及第二距離d2亦可包含其他數值。
隨後，在某些實施例中，底部填充材料(underfill material)124(參見第9圖)將會沿積體電路晶片安裝區104之第一側108a充填(dispense)。因此，第一距離d1係需大於第二距離d2，以適於底部填充材料124(參見第9圖)之充填針頭之直徑。在某些實施例中，底部填充材料124將沿兩側充填，且預防底部填充材料流動之元件106與第二側(例如第1圖之第四側108d)具有第二距離d1，以適於沿額外側108d充填底部填充材料124，如第1圖虛線所示。
第2至4圖顯示依照本揭露其他實施例之封裝裝置100之上視圖，其顯示預防底部填充材料流動之元件106的各種形狀。在第2圖中，預防底部填充材料流動之元件106包含兩同心環110a及110b，圍繞積體電路晶片安裝區106設置。或者， 預防底部填充材料流動之元件106亦可包含三個或更多個的同心環(未顯示)。預防底部填充材料流動之元件106較佳包含二或多個材料環110a及110b，因為當內環110a無法完全止住底部填充材料124的流動時，外環110b可止住這些溢流並防止底部填充材料124流出外環110b。在第2圖所示之實施例中，材料環110a及110b皆為連續的環。
或者，環110a及110b之一或多者可為不連續的環(例如環110a及/或110b為不連續的)。例如，第3圖顯示環110a及110b皆為不連續的環。在某些實施例中，材料環110a及110b中的中斷或不連續處係由環110a及110b相互錯開，以防止底部填充材料124流出外環110b。在其他實施例中，環110a可為不連續的，另一環110b為連續的。如第4圖所示，外環110b為連續的環。
在預防底部填充材料流動106包含二或多個環110、110a及110b的實施例中，或在環110a或110b為不連續的環的實施例中，預防底部填充材料流動之元件106包含由基材102形成之複數個隆起元件。
第5圖顯示依照本揭露某些實施例之封裝裝置100之一部分的上視圖。積體電路晶片120可例如裝設於基材102之積體電路晶片安裝區104。複數個圖案112形成於基材102之頂面。這些圖案112可包含導電材料，例如銅、鋁、其他材料、多層之前述材料或前述之合金，且在某些實施例中可包含導線或導電墊。在某些實施例中，圖案112可包含虛置圖案，其可基於各種理由包含於基材102之結構中。例如，改善基材之熱 性質、熱膨脹係數、化學機械研磨(CMP)平坦度或電鍍均勻性。較佳地，在某些實施例中，新穎的預防底部填充材料流動之元件106亦可與圖案112形成於相同的材料層中，以免去額外的材料層及微影製程。
第6圖顯示依照本揭露其他實施例之封裝裝置100之一部分的上視圖。環110a及110b皆為不連續的環，以適用於設置導電線路114於基材102上。例如，線路114可包含導線設於封裝裝置100之重分佈層116之頂層。在某些實施例中，由於預防底部填充材料流動之元件106之環110a及110b為導體，為了防止導電線路114短路，環110a及110b之接近線路114之的分為不連續的，且未與線路114連接。預防底部填充材料流動之元件106之環110a及110b及部分的重分佈層116之線路114可減少或防止底部填充材料124流出環110a及110b。
參見第7圖，其顯示依照本揭露其他實施例之封裝裝置100之一部分的上視圖。在其他實施例中，重分佈層116係經修飾，以使預防底部填充材料流動之元件106包含連續的環110a及110b。第8圖顯示如第7圖所示之封裝裝置100之一部分的剖面圖。如第8圖所示，線路114與導電區塊118在重分佈層116的下層相連接。線路114及導電區塊118係形成於重分佈層116之一或多層絕緣材料層中。某些線路114還包含凸塊下金屬(underball metallization，UBM)結構，其中導電凸塊122係會在隨後與其接合。
第9圖顯示為依照本揭露某些實施例之底部填充材料124充填於積體電路晶片120下的透視圖，其中積體電路晶 片120裝設於封裝裝置100上。積體電路晶片120透過複數個導電凸塊122接合至基材102上。導電凸塊122可以陣列形式、隨機圖案或其他圖案排列於積體電路晶片120之底面上。導電凸塊122可包含例如焊球、控制塌陷高度晶片連接(controlled collapse chip connection，C4)凸塊或其他型態之連接器。導電凸塊122可由使用例如回焊製程與基材102之積體電路晶片安裝區104上之接觸點(未顯示)或凸塊下金屬(UBM)結構接合底部填充材料124之充填可在接合積體電路晶片120至基材102之後進行。
充填針126係用以沿積體電路晶片120之一或多側充填底部填充材料124。充填針126之充填路徑係以箭頭128顯示。底部填充材料124於充填時係為液體，其係流入導電凸塊122之間，並可由針126沿積體電路晶片120之一寬度流至積體電路晶片120之對側。液體底部填充材料124之流動路徑係以標號130顯示。由於例如毛細作用，液體底部填充材料124會在積體電路晶片120下方流動。底部填充材料124可包含環氧樹脂或聚合物，或其他合適材料。在固化之後，底部填充材料124包硬化的固體。如第6圖所示，預防底部填充材料流動之元件106包含單個環110。預防底部填充材料流動之元件106可防止底部填充材料124流至環110外。
第10圖係顯示裝設於封裝裝置1000上之積體電路晶片120之一部分的剖面圖，並顯示依照本揭露某些實施例之半導體封裝裝置150。在此，亦顯示固化後之底部填充材料124之更詳細的圖式。當施予底部填充材料124時，由於底部填充 材料124的之充填及固化過程中之彎液面效應(meniscus effect)，其係會沿積體電路晶片120之邊緣形成片材(fillets)138。在固化後，這些片材138之頂面可具有凹陷形狀(未顯示)。預防底部填充材料流動之元件106可作為圍壩阻擋或減少底部填充材料124沿四周向外流動。底部填充材料124之隆起區域140可形成於接近預防底部填充材料流動之元件106之處。底部填充材料124之其他部分之厚度相較於隆起部分140相對較薄。在某些實施例中，未形成隆起區域140(未顯示)。在其他實施例中，底部填充材料124之部分142未完全延伸至內環110a，且基材102之接近內環110a的部分係為暴露的(未顯示)。
第10圖亦顯示預防底部填充材料流動之元件106之環110a及110b之形狀及尺寸之剖面圖。環110a及110b之剖面形狀可為梯形，其接近基材102的部分之寬度係大於頂部。或者，環110a及110b可為方形、矩形或其他形狀。預防底部填充材料流動之元件106之環110a及110b之一側的剖面寬度d3皆為約5 μm或小於5 μm。預防底部填充材料流動之元件106之環110a及110b皆可具有超出基材102表面之高度d4，高度d4為約5 μm或小於5 μm。或者，寬度d3及高度d4可包含其他數值。
在某些實施例中，預防底部填充材料流動之元件106包含金屬。例如，預防底部填充材料流動之元件106可包含金屬、絕緣體、環氧樹脂、聚合物、前述之多層結構或前述之組合。環110a及110b可包含一第一層134及一第二層136置於第一層134上。例如，第一層134可包含金屬或其他導電材料，第二層136可包含絕緣體，例如二氧化矽、氮化矽、其他絕緣體 或前述之多層、或前述之組合。或者，第一層134及第二層136可包含其他材料，且環110a及110b可包含單一材料層或三或更多層的材料層。
預防底部填充材料流動之元件106可由圖案化基材102之材料層或添加材料至基材102形成。例如，預防底部填充材料流動之元件106之環110a及110b可由添加材料層至基材102之頂面，並以微影技術圖案化此材料層，以形成環110a及110b。或者，可由電鍍形成環110a及110b。在某些實施例中，環110a及110b係形成於基材102之既有材料層中，因而不需要額外的材料層，如第5圖所示。環110a及110b可形成於相同的材層中，且元件112及/或線路114形成於此相同的材料層中。
再次參見第10圖，絕緣層132可形成於基材102之頂面上。或者，亦可形成其他材料層於接近基材102之頂面處。例如，可形成重分佈層116(未顯示於第10圖中，請參見第8圖)於基材102之頂面，其可包含扇出(fan-out)的導線，以連接積體電路晶片120及重分佈層116之接觸墊。或者，亦可形成重分佈層116於基材102之底面(未顯示)。在某些實施例中，基材102未包含重分佈層116或絕緣層132。
第11圖顯示依照本揭露某些實施例之半導體封裝裝置150之剖面圖。在某些實施例中，基材102包含複數個穿基材通孔(through-substrate vias，TSVs)144。在某些實施例中，不包含這些穿基材通孔144。在某些實施例中，基材102包含部分的晶圓，並包含以晶片堆疊晶圓(chip-on wafer，COW)製程裝設積體電路晶片120於基材102上。或者，亦可使其他製程裝 設積體電路晶片120。
在某些實施例中，在經過如第11圖所示之半導體封裝裝置150之製程後，可形成塑模化合物152於積體電路晶片120、預防底部填充材料流動之元件106、底部填充材料124及基材之暴露部分上，形成如第12圖所示之結構，其係顯示依照本揭露某些實施例之包含封裝基材102之半導體封裝裝置150。在某些實施例中，半導體封裝裝置150可與印刷電路板(PCB)基材158一併封裝。此印刷電路板(PCB)基材158在本揭露之某些申請專利範圍中，亦可稱為第二基材。例如，焊球156可藉由晶片堆疊晶圓堆疊基材(chip-on wafer on-substrate，COWOS)製程接合至基材102之穿基材通孔144上。此包含基材150及預防底部填充材料流動之元件106的新穎的半導體封裝裝置150，亦可使用於其他應用或其他封裝組態中。
第13圖顯示依照本揭露某些實施例之半導體封裝裝置之製造方法之流程圖180。在步驟182中，提供一包含基材102之封裝裝置100，此基材102包含一積體電路晶片安裝區104及一預防底部填充材料流動之元件106圍繞該積體電路晶片安裝區104設置。在步驟184中，裝設積體電路晶片120至基材102之積體電路晶片安裝區104上。在步驟186中，充填底部填充材料124至積體電路晶片120底下。預防底部填充材料流動之元件106係會防止底部填充材料124流過封裝裝置100上之預防底部填充材料流動之元件106。
本揭露某些實施例係包含在此所述的封裝裝置100之製造方法，且亦包含含新穎的預防底部填充材料流動之 元件106之封裝裝置100。本揭露某些實施例亦包含半導體封裝裝置150，其可使用在此所述之新穎的封裝裝置100作封裝。
依照本揭露某些實施例所提供之新穎的封裝裝置100，其包含在此所述的預防底部填充材料流動之元件106。預防底部填充材料流動之元件106之環110、110a及110b減少或防止底部填充材料124沿四周向外流動，因而形成改良的封裝裝置150。減少或防止底部填充材料124向外流動可具有如下之好處：防止或減少底部填起材料124之脫層，並因此在某些應用中亦可減少或防止隨後沉積之塑模化合物之脫層。因此，可使底部填充材料120及後沉積的塑模化合物與基材之黏著性增加，且因較強的黏著性，可減少半導體封裝裝置150之膨脹的風險。此預防底部填充材料流動之元件106包含虛置圖案設計，其可減少底部填充材料124流至積體電路晶片120外之區域，且在製程中無需添加任何額外的花費。此新穎的預防底部填充材料流動之元件106的結構及設計可輕易地整合於封裝裝置之製程中。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲 得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍應以較寬廣的範圍或意義來解讀。
102‧‧‧基材
106‧‧‧預防底部填充材料流動之元件
120‧‧‧積體電路晶片
122‧‧‧導電凸塊
124‧‧‧底部填充材料
144‧‧‧穿基材通孔
150‧‧‧半導體封裝裝置
152‧‧‧塑模材料
156‧‧‧焊球
158‧‧‧印刷電路板基材

Claims (10)

  1. 一種封裝裝置，包含：一基材，包含一積體電路晶片安裝區；以及一預防底部填充材料流動之元件，圍繞該積體電路晶片安裝區設置。
  2. 如申請專利範圍第1項所述之封裝裝置，其中該預防底部填充材料流動之元件包含單個或複數個該基材之隆起元件。
  3. 如申請專利範圍第1項所述之封裝裝置，其中該積體電路晶片安裝區具有一剖面寬度約5 μm或小於約5 μm，及/或具有一高度高於該基材之頂面約5 μm或小於約5 μm。
  4. 如申請專利範圍第1項所述之封裝裝置，其中該預防底部填充材料流動之元件設置為與該積體電路晶片安裝區之一第一側具有一第一距離，且其中該預防底部填充材料流動之元件設置為與該積體電路晶片安裝區之一第二側具有一第二距離，其中該第二距離小於該第一距離。
  5. 一種封裝裝置之製造方法，該方法包含：提供一基材，該基材包含一積體電路晶片安裝區；以及形成一預防底部填充材料流動之元件於基材上並圍繞該積體電路晶片安裝區，其中該防止一底部填充材料流動之元件係用以預防置於積體電路晶片下方之底部填充材料流過該預防底部填充材料流動之元件，其中該積體電路晶片置於該積體電路晶片安裝區上。
  6. 如申請專利範圍第5項所述之封裝裝置之製造方法，其中該形成該底部填充材料之步驟包含圖案化該基材之一材料 層或添加一材料至該基材。
  7. 如申請專利範圍第5項所述之封裝裝置之製造方法，其中該形成該底部填充材料之步驟包含形成一環，其圍繞該積體電路晶片安裝區，其中該環為連續的環或一不連續的環。
  8. 如申請專利範圍第5項所述之封裝裝置之製造方法，其中該形成該底部填充材料之步驟包含形成複數個同心環，圍繞該積體電路晶片安裝區。
  9. 一種半導體裝置之封裝方法，包含：提供一封裝裝置，該封裝裝置包含一基材，該基材包含一積體電路晶片安裝區及一預防底部填充材料流動之元件圍繞該積體電路晶片安裝區；安裝一積體電路晶片至該基材之該積體電路晶片安裝區上；以及充填一底部填充材料至該積體電路晶片下方，其中預防底部填充材料流動之元件防止該底部填充材料流過該封裝基材上之該預防底部填充材料流動之元件。
  10. 如申請專利範圍第9項所述之半導體裝置之封裝方法，其中該基材包含一第一基材，且該半導體裝置之封裝方法更包含提供一第二基材，且更包含使用一晶圓堆疊晶片堆疊基材製程接合該封裝裝置及該第二基材。
TW102136460A 2012-10-19 2013-10-09 半導體裝置之封裝方法、封裝裝置及其製造方法 TWI512913B (zh)

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