CN107027239A - 柔性印制电路板及应用其的智能卡模块和智能卡 - Google Patents
柔性印制电路板及应用其的智能卡模块和智能卡 Download PDFInfo
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Abstract
本发明关于一种柔性印制电路板及应用其的智能卡模块和智能卡,包括至少一层基板,所述基板至少一侧上设置用于安装芯片组件的焊盘区,所述焊盘区上设有若干间隔排布的焊盘和连接于对应焊盘的迹线,其中至少有一焊盘为圆形焊盘。本发明还提供一种应用所述柔性印制电路板的SIM卡。所述柔性印制电路板的结构稳定性高。本发明采用圆形的焊盘,使得所述焊盘区中铜箔占用面积更小,留有更多的空间贴合PET膜,因此在将芯片安装于焊盘区的过程中,较大面积的PET膜可以涂抹更多的粘胶,提高芯片与焊盘区的结构稳定性。
Description
技术领域
本发明涉及电路板封装领域,尤其涉及一种柔性印制电路板及应用其的智能卡模块和智能卡。
背景技术
随着人类社会的发展,通讯设备和身份识别设备得到了越来越广泛的应用。其中,智能卡及相应识别设备的使用使得人类出行的安全性和便捷性大大提高。
智能卡(Smart card或IC Card),又称智慧卡、集成电路卡及IC卡,是指粘贴或嵌有集成电路芯片的一种便携式卡片塑料。卡片包含了微处理器、I/O界面及存储器,提供了数据的运算、访问控制及存储功能,卡片的尺寸和连接点定义目前由ISO规范统一规定,主要规范在ISO7810中。常见智能卡有电话IC卡、身份IC卡,以及一些交通票证和存储卡。
智能卡包括卡体和安装在卡体上的智能卡模块。智能卡模块包括柔性印制电路板(Flexible Printed Ciruit,FPC)和安装在电路板上的电子元件(如芯片)。柔性印制电路板是一种特殊的印制电路板。它具有重量轻、厚度薄、柔软、可弯曲等特点而广泛应用于各类电子装置中,如手机、笔记本电脑、平板电脑、液晶显示装置(LCD)等等。
目前市面上的柔性印制电路板产品中,用于焊接芯片的焊盘(连接盘)为方形,而焊接芯片的金球呈圆球形,因此正方形的焊盘造成了焊盘材料的浪费。同时,方形焊盘导致芯片覆盖区域的焊盘和迹线之间的距离在很小时容易发生意外短路,这使得焊盘之间的距离设计无法减小。并且,方形的焊盘占用了FPC上的聚酯类薄片(Polyethylene Terephthalate,PET)的较大面积,使得所述芯片与所述FPC之间的粘合不牢固,模块的可靠性降低。
发明内容
有鉴于此,本发明旨在提供一种新型的可靠性高的柔性印刷电路板及其智能卡模块和智能卡,以解决现有技术中焊盘材料浪费,设计难度大和粘合效果不理想的问题。本发明是通过下述技术方案来解决上述技术问题的:一种柔性印制电路板,包括至少一层基板,所述基板至少一侧上设置用于安装芯片组件的焊盘区,所述焊盘区上设有若干间隔排布的焊盘和连接于对应焊盘的迹线,其中至少有一焊盘为圆形焊盘。
作为一种优选方案,所述焊盘区上的焊盘均为圆形焊盘。
作为一种优选方案,相邻两个焊盘圆心之间的最小间距小于等于177um。
作为一种优选方案,相邻两个焊盘圆心之间的最小间距等于142um。
作为一种优选方案,相邻两个焊盘之间的最小间距小于等于75um。
作为一种优选方案相邻两个焊盘之间的最小间距等于40um。
作为一种优选方案,所述若干迹线中至少一条迹线包括延伸部,所述延伸部沿所述焊盘区的边界延伸。
作为一种优选方案,所述延伸部背离对应的迹线的一端向邻近的另一迹线的方向延伸。
作为一种优选方案,所述若干延伸部沿所述焊盘区的边界围成一预设形状。
作为一种优选方案,所述延伸部的厚度为10um-15um。
作为一种优选方案,所述延伸部的厚度为10um。
作为一种优选方案,所述延伸部背离对应的迹线的一端与邻近的另一迹线之间绝缘。
作为一种优选方案,所述每一迹线位于所述焊盘区中的部分宽度均相等。
作为一种优选方案,所述柔性印制电路板还包括至少一组定位标记,每一定位标记设置于所述迹线远离所述焊盘区的位置。
作为一种优选方案,至少一根迹线上设置贯通所述基板的过孔,所述过孔中填充导电介质。
作为一种优选方案,所述基板的数量至少为两层,所述基板叠放设置,所述迹线上设置通孔,所述通孔中填充导电介质。
本发明还涉及一种智能卡模块,所述智能卡模块包括如前述的柔性印制电路板和一个芯片,所述芯片设置于所述柔性印制电路板安装芯片组件的焊盘区位置。
本发明还涉及一种智能卡,包括卡体,所述板体设置一凹槽,所述智能卡还包括前述的智能卡模块,所述智能卡模块设置于所述板体的凹槽位置。
本发明的柔性印制电路板采用圆形的焊盘,使得所述焊盘区中铜箔占用面积更小,留有更多的空间贴合PET膜,因此在将芯片安装于焊盘区的过程中,较大面积的PET膜可以涂抹更多的粘胶,提高芯片与焊盘区的结构稳定性。
附图说明
图1是本发明第一实施例的柔性印制电路板的俯视示意图。
图2是现有柔性印制电路板的俯视示意图。
图3是本发明第二实施例的柔性印制电路板的俯视示意图。
图4是本发明第三实施例的柔性印制电路板的俯视示意图。
图5是本发明第四实施例的柔性印制电路板的俯视示意图。
图6是本发明第一实施例的柔性印制电路板的另一俯视示意图。
图7是本发明一个实施例下智能卡产品的应用示意图。
主要元件符号说明
柔性印制电路板 | 1 |
基板 | 12 |
焊盘区 | 2 |
焊盘 | 3 |
第一焊盘 | 31 |
第二焊盘 | 32 |
第三焊盘 | 33 |
第四焊盘 | 34 |
第五焊盘 | 35 |
过孔 | 4 |
通孔 | 41 |
迹线 | 5 |
第一迹线 | 51 |
第二迹线 | 52 |
第三迹线 | 53 |
第四迹线 | 54 |
第五迹线 | 55 |
延伸部 | 56 |
定位标记 | 57 |
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
本发明的各种实施例将参照附图进行说明。在说明书及附图中,具有类似结构或功能的元件将用相同的元件符号表示。可以理解,附图仅为提供参考与说明使用,并非用来对本发明加以限制。附图中显示的尺寸仅仅是为便于清晰描述,而并不限定比例关系或对本发明进行穷尽性的说明,也不是对本发明的范围进行限制。除非另有定义,本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。
需要说明的是,当组件被称为“固定于”另一个组件,它可以直接在另一个组件上或者也可以存在居中的组件。当一个组件被认为是“连接”另一个组件,它可以是直接连接到另一个组件或者可能同时存在居中组件。当一个组件被认为是“设置于”另一个组件,它可以是直接设置在另一个组件上或者可能同时存在居中组件。
图1根据本发明第一实施方式示出了柔性印制电路板1的平面示意性结构。该柔性印制电路板1可以应用于智能卡,也可以应用于其它电子装置,如手机、笔记本电脑、平板电脑、液晶显示装置(LCD)、电机,以及其它电子装置内的电子元器件。本实施方式中,所述柔性印制电路板1优选地适用于一智能卡模块。一个芯片(图未示)以倒装芯片(flip chip)的方式安装于电路板上,同时该柔性印制电路板1上设置其它必要的电子元件,形成智能卡模块。之后,将智能卡模块设置在一个卡体10(见图7)上,就形成了完整的智能卡产品。
所述智能卡包括至少一塑料板体(卡体10)、安装于所述板体上的智能卡模块,即柔性印制电路板1和电路板上的电子元件。可以理解,为减小所述智能卡的厚度,所述卡体上可以开设于所述印刷电路板1及芯片厚度及形状相匹配的安装槽。在一些实施例中,板体可以设置一些天线与智能卡连接,从而达到智能卡的无线通讯功能。在另一些实施例中,天线可以设置在智能卡模块中相对芯片安装面的另一面,以此改善加工工序。
所述柔性印制电路板1包括至少一个焊盘区2(图中圆形虚线区域),所述焊盘区2上设置若干个焊盘3(连接盘)和若干条迹线5。每一焊盘3上连接有一条迹线5,所述迹线5用于将焊盘区上安装的电子元器件(如芯片组件)连接至另一电子元器件或反面接触盘。此处焊盘可以以倒装芯片的工艺与芯片组件连接,也可以以引线键合的方式连接芯片组件。
可以理解,所述焊盘2和迹线5的数量根据所述焊盘区2上需焊接的芯片(图未示)的引脚数量决定。智能卡的芯片引脚根据ISO相关规范已经得到一些限定,本实施方式中,所述焊盘3和迹线5的数量均为五个,其中三个焊盘3均匀间隔排成一排,另外两个焊盘3排成平行相对的另外一排。
所述柔性印制电路板1包括至少一层基板12,本实施方式中,所述基板12为PET材料制成。所述焊盘3设置于所述柔性印制电路板1的基板12上的焊盘区2中。本实施方式中,所述焊盘3和迹线5的材料为铜箔加镍层覆盖其上形成,所述柔性印制电路板1为双层板(双面板),所述柔性印制电路板1的基板12至少一侧安装有焊盘3和迹线5,另一面可以同样设置迹线和焊盘。本实施方式中,为节约篇幅,以安装于所述基板12同一侧的焊盘3和迹线5为例进行描述。
可以理解,所述焊盘3和迹线5设置于所述焊盘区2的方式可以为通过在所述焊盘区2中印刷导电材料的方式,还可以为电镀刻蚀的方式在所述焊盘区2中预设的位置电镀出焊盘3和迹线5。
本实施方式中,所述若干焊盘3中至少一个焊盘3为圆形,在保证芯片组装公差在±25um之内的前提下,相邻两个焊盘3之间的最小间距a小于等于75um,较佳的,所述最小间距a为40um。相邻两个焊盘3圆心之间的最小间距b小于等于177um,较佳地,所述最小间距b为142um。相比于普通矩形的焊盘结构,本实施方式中的焊盘3与普通焊盘的矩形的内切圆尺寸相同,使得所述焊盘3的耗材少。同时,生产过程中只需控制好圆形焊盘之间的距离,即可保证电路之间不会发生短路(short)的意外情况。在保证制造公差相同的条件下,邻近的焊盘3之间的距离减小有利于所述柔性印制电路板1更好的进行布线,同时芯片的铝盘间距也可缩小,从而提供缩小芯片尺寸的空间,占用电子装置的空间更小。
并且,参阅图2,现有普通矩形焊盘的柔性印制电路板的圆形焊盘区中,铜箔占据的面积占整个焊盘区的24.4%。参阅图1,而采用本发明实施方式的圆形焊盘3的柔性印制电路板1中,焊盘3采用同样的布局,并且焊盘区2面积相同的情况下,铜箔的面积占整个焊盘区2的13%。很明显,本发明实施方式的柔性印制电路板1的焊盘区2中铜箔占用面积更小。而较大面积的基板12(PET膜)可以涂抹更多的粘胶,提高芯片与焊盘区2的结构稳定性。
图3至图5根据本发明另一个构思示出了另一些技术方案。其中,所述若干迹线5中至少其中一条迹线5上延伸出至少一延伸部56。所述延伸部56由所在的迹线5靠近焊盘3的部位沿所述焊盘区2的边界向邻近的迹线5延伸,直至延伸至与邻近的迹线5一侧接近的位置。可以理解,每一迹线5的延伸部56均与其它任意一个迹线之间绝缘。
所述延伸部56沿所述焊盘区2的边界延伸后,共同围成所述焊盘区2的边界,使得在所焊盘区2中涂抹用于粘接芯片(图未示)的粘胶层时,在所述若干延伸部56的引导和阻挡下,所述粘胶能够沿焊盘区2流动,并均匀涂抹在整个焊盘区2中。所述延伸部56能够阻挡粘接流动到焊盘区2之外的区域,避免涂胶不均匀和粘胶随意流动。本实施方式中,所述延伸部56突出所述基板12表面的厚度为10um-15um,较佳的,所述厚度为10um。所述延伸部56的材料与所述迹线5的材料相同。在本发明其它实施方式中,所述延伸部56也可以为由PET材料、其它金属材料或塑料等制成。
可以理解,所述焊盘区2的形状依据芯片的形状可以设置为圆形、矩形、多边形等任意形状。所述若干延伸部56沿所述焊盘区2围成的形状也相应的为圆形、矩形、多边形等形状。本实施方式中,所述焊盘区2的形状为圆形。
参阅图3,在本发明第二实施方式中,所述柔性印制电路板1包括第一焊盘31、第二焊盘32、第三焊盘33、第四焊盘34、第五焊盘35和分别与这些焊盘对应连接的第一迹线51、第二迹线52、第三迹线53、第四迹线54和第五迹线55。在本实施方式中,所述第一迹线51和第三迹线53靠近对应焊盘的位置向两侧分别延伸出一延伸部56,所述第四迹线54向所述第五迹线55的方向延伸出延伸部56。
连接于第一迹线51的两延伸部56为一长一短的两段圆弧,较长的延伸部56朝向所述第二迹线52的一侧方向延伸,较短的延伸部56朝向所述第五迹线55的一侧方向延伸。所述较长的延伸部56部分与所述第一迹线51重合。
连接于第三迹线53的两延伸部56为一长一短的两段圆弧,较短的延伸部56朝向所述第二迹线52的另一侧方向延伸,较长的延伸部56朝向所述第四迹线54的一侧方向延伸。
连接于第一迹线51的较短的延伸部56、连接于第四迹线54的延伸部56及连接于所述第三迹线53的较短延伸部56的长度和弧度相同,并且连接于第四迹线54的延伸部56朝向所述第五迹线55延伸。
所述若干延伸部56沿焊盘区2围成一不封闭的圆形。所述第二迹线52设置于连接于第一迹线51的较长延伸部56与连接于第三迹线53的较短延伸部56所形成的缝隙之间。所述第五迹线55设置于连接于第一迹线51的较短延伸部56与连接于第四迹线54的延伸部56所形成的缝隙之间。所述每一迹线位于所述焊盘区2中的部分宽度均相等。连接于每一焊盘的迹线位于所述焊盘区2附近的部分大体平行设置。
参阅图4,本发明第三实施方式与本发明第二实施方式不同在于,所述第一迹线51、第三迹线53及第四迹线54位于所述焊盘区2附近的部分的延伸方向与所述焊盘区2所在圆的径向方向相同。
参阅图5,本发明第四实施方式中,所述柔性印制电路板1包括第一焊盘31、第二焊盘32、第三焊盘33、第四焊盘34、第五焊盘35和分别这些焊盘对应连接的第一迹线51、第二迹线52、第三迹线53、第四迹线54和第五迹线55。在本实施方式中,所述第一迹线51、第二迹线52及第四迹线54靠近对应焊盘的位置向迹线一侧分别延伸出一延伸部56,所述第五迹线55靠近对应第五焊盘35的位置向两侧分别延伸出一延伸部56。
设于第一迹线51上的延伸部56朝向所述第二迹线52方向延伸,设于第二迹线52上的延伸部56朝向所述第三迹线53的方向延伸,连接于第四迹线54上的延伸部56朝向所述第三迹线53延伸。
设于第五迹线55的两延伸部56分别向邻近的第一迹线51和第四迹线54的方向延伸。
所述若干延伸部56沿焊盘区2围成一不封闭的圆形。所述第三迹线53设置于第二迹线52的延伸部56与第四迹线54的延伸部56所形成的缝隙之间。所述每一迹线位于所述焊盘区2中的部分宽度均相等。连接于第二、第三和第五焊盘32、33和35的迹线位于所述焊盘区2附近的部分大体平行设置。连接于第一和第四焊盘31和34的迹线位于所述焊盘区2附近的部分大体平行设置并与所述连接于第二、第三和第五焊盘32、33和35的迹线位于所述焊盘区2附近的部分的延伸方向垂直,连接于所述第五迹线55两侧的延伸部56的长度和弧度相同,以使所述第一、第五焊盘31、35之间的距离与所述第四、第五焊盘34、35之间的距离相同。
可以理解,本发明的柔性印制电路板1上的焊盘3的尺寸大小取决于制造尺寸公差和焊盘3上承载芯片焊接用金球(图未示)的大小。当公差范围大,装配精度低时,焊盘3的尺寸可以增大,当公差范围小,装配精度高时,焊盘3的尺寸减小。焊盘3的尺寸与芯片承载的金球尺寸成正比。
参阅图3,所述柔性印制电路板1还包括至少一组定位标记57,一组定位标记数量至少为两个。本实施方式中,所述定位标记57的个数为四个。所述定位标记57设置于迹线5上,所述定位标记57用于方便芯片装配设备对芯片在柔性印制电路板1上的安装位置进行精确定位。当芯片放置在印刷电路板上时,操作人员通过显示设备观察芯片的精确位置,借助定位标记,便可知道芯片的位置是否出现偏差。本实施方式中,所述定位标记57的材料与所述迹线5相同,其设置于所述迹线5远离所述焊盘区2的位置,以进一步减少所述焊盘区2中的铜箔面积。
参阅图6,本实施方式中,所述迹线5上开设贯穿所述基板12的过孔4,所述过孔4开设于所述迹线远离所述焊盘区2的位置,并且所述迹线5开设所述过孔4的位置的尺寸大于所述迹线5未开设过孔4的尺寸。所述过孔中填充有导电介质,优选的,所述导电介质与所述焊盘3的材料相同。所述过孔4可将所述焊盘3连接于位于所述柔性印制电路板1不同层上的另一焊盘3或迹线4,以完成焊盘3传输的电信号在不同层之间的传输。
可以理解,所述柔性印制电路板1也可以为单面板,所述焊盘3和迹线5设于所述柔性印制电路板1的同一侧的外表面上。
可以理解,所述柔性印制电路板1还可以为双层板,一层为用于连接芯片的焊盘和迹线,另一层为与电子设备沟通的接触盘。比如,所述柔性印制电路板1包括至少两层叠放的基板12,两层基板12之间填充粘胶层,上述焊盘3和迹线5形成与位于柔性印制电路板1的外表层上。其中,位于柔性印制电路板1最外层的电路中的迹线5上开设贯穿所述基板12的盲孔或通孔41。本实施方式中,所述通孔41开设于所述迹线5远离所述焊盘区2的位置,并且所述迹线5开设所述通孔41的位置的尺寸大于所述迹线5未开设通孔41的尺寸。所述通孔41中填充有导电介质,优选的,所述导电介质与所述焊盘3的材料相同,为铜箔。所述通孔可将所述焊盘3连接于位于所述柔性印制电路板1其它层上的另一焊盘3或迹线4,可使焊盘3传输的电信号在不同层之间传输。
本发明的柔性印制电路板1采用圆形的焊盘3,使得所述焊盘区2中铜箔占用面积更小,留有更多的空间贴合PET膜,因此在将芯片安装于焊盘区2的过程中,较大面积的PET膜可以涂抹更多的粘胶,提高芯片与焊盘区2的结构稳定性。
图7根据本发明一个实施例示出了智能卡模块安装在智能卡上的应用性示意结构。在该示意图中,卡体10为一个塑料基板,靠近中间的部分形成空槽。柔性印刷电路板1的一面安装了芯片(图未示出),另一面按照SIM卡标准制成智能卡接触端(如图所示),形成智能卡模块。这样,将智能卡模块置入卡体10,形成完整的智能卡,供用户使用。
由此,本发明令人满意地对实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本发明一部分实施例,而没有穷尽性地例举所有可能的实施例。本领域的技术人员可以对各个实施例中的技术特征进行各种组合以满足实际需要。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。
以上所述,仅为本发明的较佳实施方式,并非是对本发明作任何形式上的限定。另外,本领域技术人员还可在本发明精神内做其它变化,当然,这些依据本发明精神所做的变化,都应包含在本发明所要求保护的范围之内。
Claims (17)
1.一种柔性印制电路板,所述柔性印制电路板的至少一外表面上设置用于安装芯片组件的焊盘区,所述焊盘区上设有若干间隔排布的焊盘和连接于对应焊盘的迹线,其特征在于:所述焊盘区中至少有一焊盘为圆形焊盘。
2.如权利要求1所述的柔性印制电路板,其中所述焊盘区上的焊盘均为圆形焊盘。
3.如权利要求1所述的柔性印制电路板,其中相邻两个焊盘圆心之间的最小间距小于等于177um。
4.如权利要求3所述的柔性印制电路板,其中相邻两个焊盘圆心之间的最小间距等于142um。
5.如权利要求1所述的柔性印制电路板,其中相邻两个焊盘之间的最小间距小于等于75um。
6.如权利要求5所述的柔性印制电路板,其中相邻两个焊盘之间的最小间距等于40um。
7.如权利要求1所述的柔性印制电路板,其中所述若干迹线中至少一条迹线包括延伸部,所述延伸部沿所述焊盘区的边界延伸。
8.如权利要求7所述的柔性印制电路板,其中所述延伸部背离对应的迹线的一端向邻近的另一迹线的方向延伸。
9.如权利要求8所述的柔性印制电路板,其中所述若干延伸部沿所述焊盘区的边界围成一预设形状。
10.如权利要求9所述的柔性印制电路板,其中所述延伸部的厚度为10um-15um。
11.如权利要求10所述的柔性印制电路板,其中所述延伸部的厚度为10um。
12.如权利要求9所述的柔性印制电路板,其中所述延伸部背离对应的迹线的一端与邻近的另一迹线之间绝缘。
13.如权利要求1所述的柔性印制电路板,其中所述每一迹线位于所述焊盘区中的部分宽度均相等。
14.如权利要求2所述的柔性印制电路板,其中至少一根迹线上设置贯通所述基板的过孔,所述过孔中填充导电介质。
15.如权利要求1所述的柔性印制电路板,其中所述柔性印制电路板还包括至少一组定位标记,每一定位标记设于其中一迹线远离所述焊盘区的位置。
16.一种智能卡模块,其特征在于:所述智能卡模块包括芯片和权利要求1-15任一项所述的柔性印制电路板,所述芯片设置于所述柔性印制电路板安装芯片组件的焊盘区位置。
17.一种智能卡,包括卡体,所述板体设置一凹槽,其特征在于:所述智能卡还包括如权利要求16所述的智能卡模块,所述智能卡模块设置于所述板体的凹槽位置。
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DE102017100420.3A DE102017100420A1 (de) | 2016-02-02 | 2017-01-11 | Platine und Smartcardmodul und und die Platine verwendende Smartcard |
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CN108462822B (zh) * | 2018-06-02 | 2024-03-19 | Oppo广东移动通信有限公司 | 光感组件及电子设备 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201146630Y (zh) * | 2008-01-28 | 2008-11-05 | 微盟电子(昆山)有限公司 | 电子载板及焊垫结构 |
US20090194863A1 (en) * | 2008-02-01 | 2009-08-06 | Yu-Nung Shen | Semiconductor package and method for making the same |
CN202758872U (zh) * | 2012-07-09 | 2013-02-27 | 上海华虹集成电路有限责任公司 | 用于安装双界面智能卡芯片的条带单元 |
Family Cites Families (6)
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US6938335B2 (en) * | 1996-12-13 | 2005-09-06 | Matsushita Electric Industrial Co., Ltd. | Electronic component mounting method |
US6404064B1 (en) * | 2000-07-17 | 2002-06-11 | Siliconware Precision Industries Co., Ltd. | Flip-chip bonding structure on substrate for flip-chip package application |
US8994155B2 (en) * | 2012-07-26 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging devices, methods of manufacture thereof, and packaging methods |
FR3006551B1 (fr) * | 2013-05-30 | 2016-12-09 | Linxens Holding | Procede de fabrication d'un circuit imprime, circuit imprime obtenu par ce procede et module electronique comportant un tel circuit imprime |
JP2014236188A (ja) * | 2013-06-05 | 2014-12-15 | イビデン株式会社 | 配線板及びその製造方法 |
DE102014107299B4 (de) * | 2014-05-23 | 2019-03-28 | Infineon Technologies Ag | Chipkartenmodul, Chipkarte, und Verfahren zum Herstellen eines Chipkartenmoduls |
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CN201146630Y (zh) * | 2008-01-28 | 2008-11-05 | 微盟电子(昆山)有限公司 | 电子载板及焊垫结构 |
US20090194863A1 (en) * | 2008-02-01 | 2009-08-06 | Yu-Nung Shen | Semiconductor package and method for making the same |
CN202758872U (zh) * | 2012-07-09 | 2013-02-27 | 上海华虹集成电路有限责任公司 | 用于安装双界面智能卡芯片的条带单元 |
Cited By (1)
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