TW201409632A - 封裝基板之製法 - Google Patents

封裝基板之製法 Download PDF

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TW201409632A
TW201409632A TW101130384A TW101130384A TW201409632A TW 201409632 A TW201409632 A TW 201409632A TW 101130384 A TW101130384 A TW 101130384A TW 101130384 A TW101130384 A TW 101130384A TW 201409632 A TW201409632 A TW 201409632A
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layer
package substrate
load
manufacturing
metal layer
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TW101130384A
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TWI463620B (zh
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白裕呈
林俊賢
蕭惟中
孫銘成
洪良易
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矽品精密工業股份有限公司
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Priority to TW101130384A priority Critical patent/TWI463620B/zh
Priority to CN201210322593.4A priority patent/CN103632980A/zh
Priority to US13/682,134 priority patent/US20140057410A1/en
Publication of TW201409632A publication Critical patent/TW201409632A/zh
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Publication of TWI463620B publication Critical patent/TWI463620B/zh
Priority to US14/755,372 priority patent/US10096491B2/en

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Abstract

一種封裝基板之製法，係包括：提供一以黏著層結合兩承載結構之承載件，該黏著層係黏貼於該兩承載結構之邊緣之非佈線區；形成單一層線路層於該承載結構上；以及分離該兩承載結構，以形成兩具有該承載結構之封裝基板。藉由該承載結構，可於薄化線路層之同時，使該封裝基板具有足夠之剛性進行封裝製程，故於封裝製程後，再移除該承載結構，即可有效降低封裝件之厚度，以達薄化封裝件之目的。

Description

封裝基板之製法
本發明係有關一種半導體封裝基板，尤指一種具有承載結構的封裝基板之製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係朝降低承載晶片之封裝基板的厚度發展。
早期半導體封裝件之製法中，係以具有核心層10之封裝基板1提升整體結構之剛性，如第1A圖所示，以利於後續置晶與封裝製程。該封裝基板1復包含：形成於該核心層10之相對兩側上之複數介電層11、形成於該介電層11上之線路層14、形成於該介電層11中且電性連接該線路層14之複數導電盲孔12、形成於該核心層10中且電性連接該線路層14之複數導電通孔13、及形成於該最外側之介電層11上之防銲層15，且該防銲層15外露該線路層14之部分表面。於後續置晶與封裝製程中，先置放一晶片16於該防銲層15上，且該晶片16藉由複數銲線160電性連接該線路層14，再以封裝膠體17包覆該晶片16與銲線160。
然而，因該封裝基板1具有核心層10，故該封裝基板1之厚度增加，導致整體半導體封裝件之整體高度增加，而難以符合薄化之需求。
再者，因需考量該核心層10之材料成本及製作該導電通孔13之成本，故難以降低該封裝基板1之製作成本。
因此，遂發展出無核心層(coreless)之封裝基板，以達到微小化及省成本之需求。如第1B圖所示，該封裝基板1’之製法係於一承載件(圖略)上形成一無核心層(coreless)之封裝基板1’，再移除該承載件。該封裝基板1’係包含：複數介電層11、形成於該介電層11上之線路層14、形成於該介電層11中且電性連接該線路層14之複數導電盲孔12、及形成於該最外側之介電層11上之防銲層15，且該防銲層15外露該線路層14之部分表面。於後續置晶與封裝製程中，先置放一晶片16於該防銲層15上，且該晶片16藉由複數銲線160電性連接該線路層14，再以封裝膠體17包覆該晶片16與銲線160。
惟，習知封裝基板1’之製法中，於該承載件上僅能以單面製作，故一次製程僅能製造出一批封裝基板1’供封裝製程使用，導致生產效率不佳，而難以降低製作成本。
再者，因該封裝基板1’之厚度愈薄，其剛性越小，且該封裝基板1’亦需具有足夠之剛性供後續置晶或封裝製程時作承載之用，故該封裝基板1’仍需維持一定厚度而難以再薄化，以致於無法進一步薄化封裝件。
因此，如何克服上述習知技術之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種封 裝基板之製法，係包括：提供一承載件，該承載件係結合兩承載結構，該兩承載結構各具有相對之第一側與第二側，且該兩承載結構係以其第二側相結合；形成單一層線路層於該兩承載結構之第一側上；以及分離該兩承載結構，以形成兩具有該承載結構之封裝基板。
前述之製法中，該兩承載結構之第二側係以黏著層黏結，故可移除該黏著層，以分離出該兩封裝基板；或者，該兩承載結構之分離係以沿該第二側之黏著層內側進行切割之方式，令該兩承載結構分開，以分離出該兩封裝基板。又，該黏著層係設置於該兩承載結構之第二側邊緣之非佈線區。
前述之製法中，該兩承載結構之第二側復具有支撐強化件；或者，該承載結構復具有絕緣層、形成於該絕緣層上之介電層、形成於該介電層上之金屬承載層、及形成於該金屬承載層上之金屬層，且令該金屬層形成於該第一側上。
前述之製法中，各該第一側上具有金屬層，且形成該線路層之製程係包括：形成阻層於該金屬層上，且該阻層形成有複數開口以外露部分該金屬層；形成該線路層於該開口中之金屬層上；以及移除該阻層。或者，藉蝕刻該金屬層而形成該線路層。
前述之製法中，該承載結構之第一側與第二側分別具有第一與第二金屬層，各該兩承載結構係以其第二金屬層相互結合。再者，該第一與第二金屬層係為銅箔，且該第 二金屬層係以真空壓合方式相互結合。又，形成該線路層之製程係包括：形成預備金屬層於該第一金屬層上；形成阻層於該預備金屬層上，且該阻層形成有複數開口以外露部分該預備金屬層；移除該開口中之預備金屬層，以令剩餘之該預備金屬層作為該線路層；以及移除該阻層。其中，該預備金屬層係以壓合方式形成於該第一金屬層上。
前述之製法中，復包括形成表面處理層於該線路層上。
另外，前述之製法中，復包括形成防銲層於該承載結構之第一側上。
由上可知，本發明之封裝基板之製法，係藉由在相疊之承載結構兩側製作該線路層，以於一次製程中製造出兩批封裝基板，故相較於習知技術，本發明之製法能有效提升產能。
再者，本發明之封裝基板藉由增設承載結構，可於薄化設計之同時，使該封裝基板具有足夠之剛性進行封裝製程，故於封裝製程後，再移除該承載結構，即可降低封裝件之厚度，以達到進一步薄化封裝件之目的。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝 之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“底”、“第一”、“第二”、“邊緣”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2G圖，係為本發明之封裝基板2之製法之第一實施例之剖視示意圖。
如第2A圖所示，首先，提供一承載件2b，該承載件2b係結合兩承載結構20，各該承載結構20具有相對之第一側20a與第二側20b，且各該第一側20a上具有一金屬層200，並將兩承載結構20以其第二側20b相互疊置。
於本實施例中，該承載結構20之第二側20b邊緣之非佈線區係形成有黏著層21，以藉該黏著層21相互結合兩承載結構20。具體地，該黏著層21係位於對應該第一側20a之佈線區A之外圍。於其它實施例中，亦可於該承載結構20之第二側20b之整面上塗佈該黏著層21。
再者，如第2A’圖所示，各該承載結構20復具有一絕緣層201、形成於該絕緣層201上之一介電層202、形成於該介電層202上之一金屬承載層203，令該金屬層200形成於該金屬承載層203上。其中，該絕緣層201之材質可 例如為FR4，該介電層202之材質可例如為預浸材(prepreg，簡稱PP)，該金屬承載層203與金屬層200係為銅材。
又於另一實施例中，如第2A”圖所示，該兩承載結構20之第二側20b之間可設置一支撐強化件22，以強化兩承載結構20之佈線區A之強度。其中，該支撐強化件22僅以物理方式抵靠該承載結構20，並未以化學方式(如黏貼)結合該承載結構20。
如第2B圖所示，進行圖案化線路製程，先形成一阻層23於該金屬層200上，且該阻層23形成有複數開口230以外露該金屬層200之部分表面。
如第2C圖所示，以該金屬層200為導電途徑，電鍍形成一線路層24於該開口230中之金屬層200上。
如第2D圖所示，形成表面處理層25於該線路層24上，以防止該線路層24氧化。於本實施例中，形成該表面處理層25之材質係為化鎳/金(Ni/Au)、化鎳鈀金(Electroless Nickel/Electroless Palladium/Immersion Gold,ENEPIG)、直接浸金(Direct Immersion Gold,DIG)，電鍍鎳/化鍍鈀/電鍍金、或有機保焊劑(OSP,Organic Solderability Preservative)。
如第2E圖所示，移除該阻層23，以完成單層圖案化線路結構製程。
如第2F及2G圖所示，沿該第二側20b之黏著層21內側進行切割(即該佈線區A之外圍)，如第2F圖所示之 切割線L，令該兩承載結構20自動分開，以分離出兩具有該承載結構20之封裝基板2。
請參閱第3A至3G圖，係為本發明之封裝基板3之製法之第二實施例之剖視示意圖。本實施例與第一實施例之差異在於該承載結構30之態樣與線路層34之製程。
如第3A圖所示，該兩承載結構30之第一側30a與第二側30b上分別具有第一金屬層300與第二金屬層301；接著，將兩承載結構30以其第二金屬層301相互疊置。
於本實施例中，該兩第二金屬層301係以真空壓合方式相互結合，且該第一與第二金屬層300,301係為銅箔，亦即該承載結構30係為銅箔基板(Copper clad laminate,CCL)。
如第3B圖所示，進行圖案化線路製程，先形成預備金屬層34a於該第一金屬層300上。於本實施例中，該預備金屬層34a係以壓合方式形成於該第一金屬層300上，且該預備金屬層34a係為銅箔。
如第3C圖所示，形成一阻層33於該預備金屬層34a上，且該阻層33形成有複數開口330以外露該預備金屬層34a之部分表面。
如第3D圖所示，蝕刻移除該開口330中之預備金屬層34a，以令剩餘之該預備金屬層34a作為線路層34。
如第3E圖所示，移除該阻層33，以完成單層圖案化線路結構製程。
如第3F圖所示，形成表面處理層35於該線路層34 與第一金屬層300上。於本實施例中，該表面處理層300係為銀層。
如第3G圖所示，解除真空狀態，令該兩承載結構30沿該兩第二金屬層301之界面自動分開，以分離出兩具有該承載結構30之封裝基板3。
本發明之製法藉由在疊置之承載結構20,30上、下兩側同時製作該線路層24,34，再將該兩承載結構20,30，以形成兩具有該承載結構20,30的封裝基板2,3。因此，一次製程可同時製作兩批板量，以提升產能，供後續封裝製程使用。
再者，該封裝基板2,3藉由該承載結構20,30，以提升整體封裝基板2,3之強度，故於提升該線路層24,34之薄化程度時，該封裝基板2,3不會破裂。
請參閱第4A至4D圖，係為後續置晶與封裝製程，且以類似第一實施例之封裝基板2為例。
如第4A圖所示，先置放至少一晶片26於該線路層24之置晶區240上，且該晶片26藉由複數銲線260電性連接該線路層24，再以封裝膠體27包覆該晶片26與銲線260。
如第4B圖所示，移除該承載結構20。具體地，係先分離該金屬承載層203與金屬層200，以移除該絕緣層201、該介電層202與金屬承載層203，而保留該金屬層200；再藉由蝕刻方式移除該金屬層200與部分線路層24底側，令該線路層24’之底面低於該封裝膠體27之表面。
若以第二實施例之封裝基板3為例，因該預備金屬層 34a係以壓合方式形成於該金屬層300上，故可直接分離該金屬層300與該線路層34，但需再移除該金屬層300上之表面處理層35。
如第4C圖所示，形成一防銲層28於該封裝膠體27與線路層24’上，且該防銲層28形成有複數開孔280，以外露部分線路層24’之底面。其中，外露於該開孔280之置晶區240可作為該晶片26之散熱途徑。
如第4D圖所示，進行植球製程與切單製程，沿第4C圖所示之切割線S，以取得複數個半導體封裝件2a,2a’，且於該線路層24底部上可結合如銲球之導電元件29。
本發明之封裝基板2,3減去該承載結構20,30的厚度之後，其它結構之總厚度將大幅縮小，故於封裝製程中，將該承載結構20,30移除後，可大幅降低封裝件之整體厚度，以滿足薄化之需求。
再者，即使該線路層24,34極薄化，但該封裝基板2,3藉由該承載結構20,30，以提升整體封裝基板2,3之強度，故於封裝時，該封裝基板2,3不會破裂。
又，於第一與第二實施例中，如第2G’圖所示，可形成一防銲層28於該兩承載結構20之第一側20a上，以包覆該線路層24。
另外，於其它實施例中，亦可直接圖案化蝕刻該金屬層200(或第一金屬層300)以形成線路層。
綜上所述，本發明封裝基板之製法，主要藉由在相疊之承載結構兩側製作該線路層，以形成兩具有該承載結構 的封裝基板，故一次製程可製造出兩批封裝基板，供封裝製程使用。因此，相較於習知技術之產能，本發明之製法有效提升產能，以降低製作成本。
再者，本發明之封裝基板藉由增設承載結構，以於薄化設計之同時，使該封裝基板具有足夠之剛性，以供後續置晶或封裝製程時作承載之用，且於封裝製程時，再移除該承載結構，以有效降低封裝件之厚度，故能滿足封裝件薄化之需求。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,1’,2,3‧‧‧封裝基板
10‧‧‧核心層
11‧‧‧介電層
12‧‧‧導電盲孔
13‧‧‧導電通孔
14,24,24’,34‧‧‧線路層
15,28‧‧‧防銲層
16,26‧‧‧晶片
160,260‧‧‧銲線
17,27‧‧‧封裝膠體
2a,2a’‧‧‧半導體封裝件
2b‧‧‧承載件
20,30‧‧‧承載結構
20a,30a‧‧‧第一側
20b,30b‧‧‧第二側
200‧‧‧金屬層
201‧‧‧絕緣層
202‧‧‧介電層
203‧‧‧金屬承載層
21‧‧‧黏著層
22‧‧‧支撐強化件
23,33‧‧‧阻層
230,330‧‧‧開口
240‧‧‧置晶區
25,35‧‧‧表面處理層
280‧‧‧開孔
29‧‧‧導電元件
300‧‧‧第一金屬層
301‧‧‧第二金屬層
34a‧‧‧預備金屬層
A‧‧‧佈線區
L,S‧‧‧切割線
第1A圖係為習知應用具有核心層之封裝基板所製成之封裝件之剖視示意圖；第1B圖係為習知應用無核心層之封裝基板所製成之封裝件之剖視示意圖；第2A至2G圖係為本發明之封裝基板之製法之第一實施例的剖視示意圖；其中，第2A’圖係為承載結構之局部放大圖，第2A”圖係為第2A圖之另一實施例，第2G’圖係為第2G圖之另一實施例；第3A至3G圖係為本發明之封裝基板之製法之第二實施例的剖視示意圖；以及 第4A至4D圖係為本發明之封裝基板於後續置晶與封裝製程之剖視示意圖。
2‧‧‧封裝基板
20‧‧‧承載結構
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧金屬層
24‧‧‧線路層
25‧‧‧表面處理層

Claims (16)

  1. 一種封裝基板之製法，係包括：提供一承載件，該承載件係結合兩承載結構，該兩承載結構各具有相對之第一側與第二側，且該兩承載結構係以其第二側相結合；形成單一層線路層於該兩承載結構之第一側上；以及分離該兩承載結構，以形成兩具有該承載結構之封裝基板。
  2. 如申請專利範圍第1項所述之封裝基板之製法，其中，該兩承載結構之第二側係以黏著層黏結。
  3. 如申請專利範圍第2項所述之封裝基板之製法，復包括移除該黏著層，以分離出該兩封裝基板。
  4. 如申請專利範圍第2項所述之封裝基板之製法，其中，該兩承載結構之分離係以沿該第二側之黏著層內側進行切割之方式，令該兩承載結構分開，以分離出該兩封裝基板。
  5. 如申請專利範圍第2項所述之封裝基板之製法，其中，該黏著層係設置於該兩承載結構之第二側邊緣之非佈線區。
  6. 如申請專利範圍第1項所述之封裝基板之製法，其中，該兩承載結構之第二側復具有支撐強化件。
  7. 如申請專利範圍第1項所述之封裝基板之製法，復包括形成表面處理層於該線路層上。
  8. 如申請專利範圍第1項所述之封裝基板之製法，其中，該承載結構復具有絕緣層、形成於該絕緣層上之介電層、形成於該介電層上之金屬承載層、及形成於該金屬承載層上之金屬層，且令該金屬層形成於該第一側上。
  9. 如申請專利範圍第1項所述之封裝基板之製法，其中，各該第一側上具有金屬層，且形成該線路層之製程係包括：形成阻層於該金屬層上，且該阻層形成有複數開口以外露部分該金屬層；形成該線路層於該開口中之金屬層上；以及移除該阻層。
  10. 如申請專利範圍第1項所述之封裝基板之製法，其中，各該第一側上具有金屬層，以藉蝕刻該金屬層而形成該線路層。
  11. 如申請專利範圍第1項所述之封裝基板之製法，其中，各該承載結構之第一側與第二側分別具有第一與第二金屬層，該兩承載結構係以其第二金屬層相互結合。
  12. 如申請專利範圍第11項所述之封裝基板之製法，其中，該第一與第二金屬層係為銅箔。
  13. 如申請專利範圍第11項所述之封裝基板之製法，其中，該第二金屬層係以真空壓合方式相互結合。
  14. 如申請專利範圍第1項所述之封裝基板之製法，其中，該承載結構之第一側與第二側分別具有第一與第二金 屬層，供該兩承載結構係以其第二金屬層相互結合，且形成該線路層之製程係包括：形成預備金屬層於該第一金屬層上；形成阻層於該預備金屬層上，且該阻層形成有複數開口以外露部分該預備金屬層；移除該開口中之預備金屬層，以令剩餘之該預備金屬層作為該線路層；以及移除該阻層。
  15. 如申請專利範圍第14項所述之封裝基板之製法，其中，該預備金屬層係以壓合方式形成於該第一金屬層上。
  16. 如申請專利範圍第1項所述之封裝基板之製法，復包括形成防銲層於該承載結構之第一側上。
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US13/682,134 US20140057410A1 (en) 2012-08-22 2012-11-20 Method of fabricating a packaging substrate
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570861B (zh) * 2014-12-03 2017-02-11 恆勁科技股份有限公司 封裝結構及其製法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI548011B (zh) * 2014-05-13 2016-09-01 矽品精密工業股份有限公司 封裝基板及其製法
CN106847778B (zh) * 2015-12-04 2021-06-29 恒劲科技股份有限公司 半导体封装载板及其制造方法
CN118039493A (zh) * 2024-04-12 2024-05-14 芯爱科技(南京)有限公司 封装基板的制法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645791B2 (en) * 2001-04-23 2003-11-11 Fairchild Semiconductor Semiconductor die package including carrier with mask
TW554501B (en) 2002-08-14 2003-09-21 Siliconware Precision Industries Co Ltd Substrate for semiconductor package
US6998327B2 (en) 2002-11-19 2006-02-14 International Business Machines Corporation Thin film transfer join process and multilevel thin film module
US7320173B2 (en) * 2003-02-06 2008-01-22 Lg Electronics Inc. Method for interconnecting multi-layer printed circuit board
JP4541763B2 (ja) * 2004-01-19 2010-09-08 新光電気工業株式会社 回路基板の製造方法
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100621438B1 (ko) 2005-08-31 2006-09-08 삼성전자주식회사 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법
JP4334005B2 (ja) * 2005-12-07 2009-09-16 新光電気工業株式会社 配線基板の製造方法及び電子部品実装構造体の製造方法
JP4912716B2 (ja) * 2006-03-29 2012-04-11 新光電気工業株式会社 配線基板の製造方法、及び半導体装置の製造方法
DE102006033502A1 (de) * 2006-05-03 2007-11-15 Osram Opto Semiconductors Gmbh Strahlungsemittierender Halbleiterkörper mit Trägersubstrat und Verfahren zur Herstellung eines solchen
KR100734403B1 (ko) * 2006-06-02 2007-07-02 삼성전기주식회사 전자소자 패키지 및 그 제조방법
JP5268305B2 (ja) * 2007-08-24 2013-08-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
FI121909B (fi) * 2008-04-18 2011-05-31 Imbera Electronics Oy Piirilevy ja menetelmä sen valmistamiseksi
CN102047396B (zh) * 2008-08-04 2013-01-09 松下电器产业株式会社 柔性半导体装置及其制造方法
KR101095211B1 (ko) * 2008-12-17 2011-12-16 삼성전기주식회사 기판 제조용 캐리어 부재 및 이를 이용한 기판 제조방법
KR101055462B1 (ko) * 2010-01-07 2011-08-08 삼성전기주식회사 인쇄회로기판 제조용 캐리어와 그 제조방법 및 이를 이용한 인쇄회로기판의 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI570861B (zh) * 2014-12-03 2017-02-11 恆勁科技股份有限公司 封裝結構及其製法

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