TW201345356A - Multilayer printed circuit board and method for manufacturing same - Google Patents

Abstract

This disclosure relates to a method for manufacturing a multilayer printed circuit board. The method includes the following steps. First, a substrate including a base layer and a first copper foil is provided. Then the first copper foil is etched to form a first circuit layer, which includes a first exposing portion and a first laminating portion. A first solder mask layer is attached on the first exposing portion. Next, a first alkaline developable resin layer and a third copper foil are laminated on the first circuit layer. A first opening is defined in the third copper foil, and portion of the first alkaline developable resin layer which is corresponding to the first exposing region is exposed. Finally the exposed portion is developed and removed with alkaline solution to form a cavity. The first solder mask layer is exposed in the cavity. A multilayer printed circuit board manufactured by the above-mention method is also provided.

Description

Multilayer circuit board and manufacturing method thereof

The present invention relates to circuit board technology, and more particularly to a multilayer circuit board having a recess and a method of fabricating the same.

In the information, communications and consumer electronics industries, circuit boards are an essential component of all electronic products. With the development of electronic products in the direction of miniaturization and high speed, circuit boards have also evolved from single-sided circuit boards to double-sided circuit boards and multilayer circuit boards. Multilayer boards, especially buried multi-layer boards with embedded electronic components, are widely used, see Takahashi, A. et al., 1992, IEEE Trans. on Components, Packaging, and Manufacturing Technology. The document "High density multilayer printed circuit board for HITAC M~880".

Buried circuit boards typically have a recess to embed electronic components. In the production, it is necessary to first make a multi-layer circuit board, and then use the manual slotting method to dig out the groove. The method of manual slotting not only requires more human resources, but also the precision of manual slotting is not high, which will affect the circuit. Board accuracy and quality.

In view of this, it is necessary to provide a multi-layer circuit board having a groove with a good product quality and a manufacturing method thereof.

Hereinafter, a multilayer circuit board and a method of fabricating the same will be described by way of embodiments.

A manufacturing method of a multi-layer circuit board, comprising the steps of: providing a circuit substrate, the circuit substrate comprising a substrate and a first copper foil layer attached to the surface of the substrate; forming the first copper foil layer into the first conductive circuit layer, The first conductive circuit layer has a first exposed region and a first bonding region; a first solder resist layer is disposed in the first exposed region; and a first germanium developing resin layer is pressed on a side of the first conductive circuit layer of the circuit substrate And a third copper foil layer, the first tantalum developing resin layer is in contact with the surface of the first pressing portion and the surface of the first solder resist layer, and the third copper foil layer is in contact with the first tantalum developing resin layer Forming a first opening corresponding to the first exposed region in the third copper foil layer to expose the first germanium developing resin layer corresponding to the first exposed region; exposing the first germanium exposed from the first opening Developing a resin layer; and dissolving the first enamel developing resin layer of the exposed portion with an alkaline developing solution to form a groove, the first solder resist layer being exposed in the groove.

A manufacturing method of a multi-layer circuit board, comprising the steps of: providing a circuit substrate, the circuit substrate comprising a substrate and a first copper foil layer attached to the surface of the substrate; forming the first copper foil layer into the first conductive circuit layer, The first conductive circuit layer has a first exposed region and a first bonding region; a first solder resist layer is disposed in the first exposed region; and a first germanium developing resin layer is pressed on a side of the first conductive circuit layer of the circuit substrate And a third copper foil layer, the first ruthenium developing resin layer is in contact with the surface of the first nip and the surface of the first solder resist layer, and the third copper foil layer is in contact with the first ruthenium developing resin layer Forming a first opening corresponding to the first exposed region in the third copper foil layer to expose the first germanium developing resin layer corresponding to the first exposed region; exposing the first germanium developed from the first opening a resin layer; a third tantalum developing resin layer and a fifth copper foil layer are pressed on a third copper foil layer side of the circuit substrate, the third tantalum developing resin layer and the third copper foil layer and the first opening The exposed first enamel developing resin layer is in contact with the fifth copper foil layer and a third germanium developing resin layer is in contact; a second opening corresponding to the first opening is formed in the fifth copper foil layer; the third germanium developing resin layer exposed from the second opening is exposed; and the alkaline developing solution is dissolved and removed The third germanium developing resin layer and the first tantalum developing resin layer are exposed to form a groove, and the first solder resist layer is exposed in the groove.

A manufacturing method of a multi-layer circuit board, comprising the steps of: providing a circuit substrate, the circuit substrate comprising a substrate and a first copper foil layer attached to the surface of the substrate; forming the first copper foil layer into the first conductive circuit layer, The first conductive circuit layer has a first exposed region and a first bonding region; a first solder resist layer is disposed in the first exposed region; and a first germanium developing resin layer is pressed on a side of the first conductive circuit layer of the circuit substrate And a third copper foil layer, the first ruthenium developing resin layer is in contact with the surface of the first nip and the surface of the first solder resist layer, and the third copper foil layer is in contact with the first ruthenium developing resin layer Forming a first opening corresponding to the first exposed region in the third copper foil layer to expose the first germanium developing resin layer corresponding to the first exposed region; exposing the first germanium developed from the first opening a resin layer; a third tantalum developing resin layer and a fifth copper foil layer are pressed on a third copper foil layer side of the circuit substrate, the third tantalum developing resin layer and the third copper foil layer and the first opening The exposed first enamel developing resin layer is in contact with the fifth copper foil layer and a third germanium developing resin layer is in contact; a second opening corresponding to the first opening is formed in the fifth copper foil layer; a third germanium developing resin layer exposed from the second opening is exposed; and a fifth copper foil on the circuit substrate The fifth layer of the developing resin layer and the seventh copper foil layer are pressed on one side of the layer, and the fifth tantalum developing resin layer is in contact with the fifth copper foil layer and the third tantalum developing resin layer exposed from the second opening The seventh copper foil layer is in contact with the fifth tantalum developing resin layer; a fourth opening corresponding to the second opening is formed in the seventh copper foil layer; and the fifth tantalum developing resin exposed from the fourth opening is exposed a layer; and a fifth developing resin layer, a third tantalum developing resin layer and a first tantalum developing resin layer which are exposed and removed by an alkaline developing solution to form a groove, the first solder resist layer being exposed to the layer In the groove.

A multilayer circuit board produced by the fabrication method described above. The multilayer circuit board includes a circuit substrate that is sequentially pressed, a first germanium developing resin layer, and a third conductive wiring layer. The circuit substrate includes a substrate and a first conductive circuit layer attached to the surface of the substrate, the first conductive circuit layer has an exposed area and a nip area, and the exposed area is provided with a first solder resist layer. The multilayer circuit board has a recess corresponding to the exposed region, the recess penetrating through the third conductive wiring layer and the first tantalum developing resin layer, the first solder resist layer being exposed in the recess.

A multilayer circuit board comprising a circuit substrate and a laminated substrate that are pressed together. The circuit substrate includes a substrate and a first conductive circuit layer attached to the surface of the substrate, the first conductive circuit layer has an exposed area and a nip area, the surface of the exposed area is provided with a solder resist layer, and the exposed area is The pads are exposed from the solder resist layer. The press-bonding substrate comprises a multi-layered grooved enamel developing resin layer and a plurality of open conductive circuit layers which are press-fitted together, the multi-layered grooved enamel developing resin layer and the multi-layered open conductive circuit layer are alternately arranged, each adjacent There is only one open conductive layer between the two layers of the grooved tantalum developing resin layer. The press-bonding substrate has a groove penetrating through each of the grooved enamel developing resin layer of the press-bonding substrate and each layer of the open conductive layer, the groove corresponding to the solder resist layer, A pad for exposing the solder resist layer and a plurality of exposed regions exposed from the solder resist layer to the electronic component is exposed.

In the process of fabricating the multi-layer circuit board of the present technical solution, the resin layer is developed by press-bonding, and the groove can be conveniently formed by the developing step, so that all the manufacturing processes can be more mature at the current stage. The process is realized, the waste of human resources is eliminated, and the precision of the manufacturing process is high, and the manufactured multi-layer circuit board has good quality, avoiding the error of manual slotting and high scrap rate.

The multi-layer circuit board provided by the technical solution and the manufacturing method thereof will be further described in detail below with reference to the accompanying drawings and embodiments.

The manufacturing method of the multi-layer circuit board provided by the first embodiment of the present technical solution includes the following steps:

In the first step, referring to FIG. 1, a circuit substrate 10 is provided. In the present embodiment, the circuit board 10 is a double-sided copper clad laminate, and includes a first copper foil layer 11, a base 100, and a second copper foil layer 12 that are sequentially bonded from bottom to top. The substrate 100 is an insulating layer composed of an insulating material. In other embodiments, the substrate 100 may be a multi-layer substrate, that is, the substrate 100 may be a structure including a plurality of layers of copper foil layers and insulating layers alternately arranged. In other embodiments, the circuit substrate 10 may be a single-sided copper clad laminate comprising only the first copper foil layer 11 and the substrate 100.

In the second step, referring to FIG. 2 to FIG. 4, the first copper foil layer 11 is formed into a first conductive wiring layer 110, and the second copper foil layer 12 is formed into a second conductive wiring layer 120. The first conductive circuit layer 110 and the second conductive circuit layer 120 each have a plurality of conductive lines and a plurality of conductive contacts, and the first copper foil layer 11 and the second copper foil may be selectively chemically etched by an image transfer process. The layer 12 is formed, and may be formed by selectively ablating the first copper foil layer 11 and the second copper foil layer 12 by laser.

The first conductive wiring layer 110 has a first nip 111 and a first exposed region 112. In the embodiment, the first exposed area 112 has a rectangular shape, and the first pressing area 111 surrounds and surrounds the first exposed area 112. The first exposed region 112 includes a plurality of lines 113 and a plurality of pads 114. After forming the first conductive wiring layer 110 and the second conductive wiring layer 120, a first solder resist layer 21 is disposed in the first exposed region 112, and the first solder resist layer 21 covers the plurality of lines 113 of the first exposed region 112, and The surface of the substrate 100 exposed from the first exposed region 112 is covered while exposing the plurality of pads 114 of the first exposed region 112. The first solder resist layer 21 may be formed by printing or may be formed by lamination.

In the present technical solution, before the first conductive wiring layer 110 and the second conductive wiring layer 120 are formed, the circuit substrate 10 is also drilled to form at least one first through hole, and is electrolessly plated and electroplated. A hole wall of a through hole forms a conductive layer to make the first through hole into the first via hole 101. The first via hole 101 may electrically conduct the first conductive wiring layer 110 and the second conductive wiring layer 120.

In the third step, referring to FIG. 5, the first tantalum developing resin layer 31 and the third copper foil layer 13 are press-bonded on the lower side of the circuit substrate 10 while the second tantalum developing resin layer 32 and the fourth layer are press-fitted on the upper side of the circuit substrate 10. Copper foil layer 14. That is, a first bismuth developing resin layer 31 is placed on the surface of the first nip 111 of the first conductive wiring layer 110 and the surface of the first solder resist layer 21 of the first exposed region 112, in the first enamel developing resin layer 31. A third copper foil layer 13 is placed on the surface while a second enamel developing resin layer 32 is placed on the surface of the second conductive wiring layer 120, and a fourth copper foil layer 14 is placed on the surface of the second enamel developing resin layer 32, and passed through the press machine once. The first tantalum developing resin layer 31, the third copper foil layer 13, the circuit substrate 10, the second tantalum developing resin layer 32, and the fourth copper foil layer 14 are press-bonded.

The materials of the first tantalum developing resin layer 31 and the second tantalum developing resin layer 32 may be the same, both of which are composed of a cerium developing resin, which means acid and alkali resistance when not exposed, and may be alkaline after exposure. A resin material dissolved in the developer. For example, it may be a developing ink of Kawasaki, for example, a photo-developable photoresist; for example, it may be an alkali-developable resin composition in Patent Application No. 200580000757.

Pressing the first tantalum developing resin layer 31, the third copper foil layer 13, the second tantalum developing resin layer 32, and the fourth copper foil layer 14 on both sides of the circuit substrate 10 can be realized by the following steps: first on both sides of the circuit substrate 10 The dry film which can be developed is laminated, and then the copper foil is respectively attached to the dry film, and finally pressed together by a press machine. Of course, it can also be achieved by printing the ink that can be developed on the upper side of the circuit substrate 10, bonding the copper foil on the ink printed on the upper side, and then inverting the circuit substrate 10, and also passing the printing ink and the laminated copper foil. After the process, the press is finally performed by a press machine.

After the first tantalum developing resin layer 31, the third copper foil layer 13, the second tantalum developing resin layer 32, and the fourth copper foil layer 14 are press-bonded on both sides of the circuit substrate 10, the laser drilling process and the electroless copper plating process may be performed. And an electroplating copper process to form an electrically conductive first blind via 102 between the third copper foil layer 13 and the first conductive wiring layer 110 to form a conductance between the fourth copper foil layer 14 and the second conductive wiring layer 120. The second blind via 103 is opened, thereby electrically conducting the fourth copper foil layer 14, the second conductive wiring layer 120, the first conductive wiring layer 110 and the third copper foil layer 13, as shown in FIG.

In the fourth step, referring to FIG. 6 and FIG. 7 , a first opening 131 corresponding to the first exposed region 112 is formed in the third copper foil layer 13 , and the first opening 131 is exposed to correspond to the first exposed region 112 . The first tantalum developing resin layer 31 is exposed, and the first tantalum developing resin layer 31 exposed from the first opening 131 is exposed.

Simultaneously with or after forming the first opening 131 in the third copper foil layer 13, the third copper foil layer 13 is also formed into a third conductive wiring layer 130, and the fourth copper foil layer 14 is made into a fourth conductive line. Layer 140. The third conductive circuit layer 130 and the fourth conductive circuit layer 140 each include a plurality of conductive lines and a plurality of conductive contacts. Thus, the four-layer substrate 10a can be obtained.

That is to say, the conductive lines and the conductive contacts of the third conductive circuit layer 130 may be formed by etching simultaneously with the first opening 131, or may be formed by step etching. Alternatively, in this step, the third copper foil layer 13 may be selectively etched by an image transfer process to form the third copper foil layer 13 into the third conductive wiring layer 130 having the first opening 131, and then Exposing the first tantalum developing resin layer 31 exposed from the first opening 131; the material of the third copper foil layer 13 at the first opening 131 may also be selectively removed by a first image transfer process to Forming the first opening 131, then exposing the first tantalum developing resin layer 31 exposed from the first opening 131, and then removing the portion corresponding to the first pressing area 111 by the second image transfer process and selectively etching The material of the three copper foil layers 13 forms a conductive line and a conductive contact of the third conductive wiring layer 130. The conductive lines and the conductive contacts of the fourth conductive circuit layer 140 may be formed simultaneously with the conductive lines and the conductive contacts of the third conductive circuit layer 130.

In the fifth step, referring to FIG. 8, the partially exposed first developed resin layer 31 is removed by dissolving with an alkaline developing solution to form a first recess 41. The first solder resist layer 21 is exposed in the first recess 41. The pad 114 in the first exposed region 112 of the first conductive wiring layer 110 exposed from the first solder resist layer 21 is also exposed in the first recess 41. The alkaline developer may be a NaOH solution having a pH > 13 or a KOH solution having a pH > 13.

The surface of the third conductive wiring layer 130 may be formed before the exposed first conductive resin layer 31 is dissolved in an alkaline developing solution, or after the third conductive wiring layer 130 is formed, or after the first recess 41 is formed. A second solder resist layer 22 is disposed, and a third solder resist layer 23 is disposed on the surface of the fourth conductive wiring layer 140. Thus, the four-layer circuit board 10b can be obtained.

Preferably, the second solder resist layer 22 and the third solder resist layer 23 may be formed before the exposed first developing resin layer 31 is removed by dissolving in an alkaline developing solution.

The four-layer circuit board 10b obtained according to the above steps of the first embodiment, as shown in FIG. 8, includes a fourth conductive wiring layer 140, a second germanium developing resin layer 32, a circuit substrate 10, and a first layer which are sequentially pressed together. The resin layer 31 and the third conductive wiring layer 130 are developed. The circuit substrate 10 includes a second conductive wiring layer 120, a substrate 100, and a first conductive wiring layer 110 which are sequentially bonded. The first to fourth conductive circuit layers 110 to 140 are electrically conducted through the first via hole 101, the first blind via hole 102, and the second blind via hole 103. The four-layer circuit board 10b has a first recess 41 penetrating through the third conductive wiring layer 130 and the first tantalum developing resin layer 31, so that the first protection provided in the first exposed region 112 of the first conductive wiring layer 110 The solder layer 21 and the pads 114 exposed from the first solder resist layer 21 in the first exposed region 112 are exposed in the first recess 41. The first recess 41 can be used for accommodating electronic components such that the electronic components are mounted on the pads 114 exposed from the first solder resist layer 21 in the first exposed region 112, so that the electronic components are not occupied. External space.

Those skilled in the art will appreciate that the steps in the method of fabricating a multilayer circuit board of the first embodiment are not all necessary technical features. For example, in the third step, the first tantalum developing resin layer 31 and the third copper foil layer 13 may be press-bonded only on the lower side of the circuit substrate 10 without simultaneously pressing the second tantalum developing resin layer 32 on the upper side of the circuit substrate 10. And the fourth copper foil layer 14, and thus, after the subsequent steps, a three-layer circuit board having one groove can be formed.

In addition to fabricating a three-layer circuit board or a four-layer circuit board having one recess, the present technology can fabricate a multilayer circuit board of any number of layers having any number of grooves. Hereinafter, an eight-layer circuit board having two recesses will be described as an example.

A method for fabricating a multilayer circuit board according to a second embodiment of the present technical solution includes the steps of:

In the first step, referring to Fig. 7, a four-layer substrate 10a obtained by the first to fourth steps of the first embodiment is provided.

As described above, the four-layer substrate 10a includes the fourth conductive wiring layer 140, the second germanium developing resin layer 32, the second conductive wiring layer 120, the substrate 100, and the first conductive wiring layer 110 which are sequentially pressed from top to bottom. The first tantalum developing resin layer 31 and the third conductive wiring layer 130.

In the second step, referring to FIG. 9 and FIG. 10, in the four-layer substrate 10a, the fourth conductive circuit layer 140 is defined to include a second pressing area 141 and a second exposed area 142, and in the second exposed area. A second solder resist layer 24 is disposed on 142.

In the embodiment, the second exposed area 142 is also rectangular, and the second pressing area 141 surrounds and surrounds the second exposed area 142. The second exposed region 142 includes a plurality of lines 143 and a plurality of pads 144. The second solder resist layer 24 covers the plurality of lines 143 of the second exposed region 142 and covers the surface of the second tantalum developing resin layer 32 exposed from the second exposed portion 142 while exposing the plurality of second exposed regions 142 Pad 144.

In the third step, referring to FIG. 11, the third tantalum developing resin layer 33 and the fifth copper foil layer 15 are press-bonded on the lower side of the four-layer substrate 10a, and the fourth tantalum developing resin layer 34 and the first side are laminated on the upper side of the circuit substrate 10. Six copper foil layers 16. That is, the third tantalum developing resin layer 33 is placed on the surface of the third conductive wiring layer 130 and the surface of the first tantalum developing resin layer 31 exposed from the first opening 131, and the fifth surface is placed on the surface of the third tantalum developing resin layer 33. The copper foil layer 15 is simultaneously placed on the surface of the second nip region 141 of the fourth conductive wiring layer 140 and the surface of the second solder resist layer 24, and the sixth enamel developing resin layer 34 is placed on the surface of the fourth enamel developing resin layer 34. The copper foil layer 16 is pressed together with the sixth copper foil layer 16, the fourth tantalum developing resin layer 34, the four-layer substrate 10a, the third tantalum developing resin layer 33, and the fifth copper foil layer 15 by a press.

Pressing the third tantalum developing resin layer 33, the fifth copper foil layer 15, the fourth tantalum developing resin layer 34, and the sixth copper foil layer 16 on both sides of the four-layer substrate 10a can be performed by the third step in the first embodiment. The approximate method is implemented. After the third tantalum developing resin layer 33, the fifth copper foil layer 15, the fourth tantalum developing resin layer 34, and the sixth copper foil layer 16 are press-bonded on both sides of the four-layer substrate 10a, laser drilling and electroless copper plating can be performed. a process and an electroplating copper process to form a third conductive via 104 electrically conductive between the fifth copper foil layer 15 and the third conductive wiring layer 130 to form a gap between the sixth copper foil layer 16 and the fourth conductive wiring layer 140. Conducting a fourth blind via 105 such that the sixth copper foil layer 16, the fifth copper foil layer 15, the fourth conductive wiring layer 140, the third conductive wiring layer 130, the second conductive wiring layer 120, and the first conductive line Layer 110 achieves electrical conduction as shown in FIG.

In the fourth step, referring to FIG. 12, a second opening 151 corresponding to the first opening 131 is formed in the fifth copper foil layer 15, and a third opening corresponding to the second exposed region 142 is formed in the sixth copper foil layer 16. 161, and exposing the third tantalum developing resin layer 33 exposed from the second opening 151 and the fourth tantalum developing resin layer 34 exposed from the third opening 161.

Simultaneously with or after the second opening 151 is formed in the fifth copper foil layer 15, the fifth copper foil layer 15 is also formed into a fifth conductive wiring layer 150, and the sixth copper foil layer 16 is formed into a sixth conductive wiring. The layer 160 is formed to form a six-layer substrate 10c. The fifth conductive circuit layer 150 and the sixth conductive circuit layer 160 each include a plurality of conductive lines and a plurality of conductive contacts. In general, the conductive lines and the conductive contacts of the fifth conductive circuit layer 150 and the sixth conductive circuit layer 160 can be simultaneously formed.

The conductive lines and the conductive contacts of the fifth conductive circuit layer 150 and the sixth conductive circuit layer 160 may be simultaneously etched with the second opening 151 and the third opening 161, or may be formed by step etching. Taking the fifth copper foil layer 15 as an example, in this step, the fifth copper foil layer 15 may be selectively etched by an image transfer process to form the fifth copper foil layer 15 with the second opening 151. a fifth conductive wiring layer 150, and then exposing the third germanium developing resin layer 33 exposed from the second opening 151; the second opening 151 may also be removed by a first image transfer process and selectively etching a material of the five copper foil layer 15 to form a second opening 151, and then exposing the third tantalum developing resin layer 33 exposed from the second opening 151, and then selectively etching and removing the corresponding image by a second image transfer process The material of the fifth copper foil layer 15 except the second opening 151 forms a conductive line and a conductive contact of the fifth conductive wiring layer 150.

In the fifth step, referring to Fig. 13, the fifth enamel developing resin layer 35 and the seventh copper foil layer 17 are press-bonded on the lower side of the six-layer substrate 10c while the sixth enamel developing resin layer 36 is press-bonded on the upper side of the six-layer substrate 10c. The eighth copper foil layer 18. That is, the fifth tantalum developing resin layer 35 is placed on the surface of the fifth conductive wiring layer 150 and the surface of the third tantalum developing resin layer 33 exposed from the second opening 151, and the seventh surface is placed on the surface of the fifth tantalum developing resin layer 35. The copper foil layer 17 is simultaneously placed on the surface of the sixth conductive wiring layer 160 and the surface of the fourth tantalum developing resin layer 34 exposed from the third opening 161, and placed on the surface of the sixth tantalum developing resin layer 36. The eighth copper foil layer 18 is then press-bonded to the eighth copper foil layer 18, the sixth tantalum developing resin layer 36, the six-layer substrate 10c, the fifth tantalum developing resin layer 35, and the seventh copper foil layer 17 by a press machine. .

Pressing the fifth tantalum developing resin layer 35, the seventh copper foil layer 17, the sixth tantalum developing resin layer 36, and the eighth copper foil layer 18 on both sides of the six-layer substrate 10c can be performed by the third step in the first embodiment. The approximate method is implemented. After the fifth layer of the developing resin layer 35, the seventh copper foil layer 17, the sixth tantalum developing resin layer 36, and the eighth copper foil layer 18 are pressed on both sides of the six-layer substrate 10c, laser drilling and electroless plating may be performed. a copper process and an electroplating copper process to form a fifth conductive via 106 electrically conductive between the seventh copper foil layer 17 and the fifth conductive wiring layer 150 between the eighth copper foil layer 18 and the sixth conductive wiring layer 160 Forming a sixth conductive via 107 electrically conductive, and forming a second via 108 in the six-layer substrate 10c, such that the eighth copper foil layer 18, the seventh copper foil layer 17, the sixth conductive wiring layer 160, and the fifth conductive layer The circuit layer 150, the fourth conductive circuit layer 140, the third conductive circuit layer 130, the second conductive circuit layer 120, and the first conductive circuit layer 110 are electrically conductive, as shown in FIG.

In the sixth step, referring to FIG. 14, a fourth opening 171 corresponding to the second opening 151 is formed in the seventh copper foil layer 17, and a fifth opening 181 corresponding to the third opening 161 is formed in the eighth copper foil layer 18. And exposing the fifth tantalum developing resin layer 35 exposed from the fourth opening 171 and the sixth tantalum developing resin layer 36 exposed from the fifth opening 181.

Simultaneously with or after the fourth opening 171 is formed in the seventh copper foil layer 17, the seventh copper foil layer 17 is also formed into a seventh conductive wiring layer 170, and a fifth opening 181 is formed in the eighth copper foil layer 18. At the same time or after, the eighth copper foil layer 18 is also formed into the eighth conductive wiring layer 180. Thus, the eight-layer substrate 10d can be fabricated. In general, the fourth opening 171 and the fifth opening 181 may be simultaneously formed, and the seventh conductive wiring layer 170 and the eighth conductive wiring layer 180 may be simultaneously formed. The conductive lines and the conductive contacts of the seventh conductive circuit layer 170 and the eighth conductive circuit layer 180 may be simultaneously etched with the fourth opening 171 and the fifth opening 181, or may be formed by step etching. When the step etching is formed, the exposing step may be performed after the fourth opening 171 and the fifth opening 181 are formed, before the seventh conductive wiring layer 170 and the eighth conductive wiring layer 180 are formed, or the seventh conductive wiring may be formed. The layer 170 and the eighth conductive wiring layer 180 are performed later.

In the seventh step, referring to FIG. 14 and FIG. 15, the fifth developing resin layer 35, the third tantalum developing resin layer 33, the first tantalum developing resin layer 31, and the sixth portion of the exposed portion are dissolved and removed by an alkaline developing solution. The developing resin layer 36 and the fourth developing resin layer 34 are formed, thereby forming the first groove 42 and the second groove 43. The enamel-developing resin layer of the exposed portion can be removed by dissolving the eight-layer substrate 10d in the alkaline developing solution for a certain period of time or by spraying the alkaline developing solution on both sides of the eight-layer substrate 10d.

Specifically, the exposed fifth ruthenium developing resin layer 35 is exposed from the fourth opening 171, and can be dissolved and removed by the alkaline developing solution, and after the fifth 堿 developing resin layer 35 of the exposed portion is dissolved and removed, from the second opening 151 The exposed third crucible developing resin layer 33 will also be contacted with the alkaline developing solution to be dissolved and removed, and then the same first developing resin layer 31 exposed from the first opening 131 will also be in contact with the alkaline developing solution to be Dissolving and removing, thus, forming through the seventh conductive wiring layer 170, the fifth germanium developing resin layer 35, the fifth conductive wiring layer 150, the third germanium developing resin layer 33, the third conductive wiring layer 130, and the first germanium developing The first groove 42 of the resin layer 31. The first solder resist layer 21 is exposed in the first recess 42. Similarly, the exposed sixth ruthenium developing resin layer 36 exposed from the fifth opening 181 can be dissolved and removed by the alkaline developing solution, and after the sixth 堿 developing resin layer 36 of the exposed portion is dissolved and removed, from the third opening The exposed fourth crucible developing resin layer 34 of 161 is brought into contact with the alkaline developing solution to be dissolved and removed, and thus, the eighth conductive wiring layer 180, the sixth tantalum developing resin layer 36, and the sixth conductive wiring layer 160 may be formed. The second groove 43 of the fourth developing resin layer 34. The second solder mask layer 24 is exposed to the second recess 43. The alkaline developer may be a NaOH solution having a pH > 13 or a KOH solution having a pH > 13.

Before the exposed enamel developing resin layer is dissolved with an alkaline developing solution, or after the seventh conductive wiring layer 170, the eighth conductive wiring layer 180 is formed, or after the first recess 42 and the second recess 43 are formed, A third solder resist layer 25 may be disposed on the surface of the seventh conductive wiring layer 170, and a fourth solder resist layer 26 may be disposed on the surface of the eighth conductive wiring layer 180. Thus, the eight-layer circuit board 10e can be obtained. Preferably, the third solder resist layer 25 and the fourth solder resist layer 26 may be formed before the exposed enamel developing resin layer is dissolved in an alkaline developing solution.

The eight-layer circuit board 10e obtained according to the above steps of the second embodiment is as shown in FIG. 15, and includes an eighth conductive wiring layer 180, a sixth germanium developing resin layer 36, and a sixth conductive wiring layer 160 which are sequentially pressed. a fourth germanium developing resin layer 34, a fourth conductive wiring layer 140, a second germanium developing resin layer 32, a circuit substrate 10, a first germanium developing resin layer 31, a third conductive wiring layer 130, a third germanium developing resin layer 33, The fifth conductive wiring layer 150, the fifth germanium developing resin layer 35, and the seventh conductive wiring layer 170. The circuit substrate 10 includes a second conductive wiring layer 120, a substrate 100, and a first conductive wiring layer 110 which are sequentially bonded. The first to eighth conductive circuit layers 110 to 180 are electrically conducted through the first via hole 101 and the first to sixth and sixth blind via holes 102 to 107. The eight-layer circuit board 10e has a through-seventh conductive wiring layer 170, a fifth germanium developing resin layer 35, a fifth conductive wiring layer 150, a third germanium developing resin layer 33, a third conductive wiring layer 130, and a first germanium developing layer. The first recess 42 of the resin layer 31 is such that the first solder resist layer 21 and the pads 114 exposed from the first solder resist layer 21 are exposed in the first recess 42. The eight-layer circuit board 10e further has a second recess 43 penetrating through the eighth conductive wiring layer 180, the sixth tantalum developing resin layer 36, the sixth conductive wiring layer 160, and the fourth tantalum developing resin layer 34, so that the second The solder resist layer 24 and the pads 144 exposed from the second solder resist layer 24 are exposed to the second recess 43. The first recess 42 and the second recess 43 can both be used for accommodating electronic components, so that the electronic components can be mounted on the pads 114 exposed from the first solder resist layer 21 in the first exposed region 112. It can also be mounted on the pad 144 exposed from the second solder resist layer 24 in the second exposed region 142, so that the electronic component does not occupy the external space.

Those skilled in the art will appreciate that variations of the above steps of the present teachings can be used to make other layers of multi-layer boards having other numbers of grooves. For example, a six-layer circuit board having two grooves can be fabricated by the first to fourth steps of the second embodiment and the step of developing. That is, if the six-layer substrate 10c in FIG. 12 is dissolved by the alkaline developing solution, a six-layer circuit board having grooves of two different depths, one of which penetrates the sixth conductive wiring layer 160 and the fourth, can be obtained. The ruthenium developing resin layer 34 has another groove penetrating through the fifth conductive wiring layer 150, the third ruthenium developing resin layer 33, the third conductive wiring layer 130, and the first ruthenium developing resin layer 31. Further, for example, in the above steps of the second embodiment, the first tantalum developing resin layer 31, the third copper foil layer 13, the third tantalum developing resin layer 33, and the fifth copper are added only to the lower side of the circuit substrate 10. The foil layer 15, the fifth tantalum developing resin layer 35, and the seventh copper foil layer 17 are not added to the upper side of the circuit substrate 10 to form the second tantalum developing resin layer 32, the fourth copper foil layer 14, and the fourth tantalum developing resin layer 34. The sixth copper foil layer 16, the sixth tantalum developing resin layer 36, and the eighth copper foil layer 18 are formed into a groove having a groove by making an opening, exposing, making a conductive wiring layer, and developing. a layer circuit board penetrating through the seventh conductive wiring layer 170, the fifth germanium developing resin layer 35, the fifth conductive wiring layer 150, the third germanium developing resin layer 33, the third conductive wiring layer 130, and the first germanium developing resin Layer 31. For example, if the first tantalum developing resin layer 31, the third copper foil layer 13, the third tantalum developing resin layer 33, and the fifth copper foil layer 15 are added only on the lower side of the circuit board 10, without adding any other a layer, after the steps of making an opening, exposing, making a conductive wiring layer, and developing, a four-layer circuit board having a groove penetrating through the fifth conductive wiring layer 150 and the third germanium developing resin layer 33. The third conductive wiring layer 130 and the first germanium developing resin layer 31. Of course, it is also possible to fabricate a multilayer circuit board having other layers of other structures by the modification of the steps of the above embodiments.

Those skilled in the art can understand that the multilayer circuit board fabricated by the technical solution can be considered to include the circuit substrate 10 and the pressed substrate which are pressed together. The circuit substrate 10 includes a first conductive wiring layer 110, and the first exposed region 112 of the first conductive wiring layer 110 is provided with a solder resist layer. The number of layers of the press-bonded substrate depends on the number of press-fits, and includes a multi-layered grooved enamel-developing resin layer and a plurality of open-ended conductive circuit layers that are pressed together. For example, it may include a three-layered grooved enamel developing resin layer and a three-layered open conductive layer, as shown in FIG. 15, on the lower side of the circuit substrate 10, the seventh conductive wiring layer 170, and the fifth ruthenium developing resin layer 35. A press-bonding substrate composed of a fifth conductive wiring layer 150, a third germanium developing resin layer 33, a third conductive wiring layer 130, and a first germanium developing resin layer 31. The multi-layered grooved enamel developing resin layer and the plurality of open conductive circuit layers are alternately arranged, and there is only one open conductive layer between each adjacent two layers of the enamel developing resin layer. The press-bonding substrate has a groove penetrating through each of the grooved enamel developing resin layer of the press-bonding substrate and each layer of the open conductive layer, the groove and the first exposed area 112 being disposed Corresponding to the solder resist layer, such that the solder resist layer and the plurality of pads 114 of the first exposed region 112 exposed from the solder resist layer are exposed in the recess for receiving electrons Components.

In the process of fabricating the multi-layer circuit board of the present technical solution, the resin layer is developed by press-bonding, and the groove can be conveniently formed by the developing step, so that all the manufacturing processes can be more mature at the current stage. The process is realized, eliminating the waste of human resources, and making the precision of the manufacturing process high, avoiding the error of manual slotting and high scrap rate.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

10. . . Circuit substrate

11. . . First copper foil layer

100. . . Base

12. . . Second copper foil layer

110. . . First conductive circuit layer

120. . . Second conductive circuit layer

111. . . First nip

112. . . First exposed area

113, 143. . . line

114, 144. . . Pad

twenty one. . . First solder mask

101. . . First via

31. . . First enamel developing resin layer

13. . . Third copper foil layer

32. . . Second enamel developing resin layer

14. . . Fourth copper foil layer

102. . . First blind via

103. . . Second blind via

131. . . First opening

140. . . Fourth conductive circuit layer

130. . . Third conductive circuit layer

10a. . . Four-layer substrate

41, 42. . . First groove

10b. . . Four-layer circuit board

22, 24. . . Second solder mask

23, 25. . . Third solder mask

141. . . Second nip

142. . . Second exposed area

33. . . Third enamel developing resin layer

15. . . Fifth copper foil layer

34. . . Fourth enamel developing resin layer

16. . . Sixth copper foil layer

104. . . Third blind via

105. . . Fourth blind via

151. . . Second opening

161. . . Third opening

10c. . . Six-layer substrate

150. . . Fifth conductive circuit layer

160. . . Sixth conductive layer

35. . . Fifth enamel developing resin layer

17. . . Seventh copper foil layer

36. . . Sixth developing resin layer

18. . . Eighth copper foil layer

106. . . Fifth blind guide hole

107. . . Sixth blind via

171. . . Fourth opening

181. . . Fifth opening

170. . . Seventh conductive layer

180. . . Eightth conductive layer

10d. . . Eight-layer substrate

43. . . Second groove

26. . . Fourth solder mask

10e. . . Eight-layer board

FIG. 1 is a schematic diagram of a circuit substrate provided by an embodiment of the present technical solution.

2 is a schematic view showing a state in which a copper foil layer in the circuit substrate of FIG. 1 is formed into a conductive wiring layer.

Figure 3 is a bottom plan view of Figure 2.

4 is a schematic view of the circuit board of FIG. 3 after the first solder resist layer is disposed.

Fig. 5 is a schematic view showing a state in which a bismuth-developing resin laminated copper foil layer is press-bonded on both sides of Fig. 4, respectively.

Fig. 6 is a schematic view showing a first opening corresponding to the first solder resist layer in the lower copper foil layer of the circuit board of Fig. 5;

Fig. 7 is a schematic view showing that the upper and lower copper foil layers of Fig. 6 are made into a conductive wiring layer to obtain a four-layer substrate.

Figure 8 is a schematic illustration of a four-layer circuit board having recesses made of the four-layer substrate of Figure 7.

Figure 9 is a bottom plan view of Figure 7.

FIG. 10 is a schematic view showing a second solder resist layer provided on the four-layer substrate of FIG. 7. FIG.

Fig. 11 is a schematic view showing a state in which a tantalum-developed resin laminated copper foil layer is press-bonded on both sides of the four-layer substrate of Fig. 10, respectively.

Fig. 12 is a schematic view showing the upper and lower copper foil layers of Fig. 11 as a conductive wiring layer to obtain a six-layer substrate.

Fig. 13 is a schematic view showing a state in which a bismuth-developing resin laminated copper foil layer is press-bonded on both sides of the six-layer substrate of Fig. 12, respectively.

Fig. 14 is a schematic view showing the upper and lower copper foil layers of Fig. 13 as a conductive wiring layer.

Figure 15 is a schematic illustration of an eight-layer circuit board having two recesses made from the eight-layer substrate of Figure 14.

110. . . First conductive circuit layer

120. . . Second conductive circuit layer

130. . . Third conductive circuit layer

140. . . Fourth conductive circuit layer

150. . . Fifth conductive circuit layer

160. . . Sixth conductive layer

170. . . Seventh conductive layer

180. . . Eightth conductive layer

31. . . First enamel developing resin layer

32. . . Second enamel developing resin layer

33. . . Third enamel developing resin layer

34. . . Fourth enamel developing resin layer

35. . . Fifth enamel developing resin layer

36. . . Sixth developing resin layer

twenty one. . . First solder mask

twenty four. . . Second solder mask

25. . . Third solder mask

26. . . Fourth solder mask

42. . . First groove

43. . . Second groove

10e. . . Eight-layer board

Claims (15)

A method for manufacturing a multilayer circuit board, comprising the steps of:
Providing a circuit substrate, the circuit substrate comprising a substrate and a first copper foil layer attached to the surface of the substrate;
Forming a first copper foil layer into a first conductive circuit layer, the first conductive circuit layer having a first exposed region and a first bonding region;
Providing a first solder resist layer in the first exposed area;
Pressing a first enamel developing resin layer and a third copper foil layer on a side of the first conductive circuit layer of the circuit substrate, the first 堿 developing resin layer contacting the surface of the first nip area and the surface of the first solder resist layer The third copper foil layer is in contact with the first tantalum developing resin layer;
Forming a first opening corresponding to the first exposed region in the third copper foil layer to expose the first germanium developing resin layer corresponding to the first exposed region;
Exposing a first enamel developing resin layer exposed from the first opening; and dissolving and removing the exposed first developing enamel resin layer with an alkaline developing solution to form a groove, the first solder resist layer being exposed to the In the groove. The method for fabricating a multilayer circuit board according to claim 1, wherein when the first opening corresponding to the first exposed region is formed in the third copper foil layer, the third copper foil layer is further formed Three conductive circuit layers. The method for fabricating a multilayer circuit board according to claim 1, wherein the third copper foil layer is formed into a third conductive wiring layer after exposing the first tantalum developing resin layer exposed from the first opening. . The method for fabricating a multilayer circuit board according to claim 2, wherein the second conductive circuit layer is provided with a second surface before the first developing resin layer of the exposed portion is dissolved and removed by the alkaline developing solution. Solder mask. The method for fabricating a multilayer circuit board according to claim 1, wherein the alkaline developing solution is a NaOH solution having a pH of more than 13, or a KOH solution having a pH of more than 13. The method for fabricating a multilayer circuit board according to claim 1, wherein the first conductive resin layer and the third copper foil layer are laminated on the first conductive wiring layer side of the circuit substrate.
Bonding a developable photoresist dry film on the first conductive wiring layer side of the circuit substrate as the first ruthenium developing resin layer;
The third copper foil layer is bonded to the photoresist dry film; and the circuit substrate, the photoresist dry film, and the third copper foil layer are laminated at a time by a press machine. The method for fabricating a multilayer circuit board according to claim 1, wherein the first conductive resin layer and the third copper foil layer are laminated on the first conductive wiring layer side of the circuit substrate.
Printing a developable ink layer on the side of the first conductive circuit layer of the circuit substrate as the first germanium developing resin layer;
The third copper foil layer is bonded to the printed ink layer; and the circuit substrate, the ink layer and the third copper foil layer are laminated once by a press machine. The method of manufacturing the multilayer circuit board of claim 1, wherein the circuit substrate further comprises a second copper foil layer, the substrate being bonded between the first copper foil layer and the second copper foil layer When the first copper foil layer is made into the first conductive circuit layer, the second copper foil layer is also formed into the second conductive circuit layer; and the first conductive resin is pressed on the first conductive circuit layer side of the circuit substrate. In the layer and the third copper foil layer, the second alkali developing resin layer and the fourth copper foil layer are further pressed on the second conductive wiring layer side of the circuit substrate, the second germanium developing resin layer and the second conductive line The surface of the layer is in contact with the second copper foil layer in contact with the second tantalum developing resin layer; and after forming the first opening or after exposing the first tantalum developing resin layer exposed from the first opening, The third copper foil layer is formed into a third conductive wiring layer, and the fourth copper foil layer is also formed into a fourth conductive wiring layer; before being dissolved in the alkaline developing solution to remove the exposed first photosensitive resin layer, in the third a second solder resist layer is disposed on the surface of the conductive circuit layer, and the fourth conductive circuit layer is in the surface The third solder mask is provided on the surface. A method for manufacturing a multilayer circuit board, comprising the steps of:
Providing a circuit substrate, the circuit substrate comprising a substrate and a first copper foil layer attached to the surface of the substrate;
Forming a first copper foil layer into a first conductive circuit layer, the first conductive circuit layer having a first exposed region and a first bonding region;
Providing a first solder resist layer in the first exposed area;
Pressing a first enamel developing resin layer and a third copper foil layer on a side of the first conductive circuit layer of the circuit substrate, the first 堿 developing resin layer contacting the surface of the first nip and the surface of the first solder resist layer The third copper foil layer is in contact with the first tantalum developing resin layer;
Forming a first opening corresponding to the first exposed region in the third copper foil layer to expose the first germanium developing resin layer corresponding to the first exposed region;
Exposing the first enamel developing resin layer exposed from the first opening;
Pressing a third germanium developing resin layer and a fifth copper foil layer on a side of the third copper foil layer of the circuit substrate, the third germanium developing resin layer and the third copper foil layer and the exposed from the first opening The first enamel developing resin layer is in contact, and the fifth copper foil layer is in contact with the third ruthenium developing resin layer;
Forming a second opening corresponding to the first opening in the fifth copper foil layer;
Exposing a third ruthenium developing resin layer exposed from the second opening; and dissolving the third ruthenium developing resin layer and the first ruthenium developing resin layer of the exposed portion with an alkaline developing solution to form a groove, the first A solder mask is exposed to the recess. The method of manufacturing the multilayer circuit board of claim 9, wherein the circuit substrate further comprises a second copper foil layer, the substrate being bonded between the first copper foil layer and the second copper foil layer When the first copper foil layer is made into the first conductive circuit layer, the second copper foil layer is also formed into the second conductive circuit layer; and the first conductive resin is pressed on the first conductive circuit layer side of the circuit substrate. In the layer and the third copper foil layer, the second alkali developing resin layer and the fourth copper foil layer are further pressed on the second conductive wiring layer side of the circuit substrate, the second germanium developing resin layer and the second conductive line The surface of the layer is in contact with the second copper foil layer in contact with the second tantalum developing resin layer; and after forming the first opening or after exposing the first tantalum developing resin layer exposed from the first opening, The third copper foil layer is formed into a third conductive circuit layer, and the fourth copper foil layer is also formed into a fourth conductive circuit layer; the third germanium developing resin layer and the fifth layer are pressed on the third copper foil layer side of the circuit substrate In the copper foil layer, the fourth alkaline display is also pressed on the fourth conductive circuit layer side of the circuit substrate. a shadow resin layer and a sixth copper foil layer, the fourth tantalum developing resin layer is in contact with a surface of the fourth conductive wiring layer, the sixth copper foil layer is in contact with the fourth tantalum developing resin layer; and the second opening is formed Simultaneously or after exposing the third tantalum developing resin layer exposed from the second opening, the fifth copper foil layer is also made into the fifth conductive wiring layer, and the sixth copper foil layer is also made into the sixth conductive wiring layer. Before the third developing resin layer and the first tantalum developing resin layer of the exposed portion are dissolved and removed by the alkaline developing solution, a second solder resist layer is disposed on the surface of the fifth conductive wiring layer, and the surface of the sixth conductive wiring layer is disposed on the surface of the sixth conductive wiring layer Three solder masks. A method for manufacturing a multilayer circuit board, comprising the steps of:
Providing a circuit substrate, the circuit substrate comprising a substrate and a first copper foil layer attached to the surface of the substrate;
Forming a first copper foil layer into a first conductive circuit layer, the first conductive circuit layer having a first exposed region and a first bonding region;
Providing a first solder resist layer in the first exposed area;
Pressing a first enamel developing resin layer and a third copper foil layer on a side of the first conductive circuit layer of the circuit substrate, the first 堿 developing resin layer contacting the surface of the first nip and the surface of the first solder resist layer The third copper foil layer is in contact with the first tantalum developing resin layer;
Forming a first opening corresponding to the first exposed region in the third copper foil layer to expose the first germanium developing resin layer corresponding to the first exposed region;
Exposing the first enamel developing resin layer exposed from the first opening;
Pressing a third germanium developing resin layer and a fifth copper foil layer on a side of the third copper foil layer of the circuit substrate, the third germanium developing resin layer and the third copper foil layer and the exposed from the first opening The first enamel developing resin layer is in contact, and the fifth copper foil layer is in contact with the third ruthenium developing resin layer;
Forming a second opening corresponding to the first opening in the fifth copper foil layer;
Exposing a third enamel developing resin layer exposed from the second opening;
Pressing a fifth tantalum developing resin layer and a seventh copper foil layer on a side of the fifth copper foil layer of the circuit substrate, the fifth tantalum developing resin layer and the fifth copper foil layer and the second opening The third tantalum developing resin layer is in contact with, and the seventh copper foil layer is in contact with the fifth tantalum developing resin layer;
Forming a fourth opening corresponding to the second opening in the seventh copper foil layer;
Exposing a fifth enamel developing resin layer exposed from the fourth opening; and dissolving and removing the exposed ninth developing resin layer, the third ytterbium developing resin layer, and the first ytterbium developing resin layer in an alkali developing solution, thereby forming a recess, the first solder mask being exposed in the recess. The method of manufacturing the multilayer circuit board of claim 11, wherein the circuit substrate further comprises a second copper foil layer, the substrate being bonded between the first copper foil layer and the second copper foil layer When the first copper foil layer is made into the first conductive circuit layer, the second copper foil layer is also formed into the second conductive circuit layer; and the first conductive resin is pressed on the first conductive circuit layer side of the circuit substrate. In the layer and the third copper foil layer, the second alkali developing resin layer and the fourth copper foil layer are further pressed on the second conductive wiring layer side of the circuit substrate, the second germanium developing resin layer and the second conductive line The surface of the layer is in contact with the second copper foil layer in contact with the second tantalum developing resin layer; and after forming the first opening or after exposing the first tantalum developing resin layer exposed from the first opening, The third copper foil layer is formed into a third conductive circuit layer, and the fourth copper foil layer is also formed into a fourth conductive circuit layer; the third germanium developing resin layer and the fifth layer are pressed on the third copper foil layer side of the circuit substrate In the case of the copper foil layer, the fourth alkaline layer is also pressed on the fourth conductive circuit layer side of the circuit substrate. a shadow resin layer and a sixth copper foil layer, the fourth tantalum developing resin layer is in contact with a surface of the fourth conductive wiring layer, the sixth copper foil layer is in contact with the fourth tantalum developing resin layer; and the second opening is formed Simultaneously or after exposing the third tantalum developing resin layer exposed from the second opening, the fifth copper foil layer is also made into the fifth conductive wiring layer, and the sixth copper foil layer is also made into the sixth conductive wiring layer. When the fifth enamel developing resin layer and the seventh copper foil layer are laminated on the fifth copper foil layer side of the circuit substrate, the sixth enamel developing resin layer and the first layer are also pressed on the sixth conductive wiring layer side of the circuit substrate. An eight-copper foil layer, the sixth tantalum developing resin layer is in contact with a surface of the sixth conductive wiring layer, the eighth copper foil layer is in contact with the sixth tantalum developing resin layer; at the same time as forming the fourth opening or in exposure After the fifth enamel developing resin layer exposed in the fourth opening, the seventh copper foil layer is further formed into a seventh conductive wiring layer, and the eighth copper foil layer is also formed into an eighth conductive wiring layer; The developing solution dissolves and removes the fifth 堿 developing resin layer of the exposed portion, and the third 堿Before the developing resin layer and the first tantalum developing resin layer, a second solder resist layer is disposed on the surface of the seventh conductive wiring layer, and a third solder resist layer is disposed on the surface of the eighth conductive wiring layer. A multilayer circuit board formed by the manufacturing method of the first aspect of the patent application, the multilayer circuit board comprising a circuit substrate, a first germanium developing resin layer and a third conductive circuit layer, which are sequentially pressed, the circuit The substrate comprises a substrate and a first conductive circuit layer attached to the surface of the substrate, the first conductive circuit layer has an exposed area and a nip area, and the exposed area is provided with a first solder resist layer, and the multilayer circuit board has a groove corresponding to the exposed region, the groove penetrating through the third conductive circuit layer and the first tantalum developing resin layer, and the first solder resist layer is exposed in the groove. The multilayer circuit board of claim 1, wherein the exposed area comprises a plurality of lines and a plurality of pads, the plurality of pads being exposed from the first solder resist layer and thereby being exposed to the recess The recess is configured to receive an electronic component, and the multi-layer circuit board further includes a second germanium developing resin layer, a fourth conductive circuit layer, a second solder resist layer, and a third solder resist layer, the circuit substrate Further including a second conductive wiring layer, the substrate is bonded between the first conductive wiring layer and the second conductive wiring layer, and the second germanium developing resin is laminated on the fourth conductive wiring layer and the second conductive wiring layer The second solder resist layer is disposed on the surface of the third conductive circuit layer, and the third solder resist layer is disposed on the surface of the fourth conductive circuit layer. A multi-layer circuit board comprising a circuit substrate and a laminated substrate laminated together, the circuit substrate comprising a substrate and a first conductive circuit layer attached to a surface of the substrate, the first conductive circuit layer having an exposed area and a press-fit a surface of the exposed region provided with a solder resist layer, and a plurality of pads of the exposed region are exposed from the solder resist layer, the press-bonded substrate comprising a plurality of trenched germanium developing resin layers laminated together a multi-layered open conductive layer, the multi-layered grooved developing resin layer and the plurality of open conductive circuit layers are alternately arranged, and each adjacent two layers of the grooved tantalum developing resin layer has only one open conductive layer between them. The press-bonding substrate has a groove penetrating through each of the grooved enamel developing resin layer of the press-bonding substrate and each layer of the open conductive layer, the groove corresponding to the solder resist layer, A pad for exposing the solder resist layer and a plurality of exposed regions exposed from the solder resist layer to the electronic component is exposed.