KR20020022477A - Manufacturing method for build-up multi layer printed circuit board using physical vapor deposition - Google Patents

Abstract

PURPOSE: A method for manufacturing a build-up multi layer printed circuit board is provided to obtain fine circuit pattern and highly reliable via-hole by using physical vapor deposition. CONSTITUTION: Manufacturing of a build-up multi layer printed circuit board is initiated by forming a two sides or multi layer center substrate at steps b1 and b2. At step b3, photo developed insulating resin layer(320) is formed on the top side and/or the bottom side of the center substrate. At step b4, a via-hole(330) is formed by exposure/development on the resin layer(320). At step b5, physical/chemical surface treatment is performed. At step b6, physical vapor deposition is performed. At step b7, a metal deposition film(340) is formed on the inside of the via-hole(330) and the surface of the resin layer(320). At step b8, a metal conductor layer(350) is formed by electrical plating on the metal deposition film(340). At step b9, a circuit pattern is formed by etching the metal conductor layer(350). At step b10, the prescribed steps are repeated. At step b11, post processing such as solder resist appliance, marking and boundary physical processing.

Description

MANUFACTURING METHOD FOR BUILD-UP MULTI LAYER PRINTED CIRCUIT BOARD USING PHYSICAL VAPOR DEPOSITION}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a build-up multilayer printed circuit board, and in particular, an insulating layer made of a photo developing insulating resin or a thermosetting insulating resin is formed on an upper surface and / or a lower surface of a double-sided or multilayered central substrate, and the predetermined layer is formed on the insulating layer. By forming a via hole in the via hole and forming a deposited film on the surface of the via hole and the surface of the insulating layer by using a physical vapor deposition method, it is possible not only to produce a uniform and good metal conductor layer, but also to electroplat the metal conductor layer if necessary. The present invention relates to a method for manufacturing a build-up multilayer printed circuit board using physical vapor deposition to easily obtain a metal conductor layer having a desired thickness.

Printed circuit boards are the most basic components of many electronic products that are currently manufactured. In recent years, high density multilayer printed circuit boards for miniaturization have been widely used in cell phones, PCS, IMT 2000, notebooks, palmtops, camcorders, and ball grid arrays (BGAs). It is widely applied to package substrates for semiconductors such as chip scale packaging (CSP) and multi chip module (MCM).

Referring to Figure 1 will be described the manufacturing process of manufacturing a build-up multilayer printed circuit board by laminating an insulating resin board having a copper foil (copper foil) on a central substrate.

In the conventional embodiment shown in FIG. 1, in the first step (a1), a double side copper clad laminate is used as the base substrate. The said double-sided copper clad laminated board means the board | substrate with which copper foil 1 was coated on both surfaces.

In the second step (a2), in order to connect the upper and lower conductor layers of the double-sided copper clad laminate, the through hole 3 is drilled, the plated through hole is plated, and the copper foil 4 is formed inside the hole. The upper and lower copper foils 1 are connected by the copper foil 4 inside the hole. In addition, since the plated through hole has a cavity, the filler 5 is filled therein to fill the through hole. And the copper foil of both upper and lower sides is etched, and the 1st conductor layer 2 of a desired pattern is formed.

In the third (a3) process, the RCC (resin coated copper foil) is pressed and laminated on the upper and lower surfaces of the base substrate subjected to the (a2) process. The RCC refers to the adhesive insulating resin 7 is coated on one surface of the copper foil (6).

In the fourth step (a4), the copper foil 6 of the portion 8 for forming the via hole on the surface of the laminated RCC is etched to expose the insulating resin 7.

In the fifth process (a5), via holes are formed through the insulating resin 7 with a laser drill to expose the first conductor layer 2 of the base substrate.

In the sixth step (a6), the inside of the via hole 12 is plated to connect the first conductor layer 2 and the second conductor layer 11.

In the seventh step (a7), the second conductor layer 11 is etched to form the desired conductor pattern 13.

In the eighth step (a8), the steps (a3) to (a5) are repeated to form the third conductor layer and the third insulating layer and are processed to the via hole 14.

In the ninth step (a9), the through holes 15 for interlayer connection and mounting of parts are drilled.

In the tenth step (a10), the via holes 16 and the inside 17 of the through holes 15 are plated to connect the respective conductor layers.

In the eleventh (a11) process, the third conductor layer is etched to form a desired conductor pattern 18.

In the twelfth (a12) process, the via hole 19 is filled with a filler and the solder register 20 is coated. In this step, the via hole 19 may not be plugged.

As described above, the process of manufacturing a multilayer printed circuit board by stacking RCCs on the top and bottom surfaces thereof, respectively, using a double-sided printed circuit board as a center substrate was described. Recently, the diameter of via holes in printed circuit boards is gradually decreasing due to the miniaturization, light weight, and thickness of electronic products. In the case of such fine via holes, plating on the inner surface of a blind via hole and a via hole having a large aspect ratio is high in technical difficulty, and according to the general electroless plating method, even if the plating is performed, the plating adhesion is high depending on the reliability such as adhesion. A problem arises.

With reference to FIG. 2, this technical problem will be described by looking at a cross-sectional view of a multilayer printed circuit board having a conductor layer formed by a conventional technique.

In the manufacturing process of the build-up multilayer printed circuit board using an insulating resin plate having a copper foil, the electroless plating layer 210 and the electroplating layer 220 are formed on the existing copper foil 200, so that the metal conductor layer as a whole is formed. Will be thicker. When the thickness of the metal conductor layer becomes thick, it is impossible to manufacture a fine circuit pattern in an etching process for manufacturing a circuit pattern in the future. The reason is that the metal conductor layer cannot be etched beyond a certain level of aspect ratio because it has a constant etch factor according to the type of etchant used in the etching process.

As described above, according to the manufacturing method of the conventional build-up multilayer printed circuit board, the thickness of the metal conductor layer becomes excessively thick, making it impossible to process the fine circuit pattern, and there is a problem in the reliability of electroless plating for minute via holes. It can be seen that it occurs.

Therefore, the present invention has been made to solve the above problems, the present invention is to form a via hole in the insulating layer formed on the upper surface and / or lower surface of the center substrate by an exposure / development process or a laser processing process, and the inside of the via hole and By forming at least one metal conductor layer having a predetermined thickness on the inside of the via hole and the surface of the insulating resin layer through a surface treatment process and a physical vapor deposition method on the insulating layer to manufacture a build-up multilayer printed circuit board, a fine circuit pattern And to provide a method for manufacturing a build-up multilayer printed circuit board using a physical vapor deposition method having a high reliability via hole.

A preferred embodiment of the present invention for achieving the above object is a first step of manufacturing a double-sided or multi-layer printed circuit board as a central substrate; A second step of forming a photo developing insulating resin layer on an upper surface and / or a lower surface of the central substrate; A third step of forming a via hole in the photo developing insulating resin layer through an exposure / development process; A fourth step of performing physical / chemical surface treatment for removing residues remaining in the via hole and for surface treatment of the insulating resin layer; A fifth process of performing surface modification treatment to improve physical vapor deposition characteristics using plasma in the physical and chemical surface-treated via holes and the insulating resin layer; A sixth step of forming a metal conductor layer having a predetermined thickness through physical vapor deposition on the inside of the surface modified via hole and the surface of the insulating resin layer; A seventh step of forming a desired circuit pattern by etching the metal conductor layer formed in the step; And / or an eighth process of repeating the process on the formed build-up multilayer printed circuit board to manufacture a build-up multilayer printed circuit board having a desired number of layers, applying and marking a solder register to the build-up multilayer printed circuit board, physical outline processing, and the like. It provides a build-up multilayer printed circuit board manufacturing method using a physical vapor deposition method further comprising a ninth step of the post-processing process.

In the present invention, the first process is a double-sided or multi-layer printed circuit board manufacturing process by the existing manufacturing method, it can be subjected to the oxidation (oxide) treatment for the improvement of the interlayer adhesion.

In the present invention, the second step is to compress the photo-developed insulating resin substrate in the form of a film on the upper and / or lower surface of the central substrate or to the upper and / or lower surface of the liquid photo-developed insulating resin The insulating resin layer may be prepared by applying one or more times. When the film-type photo developing insulating resin plate is pressed onto the upper and / or lower surface of the center substrate, the pressing process may be a vacuum lamination method, a roller pressing method, or a pressing crimping method. The reliability of the crimping process can be increased under an atmosphere such as temperature or vacuum.

In the present invention, the third step is an exposure step of irradiating light to the photo-developable insulating resin layer through a film for producing a predetermined pattern, and developing the via hole under conditions that conform to the specifications of the insulating resin irradiated with the light. One embodiment may be configured including a developing process to be formed.

Another embodiment of the present invention for achieving the above object is a first step of manufacturing a double-sided or multi-layer printed circuit board as a central substrate; Forming a thermal curable dielectric layer on an upper surface and / or a lower surface of the central substrate; A step S3 of forming via holes in the thermosetting insulating resin layer through laser processing; A S4 process of performing physical / chemical surface treatment for removing residues remaining in the via hole and surface treatment of the insulating resin layer; S5 step of performing a surface modification treatment to improve the physical vapor deposition characteristics by using a plasma in the internal and insulating resin layer of the physical / chemical surface treatment via hole; A step S6 of forming a metal conductor layer having a predetermined thickness through physical vapor deposition on the inside of the surface modified via hole and the surface of the insulating resin layer; A seventh step of etching the metal conductor layer formed in the step to form a desired circuit pattern; And / or step S8 of manufacturing the build-up multilayer printed circuit board having a desired number of layers by repeating the process on the formed build-up multilayer printed circuit board, coating and marking solder resist on the build-up multilayer printed circuit board, physical outline processing, and the like. It provides a build-up multilayer printed circuit board manufacturing method using a physical vapor deposition method characterized in that it further comprises a S9 process which is a post-processing process.

In another embodiment of the present invention, the thermosetting insulating resin layer may be formed by laminating a thermosetting insulating resin plate in the form of a film or applying the liquid thermosetting insulating resin one or more times. In addition, in each embodiment of the present invention, as well as photographic development type insulating resin, thermosetting insulating resin, various insulating materials may be applied.

In each embodiment of the present disclosure, the fourth process may further include filling a conductive paste into the surface-treated via hole and curing the surface to form a filled via.

Also, in each embodiment of the present disclosure, the sixth process may further include a process of tilting the surface-modified substrate at a predetermined angle to move along a predetermined trajectory to form a uniform metal conductor layer in the via hole. In addition, the step of forming a deposition film having a predetermined thickness by using a physical vapor deposition method on the inside of the surface-modified via hole and the surface of the insulating resin layer, and / or by electroplating the formed deposition film as a seed layer It can comprise the process of forming the metal conductor layer of predetermined thickness which consists of a vapor deposition film and an electroplating layer.

1 is a conventional build-up multilayer printed circuit board manufacturing process diagram

2 is a cross-sectional view of a build-up multilayer printed circuit board having a conductor layer formed by a conventional technique.

3 is a manufacturing process diagram of the build-up multilayer printed circuit board using the physical vapor deposition method according to an embodiment of the present invention

4A to 4B are cross-sectional views of a build-up multilayer printed circuit board using physical vapor deposition method completed by one embodiment and another embodiment of the present invention.

5 is a manufacturing process diagram of the build-up multilayer printed circuit board using physical vapor deposition according to another embodiment of the present invention

200: copper foil 210: electroless plating layer

220, 350: Electroplated layer 320: Photo developing insulating resin

330: via hole 335: residue

340: physical vapor deposition film 360: fine circuit pattern

370: solder register 510: filled via

These objects, features and advantages of the present invention will be more readily understood by reference to the accompanying drawings and the following detailed description.

Hereinafter, the present invention proposes a method of manufacturing a multilayer printed circuit board having a six-layer structure by a build-up method as a preferred embodiment, but the manufacturing method according to the present invention is not limited or limited thereto and is variously modified by those skilled in the art. Of course it can be done.

Hereinafter, with reference to the embodiment shown in the drawings, the present invention will be described in more detail.

3 is a manufacturing process diagram illustrating a method for manufacturing a build-up multilayer printed circuit board using physical vapor deposition according to an embodiment of the present invention, the first process (b1, b2) of manufacturing a double-sided or multi-layered central substrate, A second step (b3) of forming a photo developing insulating resin layer capable of exposing and developing the upper and / or lower surfaces of the central substrate; and forming a via hole in the photo developing insulating resin layer through an exposure / development process. A third step (b4), a fourth step (b5) of performing physical / chemical surface treatment for removing residues remaining in the via hole and surface treatment of the insulating resin layer, and the physical / chemical surface treatment of the via hole. Step 5 (b6), which is a surface modification process for improving physical vapor deposition characteristics by using plasma on the inner and insulating resin layers, and physical vapor deposition on the surfaces of the surface modified via hole and the surface of the insulating resin layer. Step 6-1 (b7) of manufacturing a metal deposition film having a predetermined thickness through the step; step 6-2 (b8) of forming a metal conductor layer by electroplating the metal deposition film formed in the step; and in the step A seventh step (b9) of etching the formed metal conductor layer to form a desired circuit pattern, and / or repeating the above step on the build-up multilayer printed circuit board using the formed physical vapor deposition method, using a physical vapor deposition method having a desired number of layers. The eighth step (b10) of manufacturing a build-up multilayer printed circuit board, and the ninth step (b11) of post-processing processes such as applying and marking a solder register to the build-up multilayer printed circuit board and physical outline processing are shown. Build-up multilayer printed circuit boards using the physical vapor deposition method completed by the process are shown in FIGS. 4A and 4B.

In addition, as another embodiment of the present invention, the insulating layer formed on the upper surface and / or lower surface of the center substrate in the process (b3) of Figure 3 is not shown in the drawing, but instead of the photo-developable insulating resin layer thermosetting insulation It can be formed using a thermal curable dielectric. In this case, the thermosetting insulating resin layer may be formed by laminating a thermosetting insulating resin plate in the form of a film or applying the liquid thermosetting insulating resin one or more times. In addition, in each embodiment of the present invention, as well as photographic development type insulating resin, thermosetting insulating resin, various insulating materials may be applied. In addition, the process of forming the via hole in the insulating layer formed by the thermosetting insulating resin is performed differently from the process of forming the via hole by the exposure and development process of FIG. 3 (b4). Via holes are formed in the insulating layer formed by the thermosetting insulating resin through laser processing performed by a laser drill. The subsequent process is performed in the same manner as the process of FIG. 3 (b5) and the subsequent processes.

Each embodiment of the present invention may further include filling a conductive paste into the via hole surface-treated through the step (b5) and curing the same to form a filled via.

In addition, in each embodiment of the present invention, the sixth process may further include a process of tilting the surface-modified substrate at a predetermined angle to move along a predetermined trajectory to form a uniform metal conductor layer in the via hole. .

In each embodiment of the present invention, a double-sided printed circuit board is used as the center board. According to the present invention, it is a matter of course that the multilayer printed circuit board can be applied as the center substrate.

In the first steps (b1, b2), a double-sided printed circuit board having upper and lower conductor layers is formed by forming predetermined plated through-holes and conductor patterns on a double-sided copper clad laminate having copper foil coated on both sides of the insulating layer. It is a process of manufacturing. Since the plated through hole has a cavity, it can be filled with a filler such as ink or conductive paste therein to fill the cavity. In addition, an oxide treatment may be performed to improve interlayer adhesion.

The second step (b3) is a step of forming a photo developing insulating resin layer that can be exposed and developed on the upper and / or lower surfaces of the center substrate.

In the third step (b4), the photodevelopable insulating resin layer is subjected to an exposure process by light through a film for producing a predetermined pattern, and a developing process is performed under conditions that conform to the specifications of the photodevelopable insulating resin. Forming process.

The fourth step (b5) is a step of performing physical / chemical processing for removing residues in the via holes and surface treatment of the insulating resin layer formed by the third step.

The fifth step (b6) is a surface modification step of improving physical vapor deposition characteristics using plasma in the via hole and the insulating resin layer of the physically and chemically surface-treated via holes by the fourth step.

The sixth step (b7) is a step of manufacturing a metal deposition film having a predetermined thickness through physical vapor deposition on the surface of the via hole and the insulating resin layer surface-modified by the fifth step. This process is a process that replaces the existing electroless plating and is capable of forming excellent plating adhesion and a uniform conductor layer compared to the electroless plating. In addition, it is possible to form a high quality conductor layer as compared to the electroless plating, thereby improving the electrical reliability. As a deformable example of the step 6-1, first, a deposition film having a predetermined thickness is manufactured by physical vapor deposition on an insulating layer using a less reactive metal, and then a deposition film is formed of another type of metal on the deposition film. The process of improving the reliability of a metal vapor deposition film by completing a seed layer is also applicable.

In the sixth step (b8), electroplating is performed using the metal deposition film formed in the sixth step as a seed layer to form a metal conductor layer composed of the metal deposition film and the electroplating layer. This step is a step of performing general electroplating on the conductor layer formed by the step 6-1, which is a step that can further increase the mass productivity. The conductor layer formed in the step 6-1 is excellent in electrical and physical properties, but when plated to a predetermined thickness or more, the production efficiency is reduced, it is effective to apply this process when a conductor layer of a certain thickness or more is required. . On the other hand, if the conductor layer of the thin film is required, the present step 6-2 may be omitted.

The seventh step (b9) is a step of forming a desired circuit pattern by etching the metal conductor layers formed in the steps 6-1 and 6-2.

The eighth step (b10) is a build-up multilayer printed circuit board using the physical vapor deposition method of the desired number of layers by repeating the second step to the seventh step to the build-up multilayer printed circuit board using the physical vapor deposition method formed. It is a process of manufacturing.

The ninth step (b11) is a post-processing step including the application and marking of the solder register, physical outline processing and the like.

Hereinafter, with reference to Figures 3 to 6 will be described in more detail the overall operation of an embodiment of the present invention.

In an embodiment of the present invention, a double-sided printed circuit board is used, but a multilayer printed circuit board having four or more layers may be applied.

In the step (b1), a double-sided copper clad laminate 300 is prepared to manufacture a central substrate, which is a basis for manufacturing a multilayer printed circuit board.

In the conventional build-up multi-layer printed circuit board manufacturing process, to connect the upper and lower conductor layers of the double-sided copper clad laminate, through-holes are drilled and plated to connect the upper and lower conductor patterns, and to prevent the cavity of the plating through-holes. Fillers were used.

In the step (b2) of the present invention, the cavity is blocked by using a conductive paste or a filler inside the plated through hole 310. Therefore, in the case of using a conductive paste, it will be possible to manufacture a plated through hole having higher electrical reliability.

In the step (b3), the photo developing insulating resin layer 320 is formed on the upper and / or lower surfaces of the central substrate. In this case, the method of forming the insulating resin layer may be a film-type photo developing insulating resin pressed on the upper and / or lower surface of the central substrate, or a liquid photo developing insulating resin on the upper and / or lower surface of the central substrate. The method of apply | coating times or more and drying can be used. In the case of pressing a film-type insulating resin film onto a center board, a roller pressing method or a press pressing method may be used, and a pressing process may be performed using a vacuum laminator or a vacuum hot press. It is also possible to increase the reliability by applying time vacuum.

In the step (b4), the via hole 330 for interlayer connection is formed by exposure / development of the photo developing insulating resin. This is a process of forming a via hole for electrically connecting two or more different conductor layers in a multilayer printed circuit board, which is the most important part in manufacturing a build-up multilayer printed circuit board. In the exposure process, first, a manufacturing film for exposure is manufactured, and then the light of the reaction wavelength is irradiated onto the photo-developing insulating resin through the film for manufacturing in an exposure machine having a wavelength at which the photo-developing insulating resin reacts. At this time, a difference in physical and chemical composition occurs between the portion irradiated with light and the portion not irradiated onto the photoresist insulating resin.

After the exposure process is completed, the exposed photo-developed insulating resin layer (a portion where the light is irradiated physically or chemically or unchanged) is developed to form a via hole 330 of a desired shape.

In the developing step, a developer of any concentration is sprayed to melt the via hole portion. The developer may be water, an aqueous alkali solution, an alcohol, an organic solvent, or the like under conditions that conform to the specifications of the used photo developing resin. In addition, the developing characteristics can develop the via holes of a desired shape and dimension by adjusting the developing force at an arbitrary injection pressure and flow rate according to the conditions in accordance with the specifications of the used photo developing insulating resin.

In the step (b5), physical / chemical processing is performed for removing residues in the via holes and surface treatment of the insulating resin layer formed by the process. The physical processing is scrubbing for surface flatness and foreign matter removal, and the chemical processing refers to a chemical treatment for removing residue and forming surface roughness. This physical and chemical processing is to improve the electrical properties of the build-up multilayer printed circuit board by removing the contaminants remaining on the surface of the via hole and the surface of the insulating resin layer and the plating adhesion and the better adhesion during the formation of the conductor layer.

In the step (b6), the surface of the via hole and the surface of the insulating resin layer physically and chemically treated in the above process is modified with plasma to improve physical vapor deposition characteristics. When the conductor layer is formed through physical vapor deposition, the bonding of atomic units rather than molecular units such as plating is performed, and thus, ionized metal may be better deposited on the inside of the via hole and the surface of the insulating resin layer. It is possible to activate these surfaces by surface treatment under certain conditions using a plasma.

In the step (b7), the physical vapor deposition film 340 is formed on the inside of the surface-modified via hole and the surface of the insulating resin layer through physical vapor deposition. In this case, in order to efficiently deposit the metal deposition film into the via hole, it is also possible to allow a constant orbital movement in a tilting state of the printed circuit board. Unlike the electroless plating, the metal deposition film formed by the physical vapor deposition method achieves the bonding of atomic units, and thus it is possible to obtain better plating adhesion and to control the purity of the conductor layer by simply changing the target. As a result, a deposited film having excellent electrical characteristics can be obtained. In addition, it is also possible to apply a variety of metal materials, in order to improve the reliability of the deposited film to form a less reactive metal deposition film to form an inter metal layer (inter metal layer), and then another deposited metal film having excellent conductivity on the intermediate metal layer It is also possible to form a step to complete the seed layer. The intermediate metal layer prevents diffusion, migration, delamination of the insulating layer and the deposited film, and serves to improve the reliability of the deposited film. In addition, since the thickness of the deposited film is formed in comparison with the electroless plating, it has a great influence on the uniformity of the electroplating, thereby improving the performance of the build-up multilayer printed circuit board using physical vapor deposition as a whole. Does not cause.

In the step (b8), electroplating is performed at a desired thickness using the metal deposition film formed in the above step as a seed layer, thereby completing a metal conductor layer composed of the metal deposition film and the electroplating layer 350. In the case of the physical vapor deposition method, the production efficiency is reduced in order to form a metal deposition film having a predetermined thickness or more, so the metal deposition film by the physical vapor deposition method is effectively used as a seed layer for electroplating. However, in order to manufacture the fine circuit pattern, the thickness of the formed metal deposition film needs to be thin, so that when the fine circuit pattern is formed by forming the thin metal deposition film, the electroplating process may be omitted.

In step (b9), the metal conductor layer completed in the step is etched to produce a desired circuit pattern 360. In the conventional process, after the insulating resin plate including the copper foil is pressed, electroless plating and electroplating are performed for plating the inside of the via hole, so that the thickness of the entire metal conductor layer becomes very thick. When the thickness of the metal conductor layer becomes thick, the etchable aspect ratio depending on the etch factor is determined according to the type of etchant to be used, thus making it impossible to manufacture a fine circuit pattern. However, in the present invention, since the metal deposition layer to be used as the seed layer is formed on the insulating resin layer without the conductor layer by physical vapor deposition, and the electroplating is formed thereon, the thickness of the overall metal conductor layer is reduced. It is possible to manufacture a finer circuit pattern. After the circuit pattern is manufactured, plugging of the via hole may be performed.

In step (b10), build-up is performed by repeating the steps (b3) to (b9) to manufacture a build-up multilayer printed circuit board using a physical vapor deposition method with a desired number of layers.

Step (b11) is a post-process, and the build-up multilayer printed circuit board using the physical vapor deposition method having six conductive layers is completed through post-processing such as application and marking of the solder register 370 and physical outline processing.

A cross section of the multilayer printed circuit board completed through the above process is shown in FIG. 4A.

Now let's look at the structure of the vias. When the via is manufactured according to the present invention, it becomes possible to form a seed layer with a uniform thickness, so that a metal conductor layer of a uniform thickness is obtained, and a via having a uniform thickness as a whole is obtained.

In the present invention, a physical vapor deposition method is introduced into a build-up multilayer printed circuit board manufacturing process to introduce a process capable of producing a good quality vias. Physical vapor deposition was applied to the build-up multilayer printed circuit board manufacturing process to reduce the thickness of the metal conductor layer to enable the fabrication of fine circuit patterns. The electrical properties could be improved.

Meanwhile, a deformable example of the physical vapor deposition method is illustrated in FIG. 5. (C1) of FIG. 5 is a state after physical / chemical surface treatment is performed by the process (b5) of FIG. 3, and FIG. 5 (c2) is further screen-printed in the via hole of (c1). The state which filled the electrically conductive paste, hardened | cured on the conditions according to the specification of the used electrically conductive paste, and formed the filled via 510 is shown. The conductive paste refers to a material mixed with a conductive metal powder, a polymer and a dimer, and the like, for example, silver paste, gold paste, and kappa paste. It refers to a material that is widely used as a material for conductors in manufacturing printed circuit boards such as pastes. After the hardening process of the field via is completed through such a process, the surface modification treatment is performed to improve the physical vapor deposition characteristics by the process (b6) of FIG. 3 (the inside of the via hole is filled with a conductive paste. Surface modification treatment), and a build-up multilayer printed circuit board using physical vapor deposition is manufactured by the process of the above embodiment. A cross-sectional view of the build-up multilayer printed circuit board using the physical vapor deposition method manufactured by the deformable example is illustrated in FIG. 4B. Vias consisting of field vias may further increase connection reliability.

The present invention is not limited to the embodiments described above, and various modifications and changes can be made by those skilled in the art, which are included in the spirit and scope of the present invention as defined in the appended claims.

Therefore, according to the present invention, the physical vapor deposition method is used in place of the electroless plating, so that a seed layer having a uniform metal conductor layer thickness, excellent plating adhesion, and electrical properties can be formed, compared to the existing electroless plating layer. Genie enables the fabrication of build-up multilayer printed circuit boards using physical vapor deposition. In particular, when the photo-developable insulating resin layer and the physical vapor deposition method are applied at the same time, there is an advantage that the mass productivity of the build-up multilayer printed circuit board having a fine circuit pattern can be greatly improved. That is, all via holes can be processed by the exposure / development process of the photo-developed insulating resin, and since the metal conductor layer is thinner than the conventional method, it has many advantages even when manufacturing a fine circuit pattern.

Claims (20)

A photodevelopable insulating resin layer is formed on the upper and / or lower surface of the central substrate, and a predetermined via hole is formed in the insulating resin layer to form a metal conductor layer in the via hole and the surface of the insulating resin using physical vapor deposition. A method of manufacturing a build-up multilayer printed circuit board using physical vapor deposition. The method of claim 1, A method of manufacturing a build-up multilayer printed circuit board using a physical vapor deposition method, wherein the photoresist insulating resin in a film form is pressed on the upper and / or lower surfaces of a central substrate to form the insulating resin layer. The method of claim 1, A method of manufacturing a build-up multilayer printed circuit board using a physical vapor deposition method, wherein the insulating resin layer is formed by applying a liquid photo developing insulating resin to the upper surface and / or the lower surface of a central substrate one or more times. A first step of manufacturing a double-sided or multilayer printed circuit board as a central substrate; A second step of forming a photo developing insulating resin layer on an upper surface and / or a lower surface of the central substrate; A third step of forming a via hole in the photo developing insulating resin layer through an exposure / development process; A fourth step of performing physical / chemical surface treatment for removing residues remaining in the via hole and for surface treatment of the insulating resin layer; A fifth step of performing a surface modification treatment to improve physical vapor deposition characteristics using plasma in the physical and chemical surface treated via holes and the insulating resin layer; A sixth step of forming a metal conductor layer on the surface of the via-hole and the insulating resin layer by physical vapor deposition; Manufacture of a build-up multilayer printed circuit board using a physical vapor deposition method comprising a seventh step of forming a multi-layer printed circuit board having at least one conductor layer and an insulating layer by etching the metal conductor layer formed in the desired pattern form. Way. The method of claim 4, wherein Build-up multi-layer printing using physical vapor deposition method further comprises an eighth step of manufacturing the build-up multilayer printed circuit board of the desired number of layers by repeating the second to seventh step on the formed multilayer printed circuit board Circuit board manufacturing method. The method of claim 4, wherein the third step, An exposure step of irradiating light onto the photo-developed insulating resin layer through a film for manufacturing a pattern; And a developing step of forming a via hole by developing the photo-developed insulating resin layer irradiated with the light. 10. A method of manufacturing a build-up multilayer printed circuit board using physical vapor deposition. The method of claim 4, wherein the fourth step, And filling a conductive paste into the surface-treated via hole and curing the via-hole to form a filled via. 17. The method of claim 1, further comprising forming a filled via. The method of claim 4, wherein the sixth step, A method of manufacturing a build-up multilayer printed circuit board using a physical vapor deposition method comprising the step of tilting the surface-modified substrate at a predetermined angle to move along a predetermined trajectory to form a uniform metal conductor layer in a via hole. The method of claim 4 or 8, wherein the sixth step, Forming a deposition film having a predetermined thickness by using physical vapor deposition on the surface of the modified via hole and the surface of the insulating resin layer; And / or And forming a metal conductor layer having a predetermined thickness comprising the deposition film and the electroplating layer by performing electroplating using the formed deposition film as a seed layer. The method of claim 4 or 8, wherein the sixth step, A first deposition process of forming an inter metal layer made of less reactive metal using physical vapor deposition on the surface of the modified via hole and the surface of the insulating resin layer; A second deposition step of forming a deposited film by another metal having excellent conductivity on the intermediate metal layer using physical vapor deposition; And / or And forming a metal conductor layer having a predetermined thickness consisting of the deposition film and the electroplating layer by performing electroplating using the secondary deposited deposition film as a seed layer. Build-up multilayer printed circuit board using a physical vapor deposition method Manufacturing method. A thermosetting insulating resin layer is formed on the upper and / or lower surface of the central substrate, and a predetermined via hole is formed in the insulating resin layer to form a metal conductor layer on the inner surface of the via hole and the surface of the insulating resin by physical vapor deposition. A method for manufacturing a build-up multilayer printed circuit board using physical vapor deposition. The method of claim 11, A method of manufacturing a build-up multilayer printed circuit board using a physical vapor deposition method, wherein the thermally curable insulating resin in the form of a film is pressed to the upper and / or lower surfaces of the central substrate to form an insulating resin layer. The method of claim 11, A method for manufacturing a build-up multilayer printed circuit board using a physical vapor deposition method, wherein the liquid thermosetting insulating resin is applied to the upper and / or lower surfaces of the central substrate one or more times to form an insulating resin layer. A S1 process of manufacturing a double-sided or multilayer printed circuit board as a central substrate; Forming a thermal curable dielectric layer on an upper surface and / or a lower surface of the manufactured center substrate; S3 step of forming a via hole by laser processing the formed thermosetting insulating resin layer; Performing a physical / chemical surface treatment to remove residues remaining in the formed via hole and to surface-treat the insulating resin layer; S5 step of performing a surface modification treatment to improve the physical vapor deposition characteristics by using a plasma to the inside and the insulating resin layer of the physical / chemical surface treatment via hole; A sixth step of manufacturing a metal conductor layer having a predetermined thickness through physical vapor deposition on the inside of the surface modified via hole and the surface of the insulating resin layer; And forming a multilayer printed circuit board having at least one conductor layer and an insulating layer by etching the formed metal conductor layer in a desired pattern form. 7. A method of manufacturing a build-up multilayer printed circuit board using physical vapor deposition. . The method of claim 14, Build-up multi-layer printing using physical vapor deposition method further comprises the step S8 of manufacturing the build-up multilayer printed circuit board of the desired number of layers by repeating the step S2 to S7 process on the formed multilayer printed circuit board Circuit board manufacturing method. The method of claim 14, wherein the S3 step, A method of manufacturing a build-up multilayer printed circuit board using physical vapor deposition, characterized in that via holes are formed on the thermosetting insulating resin layer by laser drilling. The method of claim 14, wherein the S4 step, And filling a conductive paste into the surface-treated via hole and curing the via-hole to form a filled via. 17. The method of claim 1, further comprising forming a filled via. The method of claim 14, wherein the S6 step, And forming a uniform metal conductor layer in the via hole by tilting the surface-modified substrate at a predetermined angle and moving it along a predetermined trajectory. . 19. The method of claim 14 or 18, wherein the step S6, Forming a deposition film having a predetermined thickness by using physical vapor deposition on the surface of the modified via hole and the surface of the insulating resin layer; And / or And forming a metal conductor layer having a predetermined thickness consisting of the deposited film and the electroplating layer by performing electroplating using the formed deposition film as a seed layer. The method of claim 14 or 18, wherein the sixth step, A first deposition process of forming an inter metal layer made of less reactive metal using physical vapor deposition on the surface of the modified via hole and the surface of the insulating resin layer; A second deposition step of forming a deposited film by another metal having excellent conductivity on the intermediate metal layer using physical vapor deposition; And / or And forming a metal conductor layer having a predetermined thickness consisting of the deposition film and the electroplating layer by performing electroplating using the secondary deposited deposition film as a seed layer. Build-up multilayer printed circuit board using a physical vapor deposition method Manufacturing method.