TW201345353A - 晶片組裝結構及晶片組裝方法 - Google Patents
晶片組裝結構及晶片組裝方法 Download PDFInfo
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Abstract
一種晶片組裝結構,包括一個電路板、一個位於所述電路板上之晶片以及複數將所述晶片電連接至所述電路板上之焊線。所述電路板上形成有複數第一焊墊,所述晶片上形成複數分別對應於所述第一焊墊之第二焊墊。所述每一個焊墊上形成有一個第一焊球,所述每一個第二焊墊上形成有一個第二焊球。所述焊線分別自所述第一焊球牽拉至對應之第二焊球。所述焊線包括一個因牽拉形成之拱形部,所述拱形部靠近所述第一焊球。本發明還涉及一種晶片組裝方法。
Description
本發明涉及一種晶片組裝結構及晶片組裝方法。
為實現預定之功能,電子產品中一般包括電路板以及複數設置於所述電路板上之晶片,所述晶片可能具有不同之大小以及高度。所述晶片之間以及所述晶片與所述電路板藉由打線方式電連接。
先前技術中,通常將連接線與晶片或者電路板上之焊墊採用壓焊方式相連,然,隨著技術之發展,所述晶片尺寸變得越來越小,相應地,所述晶片之結構也越來越來脆弱,如果採用壓焊之方式與連接線相連,則所述晶片容易在壓力之下損壞,造成晶片組裝良率下降。
有鑒於此,有必要提供一種能夠保證晶片組裝良率之晶片組裝結構以及晶片組裝方法。
一種晶片組裝結構,包括一個電路板、一個位於所述電路板上之晶片以及複數將所述晶片電連接至所述電路板上之焊線。所述電路板上形成有複數第一焊墊,所述晶片上形成複數分別對應於所述第一焊墊之第二焊墊。所述每一個焊墊上形成有一個第一焊球,所述每一個第二焊墊上形成有一個第二焊球。所述焊線分別自所述第一焊球牽拉至對應之第二焊球。所述焊線包括一個因牽拉形成之拱形部,所述拱形部靠近所述第一焊球。
一種晶片組裝方法,包括如下步驟:
提供一個電路板,所述電路板上形成有複數第一焊墊;
提供一個晶片,所述晶片上形成有複數與所述第一焊墊相對應之第二焊墊;
將所述晶片固定設置於所述電路板表面;
於一個所述第二焊墊上形成一個第二焊球;
於對應形成所述第二焊球之第二焊墊之一個所述第一焊墊上形成一個第一焊球;
提供一個焊線,將所述焊線之一端與所述第一焊球相焊接;
將所述焊線由所述第一焊球牽拉至所述第二焊球,所述焊線之另一端焊接至所述第二焊球,所述焊線靠近所述第一焊球因牽拉形成一個拱形部。
相較先前技術,所述之晶片組裝結構以及晶片組裝方法,通過在所述晶片之第二焊墊以及所述電路板之第二焊墊上分別形成焊球,並將所述焊線首先與第一焊墊上之焊球相連,然後將所述焊線牽拉至所述第二焊球之焊球,能夠避免壓焊方式造成所述晶片損壞,提高了晶片組裝良率。另外,上述焊線之連接方式能夠使得因牽拉所形成之拱形部靠近所述第一焊球,相較先前技術,所述焊線之長度有所減少,因此有助於減小焊線之電感,提升所述晶片之性能,並且焊線之高度有所降低,因此可以使得所述晶片組裝結構更為緊湊。
下面將結合附圖對本發明作一具體介紹。
請參閱圖1,本發明之晶片組裝結構100包括一個電路板10、設置於所述電路板10上之晶片20以及連接所述電路板10以及所述晶片20之焊線30。
所述電路板10包括一個用於承載所述晶片20之承載面11。所述承載面11上設置有複數第一焊墊12,所述第一焊墊12與所述電路板10上之電路接線端(圖未示)相連,所述每一個第一焊墊12上形成有一個第一焊球13。
所述晶片20固定設置於所述電路板10之承載面11上。所述晶片20表面設置有複數第二焊墊21,所述第二焊墊21與所述電路板10上之第一焊墊12相對應。所述每一個第二焊墊21上形成有一個第二焊球22。
所述焊線30用於將所述第一焊墊12與對應之第二焊墊21電連接。所述焊線30包括一個與所述第一焊球13相連之起始端31、一個與所述第二焊球22相連之終止端32以及一個拱形部33。所述起始端31為所述焊線30在焊接時首先固定之一端,所述終止端32為所述焊線30在焊接時最後固定之一端。所述拱形部32為所述焊線30由所述第一焊球13向所述第二焊球22牽拉所形成之過渡部分,所述拱形部33靠近所述起始端31且所述拱形部33頂端大致與所述第二焊墊21上之第二焊球22平齊。
所述第一焊球13、所述第二焊球22以及所述焊線30由高導電率之金屬材料構成,本實施方式中,所述第一焊球13、所述第二焊球22以及所述焊線30均由金(Au)構成。
本實施方式中,所述電路板10上之所述晶片20之數量為一個。應當指出,所述晶片20之數量也可以為多個,且多個晶片20之厚度可以不同,所述晶片20之間也可以採用上述方式之焊線30相連,只要所述焊線30之起始端31位於較低之晶片20上,終止端32位於較高之晶片20上,並且所述拱形部33靠近所述起始端31。
請參閱圖2,本發明之晶片組裝方法包括如下步驟:
提供一個電路板,所述電路板上形成有複數第一焊墊;
提供一個晶片,所述晶片上形成有複數與所述第一焊墊相對應之第二焊墊;
將所述晶片固定設置於所述電路板表面;
於一個所述第二焊墊上形成一個第二焊球;
於對應形成所述第二焊球之第二焊墊之一個所述第一焊墊上形成一個第一焊球;
提供一個焊線,將所述焊線之一端與所述第一焊球相焊接;
將所述焊線由所述第一焊球牽拉至所述第二焊球,所述焊線之另一端焊接至所述第二焊球,所述焊線靠近所述第一焊球因牽拉形成一個拱形部。
以上所述僅詳細描述了所述晶片其中一個第二焊墊與所述電路板之對應第一焊墊之連接方法,可以理解,其他第二焊墊與對應之第一焊墊可以採用相同方法實現連接,此處不再一一贅述。
所述之晶片組裝結構以及晶片組裝方法,通過在所述晶片之第二焊墊以及所述電路板之第二焊墊上分別形成焊球,並將所述焊線首先與第一焊墊上之焊球相連,然後將所述焊線牽拉至所述第二焊球之焊球,能夠避免壓焊方式造成所述晶片損壞,提高了晶片組裝良率。另外,上述焊線之連接方式能夠使得因牽拉所形成之拱形部靠近所述第一焊球,相較先前技術,所述焊線之長度有所減少,因此有助於減小焊線之電感,提升所述晶片之性能,並且焊線之高度有所降低,因此可以使得所述晶片組裝結構更為緊湊。
綜上所述,本發明確已符合發明專利之要件,遂依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。
100...晶片組裝結構
10...電路板
11...承載面
12...第一焊墊
13...第一焊球
20...晶片
21...第二焊墊
22...第二焊球
30...焊線
31...起始端
32...終止端
33...拱形部
圖1係本發明之晶片組裝結構之示意圖。
圖2係本發明晶片組裝方法之流程圖。
100...晶片組裝結構
10...電路板
11...承載面
12...第一焊墊
13...第一焊球
20...晶片
21...第二焊墊
22...第二焊球
30...焊線
31...起始端
32...終止端
33...拱形部
Claims (10)
- 一種晶片組裝結構,包括一個電路板、一個位於所述電路板上之晶片以及複數將所述晶片電連接至所述電路板上之焊線,所述電路板上形成有複數第一焊墊,所述晶片上形成複數分別對應於所述第一焊墊之第二焊墊,其改進在於:所述每一個焊墊上形成有一個第一焊球,所述每一個第二焊墊上形成有一個第二焊球,所述焊線分別自所述第一焊球牽拉至對應之第二焊球,所述焊線包括一個因牽拉形成之拱形部,所述拱形部靠近所述第一焊球。
- 如申請專利範圍第1項所述之晶片組裝結構,其中,每一個所述焊線包括一個與所述第一焊球相連之起始端以及一個與所述第二焊球相連之終止端,所述拱形部位於所述起始端以及所述終止端之間且靠近所述起始端。
- 如申請專利範圍第1項所述之晶片組裝結構,其中,所述拱形部之頂端與所述第二焊墊上之第二焊球平齊。
- 如申請專利範圍第1項所述之晶片組裝結構,其中,所述第一焊球、所述第二焊球以及所述焊線由高導電率之金屬材料構成。
- 如申請專利範圍第4項所述之晶片組裝結構,其中,所述第一焊球、所述第二焊球以及所述焊線的材料為金。
- 一種晶片組裝方法,包括如下步驟:
提供一個電路板,所述電路板上形成有複數第一焊墊;
提供一個晶片,所述晶片上形成有複數與所述第一焊墊相對應之第二焊墊;
將所述晶片固定設置於所述電路板表面;
於一個所述第二焊墊上形成一個第二焊球;
於對應形成所述第二焊球之第二焊墊之一個所述第一焊墊上形成一個第一焊球;
提供一個焊線,將所述焊線之一端與所述第一焊球相焊接;
將所述焊線由所述第一焊球牽拉至所述第二焊球,所述焊線之另一端焊接至所述第二焊球,所述焊線靠近所述第一焊球因牽拉形成一個拱形部。 - 如申請專利範圍第6項所述之晶片組裝方法,其中,所述晶片藉由黏接或者焊接之方式固定於所述電路板表面。
- 如申請專利範圍第6項所述之晶片組裝方法,其中,所述拱形部之頂端與所述第二焊墊上之第二焊球平齊。
- 如申請專利範圍第6項所述之晶片組裝方法,其中,所述第一焊球、所述第二焊球以及所述焊線由高導電率之金屬材料構成。
- 如申請專利範圍第9項所述之晶片組裝方法,其中,所述第一焊球、所述第二焊球以及所述焊線的材料為金。
Priority Applications (2)
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TW101114040A TW201345353A (zh) | 2012-04-20 | 2012-04-20 | 晶片組裝結構及晶片組裝方法 |
US13/533,024 US20130277839A1 (en) | 2012-04-20 | 2012-06-26 | Chip package and method for assembling same |
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TW101114040A TW201345353A (zh) | 2012-04-20 | 2012-04-20 | 晶片組裝結構及晶片組裝方法 |
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JP3865055B2 (ja) * | 2001-12-28 | 2007-01-10 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7071421B2 (en) * | 2003-08-29 | 2006-07-04 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
JP2008034567A (ja) * | 2006-07-27 | 2008-02-14 | Fujitsu Ltd | 半導体装置及びその製造方法 |
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