TWI528516B - 晶片組裝結構及晶片組裝方法 - Google Patents
晶片組裝結構及晶片組裝方法 Download PDFInfo
- Publication number
- TWI528516B TWI528516B TW101114620A TW101114620A TWI528516B TW I528516 B TWI528516 B TW I528516B TW 101114620 A TW101114620 A TW 101114620A TW 101114620 A TW101114620 A TW 101114620A TW I528516 B TWI528516 B TW I528516B
- Authority
- TW
- Taiwan
- Prior art keywords
- bonding
- pad
- wafer
- pads
- circuit board
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 29
- 238000003466 welding Methods 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 43
- 238000005476 soldering Methods 0.000 description 10
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4941—Connecting portions the connecting portions being stacked
- H01L2224/49425—Wedge bonds
- H01L2224/49426—Wedge bonds on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85186—Translational movements connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85203—Thermocompression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Description
本發明涉及一種晶片組裝結構及晶片組裝方法。
為實現預定之功能,電子產品中一般包括電路板以及複數設置於所述電路板上之晶片,所述晶片之間以及所述晶片與所述電路板藉由打線方式電連接。
在有高頻訊號通過時,所述晶片與基板間的打線結構會產生較強電感,該電感會嚴重影響電路特性,使得電路阻抗難以匹配,同時使得訊號損失增加。
另外,隨著技術之發展,晶片之尺寸逾來逾小,相應地,晶片上之引腳尺寸也逾來逾小,引腳尺寸的減小必然造成打線難度增加。
有鑒於此,有必要提供一種能夠降低電感並且容易之晶片組裝結構以及晶片組裝方法。
一種晶片組裝結構,包括一個電路板以及一個位於所述電路板上之晶片。所述電路板上形成有複數第一焊墊,所述晶片上形成複數分別對應於所述第一焊墊之第二焊墊。所述每一個第一焊墊上形成有兩個第一焊球。每一個所述第二焊墊藉由兩條焊線與對應
之第一焊墊相連。所述兩條焊線之一端分別與所述兩個第一焊球相連,另一端與所述第二焊墊藉由熱壓焊方式相連。
一種晶片組裝方法,其包括如下步驟:提供一個電路板,所述電路板上形成有複數第一焊墊;提供一個晶片,所述晶片上形成有複數與所述第一焊墊相對應之第二焊墊;將所述晶片固定設置於所述電路板表面;於每一個所述第一焊墊上形成兩個第二焊球;提供兩個焊線,將所述兩個焊線之一端分別與所述第二焊球相焊接;將所述兩個焊線由所述第一焊球牽拉至所述第二焊墊,將所述焊線之另一端以熱壓焊方式焊接至所述第二焊墊上。
與先前技術相比,所述之晶片組裝結構以及晶片組裝方法,由於採用兩條焊線連接所述電路板上之第一焊墊以及所述晶片上對應之第二焊墊,並且所述兩條焊線之間構成並聯關係,因此可以使得所述第一焊墊以及第二焊墊之間連接線路電感降低,改善電路特性。另外,所述焊線藉由熱壓焊方式焊接至所述第二焊墊上,可以將低打線之難度,同時能夠增加增加所述第二焊墊與所述焊線連接部分的橫截面積,進一步降低電感。
100‧‧‧晶片組裝結構
10‧‧‧電路板
11‧‧‧承載面
12‧‧‧第一焊墊
13‧‧‧第一焊球
20‧‧‧晶片
21‧‧‧第二焊墊
30‧‧‧焊線
31‧‧‧起始端
32‧‧‧終止端
33‧‧‧楔形部
圖1係本發明之晶片組裝結構之示意圖。
圖2係本發明晶片組裝方法之流程圖。
下面將結合附圖對本發明作一具體介紹。
請參閱圖1,本發明之晶片組裝結構100包括一個電路板10、一個設置於所述電路板10上之晶片20以及連接所述電路板10以及所述晶片20之焊線30。
所述電路板10包括一個用於承載所述晶片20之承載面11。所述承載面11上設置有複數第一焊墊12,所述第一焊墊12與所述電路板10上之電路接線端(圖未示)相連,所述每一個第一焊墊12上形成有兩個第一焊球13。本事方式中,所述兩個第一焊球13與所述晶片20之間距離相同,當然,所述第一焊球13與所述晶片20之間距離也可以不同。
所述晶片20固定設置於所述電路板10之承載面11上。所述晶片20表面設置有複數第二焊墊21,所述第二焊墊21與所述電路板10上之第一焊墊12相對應。
本實施方式中,所述第一焊墊12及所述第二焊墊21之數量均為兩個,可以理解,所述第一焊墊12與所述第二焊墊21之數量可以依據不同需求而有所變化。
所述焊線30用於將所述第一焊墊12與對應之第二焊墊21電連接。每一對第一焊墊12與第二焊墊21之間由兩條焊線30相連。所述每一條焊線30包括一個與所述第一焊球13相連之起始端31、一個與所述第二焊墊21相連之終止端32。所述起始端31為所述焊線30在焊接時首先固定之一端,所述終止端32為所述焊線30在焊接時最後固定之一端。所述終止端32採用熱壓焊接方式與所述第二焊墊
21,所述每一個第二焊墊21上兩條焊線30的焊接位置相互重合。所述兩條焊線30於所述第二焊墊21焊接位置處形成一個楔形部33。
所述第一焊球13以及所述焊線30由高導電率之金屬材料構成,本實施方式中,所述第一焊球13以及所述焊線30均由金(Au)構成。
本實施方式中,所述電路板10上之所述晶片20之數量為一個。應當指出,所述晶片20之數量也可以為多個,且多個晶片20之厚度可以不同。
請參閱圖2,本發明之晶片組裝方法包括如下步驟:提供一個電路板,所述電路板上形成有複數第一焊墊;提供一個晶片,所述晶片上形成有複數與所述第一焊墊相對應之第二焊墊;將所述晶片固定設置於所述電路板表面;於一個所述第一焊墊上形成兩個第一焊球;提供兩個焊線,將所述兩個焊線之一端分別與所述第一焊球相焊接;將所述兩個焊線由所述第一焊球牽拉至所述第二焊墊,將所述焊線之另一端以熱壓焊方式焊接至所述第二焊墊上。
上述步驟中,所述焊線之另一端相互重疊焊接至所述第二焊墊上。
以上所述僅詳細描述了所述晶片其中一個第二焊墊與所述電路板之對應第一焊墊之連接方法,可以理解,其他第二焊墊與對應之第一焊墊可以採用相同方法實現連接,此處不再一一贅述。
所述之晶片組裝結構以及晶片組裝方法,由於採用兩條焊線連接所述電路板上之第一焊墊以及所述晶片上對應之第二焊墊,並且所述兩條焊線之間構成並聯關係,因此可以使得所述第一焊墊以及第二焊墊之間連接線路電感降低,改善電路特性。另外,所述焊線藉由熱壓焊方式焊接至所述第二焊墊上,可以將低打線之難度,同時能夠增加增加所述第二焊墊與所述焊線連接部分的橫截面積,進一步降低電感。
綜上所述,本發明確已符合發明專利之要件,遂依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式及所列之數據為作試驗及參考之所用,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。
100‧‧‧晶片組裝結構
10‧‧‧電路板
11‧‧‧承載面
12‧‧‧第一焊墊
13‧‧‧第一焊球
20‧‧‧晶片
21‧‧‧第二焊墊
30‧‧‧焊線
31‧‧‧起始端
32‧‧‧終止端
33‧‧‧楔形部
Claims (10)
- 一種晶片組裝結構,包括一個電路板和一個位於所述電路板上且與所述電路板電性相連之晶片,所述電路板上形成有複數第一焊墊,所述晶片上形成複數分別對應於所述第一焊墊之第二焊墊,其改進在於:所述每一個第一焊墊上形成有兩個第一焊球,每一個所述第二焊墊藉由兩條焊線與對應之第一焊墊相連,所述兩條焊線之一端分別與所述兩個第一焊球相連,另一端與所述第二焊墊藉由熱壓焊方式相連。
- 如申請專利範圍第1項所述之晶片組裝結構,其中,所述兩個第一焊球與所述晶片之間距離相同。
- 如申請專利範圍第1項所述之晶片組裝結構,其中,所述每一個第二焊墊上兩條焊線之焊接位置相互重合。
- 如申請專利範圍第1項所述之晶片組裝結構,其中,所述兩條焊線於所述第二焊墊焊接位置處形成一個楔形部。
- 如申請專利範圍第1項所述之晶片組裝結構,其中,所述第一焊球以及所述焊線之材料為金。
- 一種晶片組裝方法,包括如下步驟:提供一個電路板,所述電路板上形成有複數第一焊墊;提供一個晶片,所述晶片上形成有複數與所述第一焊墊相對應之第二焊墊;將所述晶片固定設置於所述電路板表面;於每一個所述第一焊墊上形成兩個第一焊球;提供兩個焊線,將所述兩個焊線之一端分別與所述第一焊球相焊接;將所述兩個焊線由所述第一焊球牽拉至所述第二焊墊,將所述焊線之另 一端以熱壓焊方式焊接至所述第二焊墊上。
- 如申請專利範圍第6項所述之晶片組裝方法,其中,所述第一焊墊上形成之兩個第一焊球與所述晶片之間間隔相同距離。
- 如申請專利範圍第6項所述之晶片組裝方法,其中,以熱壓焊將所述焊線之另一端焊接至所述第二焊墊上步驟中,所述第二焊墊上兩條焊線之焊接位置相互重合。
- 如申請專利範圍第6項所述之晶片組裝方法,其中,所述兩條焊線於所述第二焊墊焊接位置處形成一個楔形部。
- 如申請專利範圍第6項所述之晶片組裝方法,其中,所述第一焊球以及所述焊線之材料為金。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW101114620A TWI528516B (zh) | 2012-04-25 | 2012-04-25 | 晶片組裝結構及晶片組裝方法 |
US13/559,621 US8860219B2 (en) | 2012-04-25 | 2012-07-27 | Chip assembly and chip assembling method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW101114620A TWI528516B (zh) | 2012-04-25 | 2012-04-25 | 晶片組裝結構及晶片組裝方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201344864A TW201344864A (zh) | 2013-11-01 |
TWI528516B true TWI528516B (zh) | 2016-04-01 |
Family
ID=49476568
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101114620A TWI528516B (zh) | 2012-04-25 | 2012-04-25 | 晶片組裝結構及晶片組裝方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8860219B2 (zh) |
TW (1) | TWI528516B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101888401B1 (ko) * | 2012-05-09 | 2018-08-16 | 삼성전자주식회사 | 집적 회로를 위한 인덕터 |
TWI549577B (zh) * | 2012-11-22 | 2016-09-11 | 鴻海精密工業股份有限公司 | 光纖連接器電路基板及光纖連接器 |
US11908823B2 (en) * | 2021-01-11 | 2024-02-20 | Wolfspeed, Inc. | Devices incorporating stacked bonds and methods of forming the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6930381B1 (en) * | 2002-04-12 | 2005-08-16 | Apple Computer, Inc. | Wire bonding method and apparatus for integrated circuit |
US8063318B2 (en) * | 2007-09-25 | 2011-11-22 | Silverbrook Research Pty Ltd | Electronic component with wire bonds in low modulus fill encapsulant |
US20120228759A1 (en) * | 2011-03-07 | 2012-09-13 | Wen-Jeng Fan | Semiconductor package having interconnection of dual parallel wires |
-
2012
- 2012-04-25 TW TW101114620A patent/TWI528516B/zh active
- 2012-07-27 US US13/559,621 patent/US8860219B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW201344864A (zh) | 2013-11-01 |
US8860219B2 (en) | 2014-10-14 |
US20130285239A1 (en) | 2013-10-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8008785B2 (en) | Microelectronic assembly with joined bond elements having lowered inductance | |
JP3573133B2 (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
WO2007066564A1 (ja) | 部品実装用ピンを形成したプリント基板 | |
TWI424799B (zh) | 基板佈局與其形成方法 | |
TWI528516B (zh) | 晶片組裝結構及晶片組裝方法 | |
CN104966724A (zh) | 配置摄像头模组于终端主板的方法及终端设备 | |
JP2006134912A (ja) | 半導体モジュールおよびその製造方法、ならびにフィルムインターポーザ | |
TWI528510B (zh) | 晶片組裝結構及晶片組裝方法 | |
US20110147928A1 (en) | Microelectronic assembly with bond elements having lowered inductance | |
JP4083142B2 (ja) | 半導体装置 | |
KR100833187B1 (ko) | 반도체 패키지의 와이어 본딩방법 | |
TWI495052B (zh) | 基板結構與使用該基板結構之半導體封裝件 | |
TWI501370B (zh) | 半導體封裝件及其製法 | |
CN102412241B (zh) | 半导体芯片封装件及其制造方法 | |
CN103327737A (zh) | 芯片组装结构及芯片组装方法 | |
JP3163214U (ja) | 半導体装置 | |
JP2008147427A (ja) | 電子部品装置及び電子部品の実装方法 | |
TWI325622B (en) | Semiconductor package substrate | |
CN103378043A (zh) | 芯片组装结构及芯片组装方法 | |
CN101527292B (zh) | 芯片封装结构 | |
JP2009141229A (ja) | 半導体装置およびその製造方法 | |
JP4422636B2 (ja) | 非接触icカードモジュール及び非接触icカード | |
CN103378046A (zh) | 芯片组装结构及芯片组装方法 | |
TW201306403A (zh) | 連接器結構及其製作方法 | |
TW201345353A (zh) | 晶片組裝結構及晶片組裝方法 |