TW201342543A - 半導體裝置及其製作方法 - Google Patents

半導體裝置及其製作方法 Download PDF

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TW201342543A
TW201342543A TW102111095A TW102111095A TW201342543A TW 201342543 A TW201342543 A TW 201342543A TW 102111095 A TW102111095 A TW 102111095A TW 102111095 A TW102111095 A TW 102111095A TW 201342543 A TW201342543 A TW 201342543A
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Taiwan
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wafer
connector
contact pad
post
type
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TW102111095A
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TWI509752B (zh
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Chen-Hua Yu
Der-Chyang Yeh
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Taiwan Semiconductor Mfg
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Abstract

本發明揭示一種用以形成晶圓級封裝之裝置及其製作方法，包括藉由一模塑材料封裝由第一技術製成之一第一晶片及由不同於第一技術之一第二技術製成之一第二晶片，於模塑材料上形成一後鈍化內連線，其藉由一第一連接體連接至第一晶片之第一接觸墊，藉由一第二連接體連接至第二晶片之第二接觸墊，其中第一連接體及第二連接體可為一導電焊料球、一導電介層窗、一導電間柱、或其它種類之連接體。

Description

半導體裝置及其製作方法
本發明係有關於半導體封裝技術，且特別是有關於一種用於異質積體技術之晶圓級封裝技術。
半導體裝置可用於多種電子產品中，例如個人電腦、手機、數位相機、及其它電子設備中。半導體工業藉由降低最小特徵尺寸而持續提昇各種電子元件(例如，電晶體、二極體、電阻、電容等等)的積體密度，以允許在給定的區域中形成更多元件。在一些應用領域中，這些更小的電子元件亦需要使用比習知小的面積之更小的封裝。
一種已開發之用於半導體裝置的更小封裝為晶圓級封裝(wafer level package，WLP)。積體電路(integrated circuits，IC)之晶圓級封裝係由不同種類的技術所構成，其可視為一異質積體(heterogeneous integration)，並可降低製造成本、提供高效能及高密度。異質積體(亦稱為超積體)的初步應用已被用於微處理器、專用積體電路(application specific integrated circuits，ASIC)、及記憶體。異質積體的其他發展中用途尚包括射頻(radio frequency，RF)、類比、光學、及微機電系統(micro-electro-mechanical systems，MEMS)，其中由異質技術所製作之積體電路，例如數位互補式金屬氧化物半 導體、矽化鍺射頻雙極性金屬氧化物半導體、及任何現存或未來的技術，皆可使用晶圓級封裝。
用於異質積體技術之數種現存的晶圓級封裝技術是以垂直堆疊積體電路為基礎。這些技術可能需要較大的高度，故可能並不適用於某些情況。因此，有必要發展其他用於異質積體技術之晶圓級封裝技術。
本發明一實施例提供一種半導體裝置，包括：一第一晶片，由一第一技術製成且具有一第一接觸墊；一第二晶片，由不同於第一技術之一第二技術製成且具有一第二接觸墊；一模塑材料，用以封裝第一晶片及第二晶片；以及一後鈍化內連線，設置於模塑材料上，藉由一第一連接體連接至第一接觸墊，藉由一第二連接體連接至第二接觸墊，其中第一連接體為第一類型，第二連接體為不同於第一類型之第二類型，第一類型及第二類型選自由一導電焊料球、一導電介層窗、及一導電間柱所組成之族群。
本發明另一實施例提供一種半導體裝置的製作方法，包括：提供一第一晶片，第一晶片由一第一技術製成且具有一第一接觸墊；提供一第二晶片，第二晶片由不同於第一技術之一第二技術製成且具有一第二接觸墊；於第一接觸墊上形成一第一連接體且於第二接觸墊上形成一第二連接體，其中第一連接體為第一類型，第二連接體為不同於第一類型之第二類型，第一類型及第二類型選自由一導電焊料球、一導電介層窗、及一導電間柱所組成之族群；以一模塑材料封裝第一晶片 及第二晶片；以及於模塑材料上形成一後鈍化內連線，模塑材料連接至第一連接體及第二連接體。
本發明又一實施例提供一種半導體裝置，包括：一第一晶片，由一第一技術製成且具有一第一接觸墊，並具有一第一鈍化保護層設置於第一接觸墊上，第一鈍化保護層具有一開口以露出第一接觸墊；一第二晶片，由不同於第一技術之一第二技術製成且具有一第二接觸墊，並具有一第二鈍化保護層設置於第二接觸墊上，第二鈍化保護層具有一開口以露出第二接觸墊；一第一連接體，設置於第一接觸墊上，及一第二連接體，連接設置於第二接觸墊上，其中第一連接體為第一類型，第二連接體為不同於第一類型之第二類型，第一類型及第二類型選自由一導電焊料球、一導電介層窗、及一導電間柱所組成之族群；一模塑材料，將第一晶片及第二晶片封裝在一起，並露出第一連接體及第二連接體；一高分子層，設置於模塑材料上，其具有一第一開口以露出第一連接體，及一第二開口以露出第二連接體；以及一後鈍化內連線，設置於高分子層上，並連接至第一開口中的第一連接體及第二開口中的第二連接體。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
101‧‧‧互補式金屬氧化物半導體晶片
201‧‧‧砷化鎵晶片
301‧‧‧矽化鍺晶片
401‧‧‧積體被動裝置
102、202、302、402‧‧‧接觸墊
103、203、303、403‧‧‧鈍化保護層
104、204、304、404‧‧‧焊膏/焊膏小塊
105、205、305、405‧‧‧焊料/焊料球
500‧‧‧晶圓級封裝(半導體)裝置
501‧‧‧載板
502‧‧‧晶粒連接膜
503‧‧‧模塑材料
504‧‧‧高分子層
505‧‧‧後鈍化內連線
506‧‧‧第二高分子層
507‧‧‧凸塊底層金屬層
508‧‧‧焊料球
6042‧‧‧焊膏小塊
6051‧‧‧銅介層窗/連接體
6052‧‧‧焊料球/連接體
6053‧‧‧銅間柱/連接體
6054‧‧‧連接體
第1(a)~1(b)圖繪示了異質技術製成的積體電路之晶 圓級封裝的數實施例。
第2(a)~2(h)圖繪示了以異質技術製作積體電路之晶圓級封裝的方法之一實施例。
第3(a)~3(f)圖繪示了以異質技術製作積體電路之晶圓級封裝的方法之另一實施例。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
晶圓級封裝通常用於要求高速度、高密度、較高的端子數量之積體電路。一晶圓級封裝之半導體裝置包括將晶粒的主動區安裝至晶片承載基底或印刷電路板(printed circuit board，PCB)上。電性及物理內連接可藉由複數連接裝置(或簡稱連接體)達成，例如導電焊料凸塊或焊料球。焊料凸塊形成於設置於主動區上的凸塊襯墊、內連接點、或接觸墊上。連接體可為焊料凸塊、焊料球、銅間柱、銅介層窗、或其他相似連接裝置，以達成二物體之間的電性連接。任何前述連接裝置皆可視為一連接體。接觸墊係指內連接點、凸塊襯墊、或任意其它連接用之導電物。
本發明揭示一種形成晶圓級封裝之裝置及其製作方法，包括一第一晶片，由一第一技術製成，及一第二晶片，由一第二技術製成，此第一晶片及第二晶片被一模塑材料封裝在一起。一後鈍化內連線(post passivation interconnect，PPI) 可形成於模塑材料上，並藉由一第一連接體連接至第一接觸墊，藉由一第二連接體連接至第二接觸墊，其中第一連接體及第二連接體可為一銅焊料球、一銅介層窗、一銅間柱、或其他類型之連接體。
如第1(a)圖之剖面圖所示，由異質積體技術所製成的晶圓級封裝半導體裝置500，包括一互補式金屬氧化物半導體晶片101、一砷化鎵晶片201、一矽化鍺晶片301、及一積體被動裝置(integrated passive device，IPD)401。互補式金屬氧化物半導體晶片101可為一處理器晶片或一記憶體晶片。砷化鎵晶片201可為一功率放大器或一光電裝置，例如一影像感測器。矽化鍺晶片301可為一雙極性互補式金屬氧化物半導體導管式類比/數位轉換器(BiCMOS pipelined A/D converter)。積體被動裝置401可為一積體被動電路，其包括了電阻、電感、及電容。裝置500可為晶圓級封裝裝置中的智慧型無線終端積體處理器(intelligent wireless terminal integrating processors)、大容量記憶體(large memory)、影像感測器、或射頻/微波收發器。
使用異質技術之晶片數量僅用以說明，並非用以限定本發明。異質積體技術之晶圓級封裝裝置500可包括由第一技術製成之一第一晶片及由第二技術製成之一第二晶片，或其他任意組合。詞彙「技術」可指晶片電晶體的尺寸、用於製造晶片的晶圓的尺寸、電晶體的差異、或其他任何本領域之詞彙。因此一互補式金屬氧化物半導體晶片、一砷化鎵晶片、一矽化鍺晶片、及一積體被動裝置皆使用不同技術製成。
雖然並未繪示於第1(a)圖中，互補式金屬氧化物半導體晶片101可包括形成於一基板上之主動和被動裝置、導電層、及介電層，此基板可為矽塊材或絕緣層上矽基板。亦可使用其它半導體材料作為基板，包括III族、IV族、及V族元素半導體。砷化鎵晶片201可包括設置於半絕緣之砷化鎵基板上的n-p-n雙極性電晶體。矽化鍺晶片301可包括以鍺為基體之矽化鍺異質接面雙極性電晶體(heterojunction bipolar transistor，HBT)。矽化鍺雙極性互補式金氧半導體技術可為一適當技術，用以製作一射頻/類比/數位之無線移動通訊元件之系統。積體被動裝置401可為一積體被動電路，其包括了電阻、電感、及電容。
第1(a)圖繪示了晶片101上的接觸墊102、晶片201上的接觸墊202、晶片301上的接觸墊302、及晶片401上的接觸墊402，其皆連接至一個或多個焊料球/凸塊508。這些接觸墊102、202、302、及402彼此電性連接。晶片101、201、301、及401可包括數個接觸墊連接至數個焊料球/凸塊，其並未繪示於第1(a)圖中。一導電層作為接觸墊102形成於互補式金屬氧化物半導體晶片101之表面上，其他接觸墊202、302、及402亦以相似方式形成。接觸墊102、202、302、及402亦可稱為導電墊。接觸墊102、202、302、及402可使用鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或其它導電材料製成。接觸墊102、202、302、及402係使用電解電鍍法、物理氣相沉積法、濺射法、或無電解電鍍製程而沉積。接觸墊102、202、302、及402的尺寸、形狀、及位置僅用以說明，並非用 以限制本發明。通常，第一接觸墊可設置於以第一技術製成之第一晶片上，第二接觸墊可設置於以第二技術製成之第二晶片上。這些接觸墊可彼此電性連接。此數個接觸墊，其並未繪示於圖中，可為相同或不同尺寸。
一鈍化保護層103可形成於互補式金屬氧化物半導體晶片101之表面且於接觸墊102的頂部，以作為結構支持及物理隔離之用。鈍化保護層103可使用未摻雜之矽玻璃(un-doped silicate glass，USG)、氮化矽(SiN)、二氧化矽(SiO2)、氮氧化矽(SiON)、聚亞醯胺(polyimide，PI)、苯並環丁烯(benzocyclobutene，BCB)、聚苯並噁唑(polybenzoxazole，PBO)、或其它絕緣材料。可藉由使用罩幕定義之光阻蝕刻製程移除鈍化保護層103的一部分，而在鈍化保護層103形成一開口以露出接觸墊102。開口的大小、形狀、及位置僅用以說明，並非用以限制本發明。鈍化保護層203、303、及403亦分別以與鈍化保護層103之相似方式、相似材料形成於晶片201、301、及401上，以作為結構支持及物理隔離，並分別具有開口以露出接觸墊202、302、及402。通常，第一鈍化保護層可形成於以第一技術製成之第一晶片上的第一接觸墊上，第二鈍化保護層可形成於以第二技術製成之第二晶片上的第二接觸墊上。
一高度精確之製版機可用以沉積焊膏104的個別區塊於接觸墊102上。焊膏104沉積於接觸墊102上，並形成小的焊膏小塊104。相似的焊膏小塊204、304、及404亦可分別使用相同方式形成於接觸墊202、302、及402上。於接觸墊102上 形成焊膏小塊104(及於接觸墊上形成其它焊膏小塊204、304、及404)之後，可將裝置500移至回焊爐，並在爐中加熱以回流焊料(亦即，汽化焊料流體並由焊膏小塊形成焊料球)。回焊製程可在回流的焊料105冷卻及固化後，形成焊料球105及對應之接觸墊102之間的物理及電性連接。亦可為了晶片201、301、及401而形成相似的焊料球205、305、及405。
可使用一模塑製程所使用之模塑材料503將異質技術所製成之晶片101、201、301、及401水平封裝在一起。晶片101、201、301、401及其接觸墊102、202、302、402分別與其對應之鈍化保護層103、203、303、403一起連接至焊料球105、205、305、405，並被模塑製程所使用之模塑材料水平封裝在一起，例如一環氧樹脂模塑化合物(epoxy molding compound，EMC)。模塑製程可視為一封裝製程。模塑材料503封裝晶片101、201、301、及401為物理上的單一部件。模塑材料503與一層晶粒連接膜(die attach film，DAF)502接觸。一承載基底先前可設於晶粒連接膜502下方，以作為模塑製程時的支持，但第1(a)圖之結構中已被移除。
一高分子層504可形成於模塑材料503上。高分子層504可被圖案化而形成開口，以露出焊料球105、205、305、及405。高分子層504的圖案化可包括光微影技術。高分子層504可使用高分子材料形成，例如環氧樹脂、聚亞醯胺、苯並環丁烯、聚苯並噁唑等等，亦可使用其它相對較軟、通常為有機之介電材料。較佳的形成方法包括旋塗法或其他常用方法。高分子層504的厚度可介於約5微米至約30微米之間。本發明說明中 所記載之尺寸僅作為例示之用，隨著積體電路的微縮，此尺寸可下修。
一金屬材料被用以形成高分子層504上的後鈍化內連線505，並沿著高分子層504的輪廓而形成。後鈍化內連線505亦可填充於高分子層504的開口，並與焊料球105、205、305、及405接觸。因此後鈍化內連線505形成焊料球105、205、305、及405(其進一步分別連接至接觸墊102、202、302、及402)之間的電性連接。後鈍化內連線505的厚度小於約30微米，較佳為介於約2微米至約10微米之間。後鈍化內連線505可進一步包括在銅層的頂部的含鎳層(未繪示)，其形成方法包括電鍍法、無電鍍法、濺鍍法、化學氣相沉積法等等。
一第二高分子層506可形成於後鈍化內連線505上。第二高分子層506可被圖案化以形成開口，即焊料球508設置處。高分子層506的圖案化可包括光微影技術。高分子層506可使用高分子材料形成，例如環氧樹脂、聚亞醯胺、苯並環丁烯、聚苯並噁唑等等，亦可使用其它相對較軟、通常為有機之介電材料。較佳的形成方法包括旋塗法或其他常用的方法。
可於第二高分子層506的開口周圍形成一凸塊底層金屬層(under bump metal layer，UBM layer)507。凸塊底層金屬層507可使用銅或銅合金形成，其中可包括銀、鉻、鎳、錫、金、或前述之組合。額外膜層可形成於此銅層上，例如一鎳層、一無鉛預焊層、或前述之組合。凸塊底層金屬層507的厚度可介於約1微米至約20微米之間。
可於凸塊底層金屬層507上安裝焊料球508。如同 本領域所熟知，焊料球508可包括錫、鉛、銀、銅、鎳、鉍等等的合金。或者，可於凸塊底層金屬層507上藉由例如電鍍、印刷等方式形成一銅凸塊以取代一焊料球508。
焊料球508與第一晶片101之接觸墊102之間的連接，係透過凸塊底層金屬層507、後鈍化內連線505、焊料球105連接至第一晶片101之接觸墊102的頂部。焊料球508及接觸墊202、302、402之間的連接係以相似方式形成。異質技術所製成之晶片101、201、301、及401被封裝在一起，彼此電性連接並連接至焊料球508，並可進一步安裝至一印刷電路板上(未繪示於圖中)。
可將異質技術所製成之晶片101、201、301、及401封裝在一起，彼此電性連接並藉由不同方式連接至焊料球。第1(b)圖中的裝置600為另一實施例，其顯示了接觸墊102、202、302、及402與焊料球508之間的不同連接機制。除了連接機制的差異，第1(b)圖中的其他部分基本上與第1(a)圖相同。
如第1(b)圖所示，第一晶片101之第一接觸墊102與焊料球508的連接是透過接觸墊102、一銅介層窗6051至後鈍化內連線505，並進一步連接至凸塊底層金屬層507，即焊料球508設置處。銅介層窗6051為連接接觸墊102與後鈍化內連線505之連接體或連接裝置。後鈍化內連線505進一步接觸至凸塊底層金屬層507，即焊料球508設置處。
第二晶片201上之第二接觸墊202與焊料球508的連接是透過另一種方式。第二接觸墊202藉由使用回流製程在其上形成的焊料球6052連接至焊料小塊6042。焊料球6052進一 步連接至後鈍化內連線505，其連接至凸塊底層金屬層507，即焊料球508設置處。焊料球6052為連接接觸墊202與後鈍化內連線505的連接體或連接裝置。後鈍化內連線505進一步與凸塊底層金屬層507接觸，即焊料球508設置處。
第三晶片301上之第三接觸墊302與焊料球508的連接是透過第三種方式。一銅間柱6053連接第三晶片301上之第三接觸墊302與後鈍化內連線505，並可進一步連接至凸塊底層金屬層層507，即焊料球508設置處。銅間柱6053為連接接觸墊302與後鈍化內連線505的連接體或連接裝置。後鈍化內連線505可進一步與凸塊底層金屬層層507接觸，即焊料球508設置處。
第1(b)圖所繪示之實施例具有一第四接觸墊402，並以與第三接觸墊302連接至焊球508相似的方式藉由銅間柱6054連接至焊料球508。
在第1(b)圖中，銅介層窗6051、焊料球6052、及銅間柱6053係用以連接至後鈍化內連線505。通常，後鈍化內連線505可藉由第一連接體連接至第一晶片之第一接觸墊上，藉由第二連接體連接至第二晶片之第二接觸墊上，其中銅介層窗、銅間柱、及焊料球為連接體的例子。此連接體可為以任意導電材料製成之介層窗、間柱、焊料球、或凸塊。不同技術製成的不同晶片可具有不同的連接體。其可為本領域現在使用或未來開發之更多種其它連接體。連接體可為不同形狀，例如正方形、球形、菱形、或其它形狀。連接體可使用不同導電性材料製成，例如銅、錫、鉛、銀、銅、鎳、鉍等等的合金。
選擇使用銅介層窗、焊料球、或銅間柱作為連接裝置或連接體端視晶片輸入/輸出端子的數目而定。若晶片101的輸入/輸出端子數目大於約100，則可使用銅介層窗6051作為連接體以連接至接觸墊102。若晶片201的輸入/輸出端子數目介於約50至100的範圍之間，則可使用焊料球6052作為連接體以連接至接觸墊202。若晶片301的輸入/輸出端子數目小於約50，則可使用銅間柱6053作為連接體以連接至接觸墊302，如第1(b)圖所示。
連接體可具有不同尺寸或形狀。銅介層窗的高度可大於10微米，寬度可大於30微米。焊料球或銅焊料球的高度可大於30微米，寬度可大於70微米。銅間柱的高度可為10至20微米，寬度可為50微米。銅介層窗可為正方形，焊料球或銅焊料球可為圓形，銅間柱亦可為球形。可使用不同方式形成連接體，例如焊料球或銅焊料球的形成可藉由網版預焊後再回流而形成，其與銅介層窗與銅間柱為不同的製程。
第2(a)~2(h)圖繪示了使用晶圓級封裝製程以組裝如第1(a)圖所示之晶圓級封裝裝置500的方法之一實施例。
如第2(a)圖所示，提供四個晶片，包括一互補式金屬氧化物半導體晶片101、一砷化鎵晶片201、一矽化鍺晶片301、及一個積體被動裝置401。接觸墊102設置於晶片101上，接觸墊202設置於晶片201上，接觸墊302設置於晶片301上，接觸墊402設置於晶片401上。鈍化保護層103可形成於互補式金屬氧化物半導體晶片101的表面上且位於接觸墊102的 頂部，以作為結構支持及物理性隔離。可藉由使用罩幕定義之光阻蝕刻製程移除鈍化保護層103的一部分而在鈍化保護層103形成一開口，以露出接觸墊102。鈍化保護層203、303、403以相似方式分別形成於晶片201、301、401上以作為結構支持及物理性隔離，並具有開口以分別露出接觸墊202、302、402。
如第2(b)圖所示，四個晶片101、201、301、及401設置於具有晶粒連接膜502之載板501上。晶片101、201、301、及401被分隔設置於晶粒連接膜502的表面上。載板501係作為封裝製程的支撐載板，並在封裝物完成時移除。
如第2(c)圖所示，一高度精確之製版機可用以沉積焊膏104的個別區塊於接觸墊102上。焊膏104沉積於接觸墊102上，形成小的焊膏小塊104。亦可分別使用相同方式沈積相似的焊膏小塊204、304、及404於晶片201、301、及401上。
如第2(d)圖所示，於接觸墊102上形成焊膏小塊104(及於接觸墊上形成其它焊膏小塊204、304、及404)之後，可將裝置500移至回焊爐，並在爐中加熱以回流焊料(亦即，汽化焊料流體並由焊膏小塊形成焊料球)。回焊製程可在回流的焊料105冷卻及固化後，形成焊料球105及對應之接觸墊102之間的物理及電性連接。相似的焊料球205、305、及405可分別形成於晶片201、301、及401上。
如第2(e)圖所示，可使用一模塑製程所使用之模塑材料503將異質技術所製成之晶片101、201、301、及401水平封裝在一起。模塑製程可視為一封裝製程。模塑材料503將晶片101、201、301、及401一起封裝成物理上的單一部件。 模塑材料503填充於晶片之間的空間，並進一步覆蓋各個晶片周圍。
如第2(f)圖所示，覆蓋焊料球105、205、305、及405之模塑材料503藉由研磨而被薄化，以露出焊料球105、205、305、及405，其用以連接其它膜層，例如後鈍化內連線層。
如第2(g)圖所示，可於模塑材料503上形成一高分子層504。高分子層504可被圖案化而形成開口，以露出焊料球105、205、305、及405。高分子層504的圖案化可包括光微影技術。一金屬材料係用以在高分子層504上形成後鈍化內連線505，並沿著高分子層504的輪廓而形成。後鈍化內連線505亦可填充於高分子層504的開口，並與焊料球105、205、305、及405接觸。因此後鈍化內連線505形成焊料球105、205、305、及405(其進一步分別連接至接觸墊102、202、302、及402)之間的電性連接。亦可於後鈍化內連線505上形成一第二高分子層506。
如第2(h)圖所示，第二高分子層506可被圖案化以形成開口，即焊料球508設置處。第二高分子層506的開口並非位於第一高分子層504的正上方。可於第二高分子層506的開口周圍形成一凸塊底層金屬層507，且可設置數層凸塊底層金屬層507的子層。焊料球508可安裝於凸塊底層金屬層層507上，且位於第二高分子層506的各個開口中。載板501在將四個晶片101、201、301、及401被封裝及連接至焊球508後移除。
第3(a)~(f)圖繪示了使用晶圓級封裝製程以 組裝如第1(b)圖所示之晶圓級封裝裝置500的方法之一實施例。
如第3(a)圖所示，提供四個晶片，包括一互補式金屬氧化物半導體晶片101、一砷化鎵晶片201、一矽化鍺晶片301、及一個積體被動裝置401。一接觸墊102設置於晶片101上，一接觸墊202設置於晶片201上，一接觸墊302設置於晶片301上，一接觸墊402設置於晶片401上。鈍化保護層103可形成於互補式金屬氧化物半導體晶片101的表面上且位於接觸墊102的頂部，以作為結構支持及物理性隔離。可藉由使用罩幕定義之光阻蝕刻製程移除鈍化保護層103的一部分而在鈍化保護層103形成一開口，以露出接觸墊102。鈍化保護層203、303、403以相似方式形成於晶片201、301、401上，並作為結構支持及物理隔離，且具有開口以分別露出接觸墊202、302、402。
如第3(b)圖所示，四個晶片101、201、301、及401被設置於具有晶粒連接膜502之一載板501。晶片101、201、301、及401被分隔設置於晶粒連接膜502的表面上。載板501係作為封裝製程的支撐載板，且在封裝完成時移除。
如第3(c)圖所示，於晶片上形成不同連接體。銅介層窗6051為連接至接觸墊102的連接體或連接裝置，其可連接接觸墊102至隨後形成之後鈍化內連線。焊料球6052及銅間柱6053為形成於接觸墊302及402的另一種連接體，其可連接接觸墊302及402至隨後形成之後鈍化內連線。接觸墊202以一藉由回流製程形成於其上之焊料球6052連接至一焊膏小塊6042。連接體的例子可包括銅介層窗、銅間柱、及焊料球，亦 可為本領域現在使用或未來開發之更多種其它連接體。連接體可為不同形狀，例如正方形、球形、菱形、或其它形狀。連接體可使用不同導電性材料製成，例如銅、錫、鉛、銀、銅、鎳、鉍等等的合金。
如第3(d)圖所示，可使用一模塑製程所使用之模塑材料503將異質技術所製成之晶片101、201、301、及401水平封裝在一起。模塑製程可視為一封裝製程。模塑材料503將晶片101、201、301、及401一起封裝成物理上之單一部件。模塑材料503填充於晶片之間的空間，並進一步覆蓋各個晶片周圍。
如第3(e)圖所示，覆蓋連接體6051、6052、6053、及6054之模塑材料503藉由研磨而被薄化，以露出連接體6051、6052、6053、及6054，其用以連接其它膜層，例如後鈍化內連線層。
如第3(f)圖所示，可於模塑材料503上形成一高分子層504。高分子層504可被圖案化而形成開口，以露出連接體6051、6052、6053、及6054。一金屬材料係用以在高分子層504上形成後鈍化內連線505，並沿著高分子層504的輪廓而形成。後鈍化內連線505亦可填充於高分子層504的開口，並與連接體6051、6052、6053、及6054接觸。因此後鈍化內連線505形成6051、6052、6053、及6054(其進一步分別連接至接觸墊102、202、302、及402)之間的電性連接。
可於後鈍化內連線505上進一步形成一第二高分子層506。第二高分子層506可被圖案化以形成開口，即焊料球 508設置處。第二高分子層506的開口並非位於第一高分子層504的正上方。可於第二高分子層506的開口周圍形成一凸塊底層金屬層507，並可設置數層凸塊底層金屬層507的子層。焊料球508可安裝於凸塊底層金屬層層507上，且位於第二高分子層506的各個開口中。載板501將四個晶片101、201、301、及401被封裝及連接至焊球508後移除。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
101‧‧‧互補式金屬氧化物半導體晶片
201‧‧‧砷化鎵晶片
301‧‧‧矽化鍺晶片
401‧‧‧積體被動裝置
102、202、302、402‧‧‧接觸墊
103、203、303、403‧‧‧鈍化保護層
104、204、304、404‧‧‧焊膏/焊膏小塊
105、205、305、405‧‧‧焊料/焊料球
500‧‧‧晶圓級封裝(半導體)裝置
502‧‧‧晶粒連接膜
503‧‧‧模塑材料
504‧‧‧高分子層
505‧‧‧後鈍化內連線
506‧‧‧第二高分子層
507‧‧‧凸塊底層金屬層
508‧‧‧焊料球

Claims (10)

  1. 一種半導體裝置，包括：一第一晶片，由一第一技術製成且具有一第一接觸墊；一第二晶片，由不同於該第一技術之一第二技術製成且具有一第二接觸墊；一模塑材料，用以封裝該第一晶片及該第二晶片；以及一後鈍化內連線，設置於該模塑材料上，藉由一第一連接體連接至該第一接觸墊，藉由一第二連接體連接至該第二接觸墊，其中該第一連接體為第一類型，該第二連接體為不同於該第一類型之第二類型，該第一類型及該第二類型選自由一導電焊料球、一導電介層窗、及一導電間柱所組成之族群。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一技術是選自由一互補式金屬氧化物半導體晶片、一砷化鎵晶片、一矽化鍺晶片、及一積體被動裝置所組成之族群。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該第一晶片是選自由一互補式金屬氧化物半導體處理器晶片、一砷化鎵光電裝置、一矽化鍺雙極互補式金屬氧化物半導體類比/數位轉換器、及包括複數電阻、電導、電容之一積體被動裝置所組成之族群。
  4. 如申請專利範圍第1項所述之半導體裝置，其中連接該後鈍化內連線及該第一接觸墊之該第一連接體為一銅焊料球、一銅介層窗、或一銅間柱。
  5. 如申請專利範圍第1項所述之半導體裝置，更包括一凸塊底 層金屬層，該凸塊底層金屬層與該後鈍化內連線接觸且形成於該後鈍化內連線上之一高分子層的一開口上。
  6. 如申請專利範圍第1項所述之半導體裝置，更包括一高分子層，其介於該模塑材料及該後鈍化內連線之間。
  7. 一種半導體裝置的製作方法，包括：提供一第一晶片，該第一晶片由一第一技術製成且具有一第一接觸墊；提供一第二晶片，該第二晶片由不同於該第一技術之一第二技術製成且具有一第二接觸墊；於該第一接觸墊上形成一第一連接體且於該第二接觸墊上形成一第二連接體，其中該第一連接體為第一類型，該第二連接體為不同於該第一類型之第二類型，該第一類型及該第二類型選自由一導電焊料球、一導電介層窗、及一導電間柱所組成之族群；以一模塑材料封裝該第一晶片及該第二晶片；以及於該模塑材料上形成一後鈍化內連線，該模塑材料連接至該第一連接體及該第二連接體。
  8. 如申請專利範圍第7項所述之半導體裝置的製作方法，更包括：於該後鈍化內連線上形成一高分子層；圖案化該高分子層而形成一開口，以露出該後鈍化內連線；以及在與該後鈍化內連線接觸之該高分子層的該開口內形成一凸塊底層金屬層。
  9. 如申請專利範圍第7項所述之半導體裝置的製作方法，其中形成該第一連接體包括形成一銅焊料球、一銅介層窗、或一銅間柱。
  10. 一種半導體裝置，包括：一第一晶片，由一第一技術製成且具有一第一接觸墊，並具有一第一鈍化保護層設置於該第一接觸墊上，該第一鈍化保護層具有一開口以露出該第一接觸墊；一第二晶片，由不同於該第一技術之一第二技術製成且具有一第二接觸墊，並具有一第二鈍化保護層設置於該第二接觸墊上，該第二鈍化保護層具有一開口以露出該第二接觸墊；一第一連接體，設置於該第一接觸墊上，及一第二連接體，連接設置於該第二接觸墊上，其中該第一連接體為第一類型，該第二連接體為不同於該第一類型之第二類型，該第一類型及該第二類型選自由一導電焊料球、一導電介層窗、及一導電間柱所組成之族群；一模塑材料，將該第一晶片及該第二晶片封裝在一起，並露出該第一連接體及該第二連接體；一高分子層，設置於該模塑材料上，其具有一第一開口以露出該第一連接體，及一第二開口以露出該第二連接體；以及一後鈍化內連線，設置於該高分子層上，並連接至該第一開口中的第一連接體及該第二開口中的第二連接體。
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