CN107591391B - 组件封装及其制造方法 - Google Patents
组件封装及其制造方法 Download PDFInfo
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- CN107591391B CN107591391B CN201610833915.XA CN201610833915A CN107591391B CN 107591391 B CN107591391 B CN 107591391B CN 201610833915 A CN201610833915 A CN 201610833915A CN 107591391 B CN107591391 B CN 107591391B
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- die
- passivation layer
- component package
- layer
- reconfiguration
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Abstract
本发明实施例提供一种组件封装,组件封装包括逻辑晶粒以及逻辑晶粒上的第一钝化层。组件封装还包括存储器晶粒以及沿着所述逻辑晶粒与所述存储器晶粒的侧壁延伸的模制化合物。组件封装还包括延伸通过所述模制化合物的导通孔以及所述模制化合物上的第一重配置层结构。所述模制化合物延伸至所述存储器晶粒的顶面与所述第一重配置层结构的底面之间。所述第一钝化层的顶面与所述第一重配置层结构的底面接触。
Description
技术领域
本发明实施例涉及一种组件封装及其制造方法。
背景技术
在现有的封装技术中(例如扇出型封装),重配置层(redistribution layer,RDL)结构可形成在晶粒上并与晶粒中的有源组件(active devices)电连接。输入/输出(Input/output,I/O)接垫(例如球底金属层(under-bump metallurgy,UBM)上的焊球)可在后续形成并透过RDL结构电连接晶粒。此封装技术的优势特征在于形成扇出型封装体的可能性。因此,位在晶粒上的I/O接垫可被重配置至一大于所述晶粒的面积,藉此增加所述晶粒的表面上所封装的I/O接垫的数量。
整合扇出型(Integrated Fan Out,InFO)封装技术变得愈来愈受欢迎,特别是其可与晶圆级封装(Wafer Level Packaging,WLP)技术结合。如此一来,所得的封装结构可提供相对低成本的高功能性密度以及高性能的封装体。通常情况下,聚合物(例如聚酰亚胺、聚苯恶唑(polybenzoxazole,PBO)以及类似聚合物)可在InFO组件中形成RDL结构时用以当作钝化层、绝缘层以及/或保护层。
发明内容
本发明实施例提供一种组件封装包括逻辑晶粒、第一钝化层、存储器晶粒、模制化合物、导通孔以及第一重配置层结构。第一钝化层位在所述逻辑晶粒上。模制化合物沿着所述逻辑晶粒的侧壁与所述存储器晶粒的侧壁延伸。导通孔延伸通过所述模制化合物。第一重配置层结构位在所述模制化合物上。所述模制化合物沿着与所述存储器晶粒相交并与所述存储器晶粒的所述侧壁平行的线延伸在所述存储器晶粒的顶面与所述第一重配置层结构的底面之间。所述第一钝化层的顶面与所述第一重配置层结构的所述底面接触。
本发明实施例提供一种组件封装包括第一晶粒、第二晶粒、第一绝缘层、模制化合物以及介电层。第一晶粒包括第一接触窗。第二晶粒包括第二接触窗。第一绝缘层位于所述第一晶粒上,所述第一接触窗延伸通过所述第一绝缘层。模制化合物沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸,其中所述模制化合物的部分表面与所述第一绝缘层的最远离所述第一晶粒的表面齐平。介电层覆盖所述第一晶粒与所述第二晶粒,一或多个导电件在所述介电层中延伸,其中所述第一接触窗与所述第二接触窗分别电性连接至所述一或多个导电件,且其中所述模制化合物的所述部分表面接触所述介电层的部分表面,所述介电层的所述部分表面横向配置在所述第二晶粒的第一侧壁与所述第二晶粒的第二侧壁之间,所述第一侧壁相对于所述第二侧壁。
本发明实施例提供一种组件封装包括第一重配置结构、逻辑晶粒、存储器晶粒、钝化层、模制材料、第二重配置结构以及一或多个连接件。第一重配置结构包括一或多个第一介电层以及一或多个第一导电件延伸通过所述一或多个第一介电层。逻辑晶粒位于所述第一重配置结构上。存储器晶粒位于所述第一重配置结构上,所述存储器晶粒位于所述逻辑晶粒旁。钝化层位于所述逻辑晶粒上。模制材料沿着所述逻辑晶粒与所述存储器晶粒之间的最短线延伸在所述逻辑晶粒与所述存储器晶粒之间。第二重配置结构包括一或多个第二介电层以及一或多个第二导电件延伸通过所述一或多个第二介电层,所述钝化层接触所述第二重配置结构。一或多个连接件位于所述第二重配置结构上,所述模制材料延伸在所述存储器晶粒的最接近所述第二重配置结构的表面与所述一或多个连接件的最接近所述存储器晶粒的表面之间。
本发明实施例提供一种组件封装的制造方法,包括:提供逻辑晶粒与存储器晶粒;在所述逻辑晶粒上形成第一导电柱并在所述存储器晶粒上形成第二导电柱;在所述逻辑晶粒上形成第一钝化层;形成沿着所述逻辑晶粒的侧壁与所述存储器晶粒的侧壁延伸的模制化合物;薄化所述模制化合物,使得所述模制化合物的上表面与所述第一钝化层的上表面实质上共平面,其中在薄化后,所述模制化合物的一部分配置于所述存储器晶粒上;以及在所述模制化合物上形成重配置层结构,其中所述第一钝化层的所述上表面与所述重配置层结构的下表面接触。
本发明实施例提供一种组件封装的制造方法,包括:接收第一晶粒,第一钝化层与第一导电柱配置在所述第一晶粒上;接收第二晶粒,第二导电柱配置在所述第二晶粒上;形成第一重配置层结构;将所述第一晶粒与所述第二晶粒安置在所述第一重配置层结构上;形成模制化合物,其沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸;薄化所述模制化合物,以暴露所述第一钝化层、所述第一导电柱、所述第二导电柱以及多个导通孔;以及在所述模制化合物上形成第二重配置层结构,其中所述模制化合物延伸在所述第二重配置层结构的底面与所述第二晶粒的顶面之间,且其中所述第一钝化层与所述第二重配置层结构的所述底面接触。
本发明实施例提供一种组件封装的制造方法,包括:在逻辑晶粒上形成第一钝化层;在所述逻辑晶粒上的所述第一钝化层上沉积第二钝化层;在第一温度下固化所述第二钝化层;在所述逻辑晶粒上配置第一连接件,所述第一连接件延伸通过所述第一钝化层与所述第二钝化层;在存储器晶粒上形成第三钝化层;在所述存储器晶粒上配置第二连接件,所述第二连接件延伸通过所述第三钝化层;形成沿着所述逻辑晶粒的侧壁与所述存储器晶粒的侧壁延伸的模制材料,其中所述模制材料接触所述第三钝化层的顶面;以及在所述模制材料、所述逻辑晶粒以及所述存储器晶粒上形成第一重配置层,所述第一重配置层包括一或多个第一导电特征配置在第一介电层中,其中所述第一连接件与所述第二连接件分别电性连接至所述一或多个第一导电特征。
本发明实施例提供一种组件封装包括第一晶粒、第一钝化层、第二晶粒、多个重配置层、模制材料以及多个通孔。第一钝化层覆盖所述第一晶粒。第二晶粒邻近所述第一晶粒。多个重配置层覆盖所述第一晶粒与所述第二晶粒,其中所述多个重配置层中的每一个重配置层包括一或多个连接件延伸通过相应的介电层,其中所述多个重配置层中的第一重配置层最接近所述第一晶粒与所述第二晶粒,且其中所述第一钝化层接触所述第一重配置层的第一介电层。模制材料沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸,其中所述第二晶粒的第一表面最接近所述第一重配置层,其中所述第一重配置层的第一表面最接近所述第二晶粒,且其中所述模制材料延伸在所述第二晶粒的所述第一表面与所述第一重配置层的所述第一表面之间。多个通孔延伸通过所述模制材料。
本发明实施例提供一种组件封装包括第一晶粒、第二晶粒、模制材料、导通孔以及第一重配置结构。第一晶粒包括第一电性连接件。第二晶粒邻近所述第一晶粒,所述第二晶粒包括第二电性连接件。模制材料沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸,其中所述模制材料接触所述第一电性连接件的侧壁或所述第二电性连接件的侧壁。导通孔延伸通过所述模制材料。第一重配置结构位于所述第一晶粒与所述第二晶粒上,所述第一重配置结构电性耦接至所述导通孔、所述第一电性连接件以及所述第二电性连接件。
本发明实施例提供一种组件封装包括第一晶粒、第二晶粒、第三钝化层、模制材料以及重配置结构。第一晶粒配置在绝缘层上,所述第一晶粒包括第一接触窗延伸通过第一钝化层。第二晶粒配置在邻近所述第一晶粒的所述绝缘层上,所述第二晶粒包括第二接触窗延伸通过第二钝化层,其中所述第二钝化层的第一表面包括平坦区与斜角区,其中所述平坦区在第一方向上延伸,所述第一方向平行于所述第二晶粒的主要表面,且其中所述斜角区在第二方向上延伸,所述第二方向与所述第一方向不同。第三钝化层覆盖所述第一晶粒。模制材料延伸在所述第一晶粒与所述第二晶粒之间,其中所述模制材料接触所述斜角区与所述平坦区中的所述第二钝化层的所述第一表面。重配置结构覆盖所述第一晶粒与所述第二晶粒,其中所述第三钝化层接触所述重配置结构的介电层,且其中所述第二钝化层的所述第一表面面向所述重配置结构。
本发明实施例提供一种组件封装包括第一晶粒、第一钝化层、第二晶粒、第一绝缘层以及模制材料。第一钝化层覆盖所述第一晶粒。第二晶粒邻近所述第一晶粒。第一绝缘层覆盖所述第一晶粒与所述第二晶粒,其中所述第一钝化层与所述第一绝缘层物理接触。模制材料沿着所述第一晶粒的侧壁、所述第二晶粒的侧壁以及所述第一钝化层的侧壁延伸,其中所述模制材料延伸在所述第二晶粒与所述第一绝缘层之间。
本发明实施例提供一种组件封装包括第一晶粒、第二晶粒、模制材料以及第一绝缘层。第一晶粒包括第一电性连接件。第二晶粒邻近所述第一晶粒,所述第二晶粒包括二电性连接件。模制材料沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸,其中所述模制材料与所述第二电性连接件的侧壁物理接触,且其中所述第一电性连接件的侧壁与所述模制材料分隔。第一绝缘层位于所述第一晶粒与所述第二晶粒上,所述第一绝缘层与所述第一电性连接件、所述第二电性连接件以及所述模制材料物理接触。
本发明实施例提供一种组件封装包括第一晶粒、第二晶粒、第三钝化层、模制材料以及第一绝缘层。第一晶粒包括第一接触窗延伸通过第一钝化层。第二晶粒包括第二接触窗延伸通过第二钝化层。第三钝化层覆盖所述第一钝化层并环绕所述第一接触窗。模制材料延伸在所述第一晶粒与所述第二晶粒之间,其中所述模制材料与所述第一钝化层的侧壁、所述第二钝化层的侧壁以及所述第三钝化层的侧壁物理接触。第一绝缘层覆盖所述第一晶粒与所述第二晶粒,其中所述第三钝化层与所述第一绝缘层物理接触,且其中所述模制材料分隔所述第二钝化层与所述第一绝缘层。
附图说明
图1A、图1B、图2、图3A、图3B以及图4至图12示出为依照一些实施例的一种组件封装的制造步骤的剖面示意图。
具体实施方式
以下揭露内容提供用于实施所提供的目标之不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本揭露为目的。当然,这些仅仅为实例而非用以限制。举例来说,在以下描述中,在第二特征上方或在第二特征上形成第一特征可包括第一特征与第二特征形成为直接接触的实施例,且也可包括第一特征与第二特征之间可形成有额外特征,使得第一特征与第二特征可不直接接触的实施例。此外,本揭露在各种实例中可重复使用组件符号及/或字母。组件符号的重复使用是为了简单及清楚起见,且并不表示所欲讨论的各个实施例及/或配置本身之间的关系。
另外,为了易于描述附图中所示出的一个构件或特征与另一组件或特征的关系,本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及类似术语的空间相对术语。除了附图中所示出的定向之外,所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向),而本文所用的空间相对术语相应地作出解释。
在具体地叙述附图实施例之前,本发明实施例的某些优势特征以及方面将通常描述如下。一般而言,一种新的结构公开了以一种方式将逻辑晶粒与高带宽(bandwidth)的存储器晶粒一起封装在组件封装中,其改善了高带宽的存储器晶粒的可靠度并且增加了组件封装的良率。举例来说,多个晶粒被封装在单一个组件封装中。在一些实施例中,一个晶粒或更多个晶粒可包括所述晶粒的顶面上的钝化层。所述钝化层可在进行研磨工艺以平坦化所述晶粒的顶面时提供给晶粒一些优点。举例来说,所述钝化层可以是一“研磨停止”层,其用在所述晶粒与所述钝化层上所进行的研磨工艺。然而,用于某些钝化层(例如聚苯恶唑系材料)的某些材料可能需要在高温时进行固化。另一方面,某些高带宽的存储器晶粒(例如动态随机存取存储器(dynamic random access memory,DRAM)晶粒)可能对用于固化所述钝化层的高温敏感。假设将在高温时固化的钝化层安置在DRAM晶粒上并在后续进行固化,此将增加DRAM晶粒的故障可能性,且相对应地降低DRAM晶粒的可靠度并降低组件封装的良率。
另外,提供一种新的结构,其中逻辑晶粒与高带宽的存储器晶粒一起被封装在组件封装中。所述逻辑晶粒包括覆盖所述逻辑晶粒的钝化层,所述钝化层包括高温固化材料。所述高带宽的存储器晶粒不包括覆盖所述高带宽的存储器晶粒的钝化层,所述钝化层包括高温固化材料。在此所述的实施例可轻易地整合在封装工艺中,且与晶圆级封装技术兼容,并可增加所述高带宽的存储器晶粒以及所述组件封装(其包括所述高带宽的存储器晶粒)的可靠度以及良率。
图1A至图12示出为依照各种实施例的一种整合扇出型(InFO)封装的中间制造步骤。参照图1A,晶圆100A的一部分具有多个高带宽的存储器晶粒102A。高带宽的存储器晶粒102A可包括DRAM、混合存储器立方体(hybrid memory cube,HMC)、磁阻式随机存取存储器(Magnetoresistive random-access memory,MRAM)、快闪存储器(Flash)、纳米尺寸分子动力存储器(Nanoscale Molecular Dynamics,NAMD),上述组合或类似晶粒。在一些实施例中,功能性测试(例如电连接测试以及压力测试)可在晶圆100A上进行,且高带宽的存储器晶粒102A可通过此功能性测试。举例来说,高带宽的存储器晶粒102A可以是已知良好晶粒(known good dies,KGDs)。
各高带宽的存储器晶粒102A可以是半导体晶粒且可包括基板、有源组件以及内连线结构(未示出)。所述基板可以是块状硅基板(bulk silicon substrate),然而,其他半导体材料(包括III族元素、IV族元素以及V族元素)也可被使用。另外,所述基板可以是绝缘体上有硅(silicon-on-insulator)基板、绝缘体上有锗(germanium-on-insulator)基板或类似基板。有源组件(例如晶体管)可被形成在所述基板的顶面处。内连线结构可被形成在所述有源组件以及所述基板上。
所述内连线结构可包括层间介电(inter-layer dielectric,ILD)层以及/或金属间介电(inter-metal dielectric,IMD)层,其包含使用任何合适方法所形成的导电特征(例如包括铜、铝、钨、其组合或类似材料的导线以及导通孔)。所述ILD层以及IMD层可包括配置在此导电特征之间的低介电常数的介电材料(low-k dielectric materials),其具有例如低于约4.0或甚至低于2.8的k值。在一些实施例中,ILD层与IMD层可由例如磷硅玻璃(phosphosilicate glass,PSG)、硼磷硅玻璃(borophosphosilicate glass,BPSG)、氟硅酸盐玻璃(fluorosilicate glass,FSG)、SiOxCy、旋涂式玻璃(Spin-On-Glass)、旋涂式聚合物(Spin-On-Polymers)、硅碳材料(silicon carbon material)、其化合物、其组合物、其组合或类似材料。所述内连线结构可与各种有源组件电连接以在各高带宽的存储器晶粒102A内形成功能性电路。
输入/输出(I/O)与钝化特征可形成在所述内连线结构上。举例来说,接触垫104可形成在所述内连线结构上且可透过所述内连线结构中的各种导电特征与所述有源组件电连接。接触垫104可包括导电特征,例如铝、铜或类似材料。此外,钝化层106可形成在内连线结构与接触垫104上。钝化层106可当作界面、绝缘以及/或保护层,其用于后续工艺步骤中高带宽的存储器晶粒102A上的额外封装特征的形成。在一些实施例中,钝化层106可改善附着性、提供绝缘性以及/或防止在后续工艺步骤中下方的内连线结构的损伤。在一些实施例中,钝化层106可由非有机材料(例如氧化硅、未掺杂硅玻璃、氮氧化硅或类似材料)所形成。然而,其他合适的钝化材料也可被使用。部分钝化层106可覆盖所述接触垫104的边缘部分。
导电柱108可配置在接触垫104与钝化层106上。在一些实施例中,导电柱108包括铜,然而,其他合适的材料(例如金属以及/或金属合金)也可用于导电柱108。导电柱108可延伸通过钝化层106中的开口且电连接接触垫104。导电柱108可例如具有约5微米至约20微米的高度H1。导电柱108还可横向延伸至钝化层106的边缘并覆盖部分钝化层106。
在一些实施例中,在上视图中,导电柱108实质上为矩形。在一些实施例中,导电柱108可以是球形或多边形。导电柱108也可不横向延伸至钝化层106的边缘或未覆盖部分钝化层106。然而,导电柱108的其他配置也可被使用。举例来说,导电柱108可以是任何类型的合适的接触窗,例如接触垫、顶金属化层或类似接触窗。
高带宽的存储器晶粒102A的各种特征可透过任何合适的方法形成而不在此详细说明。此外,上述的高带宽的存储器晶粒102A的一般特征以及配置仅是一种例示实施例,且高带宽的存储器晶粒102A可包括任意数量的上述特征以及其他特征的任意组合。举例来说,各高带宽的存储器晶粒102A可包括多个接触垫104与多个导电柱108。
图1B示出为具有多个逻辑晶粒102B的晶圆100B的一部分。在一些实施例中,功能性测试(例如,电连接测试以及压力测试)可在晶圆100B上进行,且逻辑晶粒102B可通过此功能性测试。举例来说,逻辑晶粒102B可以是已知良好晶粒(KGDs)。上述讨论可与图1A连结,关于部分晶圆100A与高带宽的存储器晶粒102A可适用在如图1B所示的部分晶圆100B,为了简洁起见将不再赘述。图1A与图1B中的相似标号表示相似构件。
如图2所示,另一个钝化层110可形成在逻辑晶粒102B的顶面。钝化层110暴露出导电柱108的至少一部分。在附图实施例中,钝化层110为聚合物层,其可例如包括聚酰亚胺(PI)、聚苯恶唑(PBO)、苯并环丁烯(benzocyclobuten,BCB)、环氧树脂(epoxy)、硅氧树脂(silicone)、丙烯酸酯(acrylates)、纳米填充酚树脂(nano-filled pheno resin)、硅氧烷(siloxane)、含氟高分子(fluorinated polymer)、降冰片烯高分子(polynorbornene)或类似材料。另外,钝化层110可以是介电层,例如氮化硅、氧化硅、氮氧化硅或类似材料。钝化层110的材料与用于形成钝化层106的材料不同。钝化层110可当作界面、绝缘以及/或保护层,其用于后续工艺步骤中逻辑晶粒102B上的额外封装特征的形成。在一些实施例中,钝化层110可改善附着性、提供绝缘性以及/或防止后续工艺步骤中下方的钝化层106的损伤。在一些实施例中,钝化层110可当作“研磨停止”层,其可指出在钝化层110上的层所进行的研磨工艺的停止点。
钝化层110可以被沉积或以其他图案化方式被形成,以暴露出至少部分导电柱108。举例来说,钝化层110可使用旋转涂布工艺(spin-on coating process)来沉积。旋转涂布工艺的参数可被选择,使得钝化层110的沉积暴露出导电柱108。举例来说,旋转速度、所使用的钝化材料的量以及类似参数可被控制,使得沉积之后的钝化层110不会覆盖或延伸在导电柱108的顶面上方。另外,钝化层110可以一种方式被形成,其使得钝化层110的顶面高于导电柱108的顶面,并使用薄化工艺(例如研磨工艺)以薄化钝化层110进而暴露导电柱108。
在逻辑晶粒102B上形成钝化层110之后,钝化层110可经过固化工艺。举例来说,钝化层110可被加热至180℃至390℃之间的温度并持续30分钟至4小时。
如上述讨论,高带宽的存储器晶粒102A(如图1A所示)可能对用于固化钝化层110的高温敏感。在一些实施例中,所述高温可包括高于250℃的温度,其会增加一些高带宽的存储器晶粒102A的故障,然而,低于250℃的温度也可能会增加一些高带宽的存储器晶粒102A的故障率。高带宽的存储器晶粒102A上的钝化层,其也经过固化工艺且与钝化层110相似,可能导致一些高带宽的存储器晶粒102A的故障、降低所述高带宽的存储器晶粒102A的可靠度以及/或减少所形成的组件封装的良率。所述组件封装包括一个高带宽的存储器晶粒102A或更多个高带宽的存储器晶粒102A。因此,钝化层不会形成在高带宽的存储器晶粒102A上,此钝化层包括高温固化材料且类似逻辑晶粒102B上的钝化层110。
参照图3A,在一些实施例中,高带宽的存储器晶粒102A可被分离。举例来说,晶圆100A可被薄化至一所需的厚度,例如,透过在高带宽的存储器晶粒102A的背面上进行机械研磨工艺、化学机械研磨(chemical mechanical polish,CMP)工艺、蚀刻工艺或类似工艺。黏着层(未示出)(例如晶粒贴覆膜(die attach film,DAF)或类似膜)可被配置在晶圆100A的背面上。之后,可将高带宽的存储器晶粒102A单体化(singulated)。举例来说,晶粒切割可沿着配置在高带宽的存储器晶粒102A之间的切割道(scribe lines)进行,以将各高带宽的存储器晶粒102A与晶圆100A分离。
参照图3B,在一些实施例中,逻辑晶粒102B也可被分离。钝化层110形成之后,例如透过在逻辑晶粒102B的背面上进行机械研磨工艺、化学机械研磨(CMP)工艺、蚀刻工艺或类似工艺,晶圆100B可被薄化至一所需的厚度。黏着层(例如晶粒贴覆膜或类似膜)可被配置在晶圆100B的背面上。黏着层(未示出)可形成在相对于钝化层110的逻辑晶粒102B的一侧上。之后,可将逻辑晶粒102B单体化。举例来说,晶粒切割可沿着配置在逻辑晶粒102B之间的切割道进行,以将各逻辑晶粒102B与晶圆100B分离。
图4至图7示出为在安置高带宽的存储器晶粒102A与逻辑晶粒102B之前,形成组件封装200的各种特征的各种中间步骤。接着,在图8中,可将高带宽的存储器晶粒102A以及逻辑晶粒102B与组件封装200整合在一起。图4中,提供载体202。载体202可包括玻璃、陶瓷或其他合适的材料,且载体202在组件封装200的各种特征的形成期间可提供结构支撑。在载体202上配置临时黏着层204(例如胶层、光热转换(light-to-heat conversion,LTHC)涂布层、紫外线(UV)膜或类似膜)。
之后,在黏着层204与载体202上形成背侧RDL结构206。RDL结构206可包括形成在一层聚合物层210或更多层聚合物层210中的导电特征208(例如导线以及/或导通孔)。聚合物层210可使用任何合适的方法(例如旋转涂布技术、溅镀技术或类似技术)以及任何合适材料(例如PI、PBO、BCB、环氧树脂、硅氧树脂、丙烯酸酯、纳米填充酚树脂、硅氧烷、含氟高分子、降冰片烯高分子或类似材料)来形成。
导电特征208可形成在聚合物层210中。此导电特征208的形成可包括图案化聚合物层210(例如使用光刻工艺与蚀刻工艺的组合)并在经图案化的聚合物层210(例如透过沉积晶种层并使用掩膜层以定义导电特征208的形状)中形成导电特征208。导电特征208可被设计以形成功能性电路以及输入/输出特征,并用以后续附着晶粒(例如晶粒102A、102B)。
接着,如图5所示,在背侧RDL结构206与载体202上可形成图案化的光刻胶214。举例来说,在背侧RDL结构206上可沉积如毯覆层(blanket layer)的光刻胶214。之后,可使用光掩膜(未示出)暴露部分光刻胶214。依据使用负型光刻胶或正型光刻胶,使得被暴露或未被暴露的部分光刻胶214随后被移除。所得的图案化的光刻胶214可包括开口216,其可被沉积在载体202的周边区域。开口216还暴露背侧RDL结构206中的导电特征208。
图6示出将例如铜、银、金等的导电材料填入开口216以形成导通孔212。开口216的填入可包括先沉积晶种层(未示出)并以导电材料电镀开口216(例如电化学电镀法、无电电镀法或类似方法)。导电材料可溢出(overfill)开口216,并可进行CMP以移除光刻胶214上的过多的部分导电材料。
接着,如图7所示,移除光刻胶214。等离子灰化工艺或湿式剥除工艺可被使用以移除光刻胶214。在等离子灰化工艺之后,可选择性地在硫酸(H2SO4)溶液中进行湿式浸入,以清洁组件封装200并移除残留的光刻胶材料。
因此,导通孔212可形成在背侧RDL结构206上。另外,导通孔212也可被导电间柱(conductive studs)或导线(例如铜线、金线或银线)所取代。导通孔212可透过开口218彼此分离。相邻导通孔212之间的至少一开口218’可足够大以配置一个晶粒或更多个晶粒(例如晶粒102A与晶粒102B)在其中。
接着,如图8所示,一个高带宽的存储器晶粒102A或更多个高带宽的存储器晶粒102A以及一个逻辑晶粒102B或更多个逻辑晶粒102B(例如,如图1至图5中所形成)被安置在组件封装200上。如图所示,组件封装200可包括载体202以及一个内连线层或更多个内连线层(例如,具有导电特征208的背侧RDL结构206)。其他内连线结构(例如与背侧RDL结构206中的导电特征208电连接的导通孔212)也可被包括。黏着层(未示出)可被使用以将晶粒102A与晶粒102B附着在背侧RDL结构206上。在附图实施例中,一个高带宽的存储器晶粒102A与一个逻辑晶粒102B被安置在组件封装200上,然而,也可考虑安置超过两个晶粒。
图8示出为一种实施例的高带宽的存储器晶粒102A与逻辑晶粒102B被并排安置,且导通孔212被配置在组件封装200的外缘上。图8所示出的构件位置为一示例,也可考虑以其他方式放置高带宽的存储器晶粒102A、逻辑晶粒102B以及导通孔212。图8还示出为一种实施例的高带宽的存储器晶粒102A上的导电柱108的顶面与逻辑晶粒102B上的导电柱108的顶面实质上共平面。在一些实施例中,高带宽的存储器晶粒102A上的导电柱108的顶面与逻辑晶粒102B上的导电柱108的顶面也可不共平面。
接着参照图9,在高带宽的存储器晶粒102A与逻辑晶粒102B被安置在背侧RDL结构206的开口218’中之后,可将模制化合物220形成在组件封装200上。模制化合物220可被分散以填入高带宽的存储器晶粒102A、逻辑晶粒102B以及导通孔212之间的空隙中。模制化合物220延伸至逻辑晶粒102B上的钝化层110上。由于高带宽的存储器晶粒102A不包括钝化层110,因此模制材料可直接延伸至钝化层106上并沿着高带宽的存储器晶粒102A上的导电柱108的侧壁延伸。
模制化合物220可包括任何合适的材料,例如环氧树脂、模制底胶(moldingunderfill)或类似材料。形成模制化合物220的合适方法可包括压缩成型法(compressivemolding)、移转成型法(transfer molding)、液态包封成型法(liquid encapsulentmolding)或类似方法。举例来说,模制化合物220可以液态形式被分散在晶粒102A、晶粒102B以及导通孔212之间。之后,进行一固化工艺以固化模制化合物220。模制化合物220的填入可溢出高带宽的存储器晶粒102A、逻辑晶粒102B以及导通孔212,使得模制化合物220覆盖高带宽的存储器晶粒102A、逻辑晶粒102B以及导通孔212的顶面。
在图10所示出的工艺步骤中,模制化合物220可被平坦化(例如使用CMP、研磨法或类似方法)以减少整体厚度,并藉此暴露导通孔212与导电柱108。在一些实施例中,研磨工艺可终止在钝化层110的侦测上。因此,钝化层110可当作“研磨停止”层。由于所得结构包括延伸通过模制化合物220的导通孔212,导通孔212可被视为模制导通孔(through moldingvias)、间导通孔(through intervias,TIVs)或类似结构。导通孔212提供电连接组件封装200中的背侧RDL结构206中的导电特征208。
如图10所示出的实施例中,逻辑晶粒102B上的导电柱108的顶面可与钝化层110的顶面实质上共平面。另外,钝化层110的顶面与模制化合物220的顶面实质上共平面。高带宽的存储器晶粒102A上的导电柱108的顶面也可与模制化合物220的顶面实质上共平面,而模制化合物220延伸至高带宽的存储器晶粒102A上的钝化层106上。
图11与图12示出为形成RDL结构226(如图12所示)的制造步骤,所述RDL结构226具有与导电柱108电连接的导电特征224(例如导通孔以及/或接触窗)。图11示出为具有开口225的图案化的聚合物层222的形成。聚合物层222可包括PI、PBO、BCB、环氧树脂、硅氧树脂、丙烯酸酯、纳米填充酚树脂、硅氧烷、含氟高分子、降冰片烯高分子或类似材料。在一些实施例中,聚合物层222可包括与钝化层110相同的材料,但其他合适材料也可适用于聚合物层222。
聚合物层222可使用毯覆式沉积工艺(例如旋转涂布法、溅镀法或类似方法)形成在模制化合物220与导电柱108上。沉积之后,可使用例如光刻工艺以及/或蚀刻工艺图案化聚合物层222以形成开口225。开口225可暴露导电柱108与导通孔212。
然后,可将导电材料填入开口225中。举例来说,可在开口225中形成晶种层(未示出),并使用电化学电镀工艺、无电电镀工艺或类似工艺将导电材料电镀至开口225中。聚合物层222中的所得导通孔(如图12所示)可电连接导电柱108以及/或导通孔212。
具有导电特征的额外聚合物层也可形成在聚合物层222上。举例来说,图12示出了具有导电特征224在其中的RDL结构226。RDL结构226在组成以及形成过程中皆可与背侧RDL结构206实质上相似。举例来说,RDL结构226可包括配置在各种聚合物层之间的导电特征224(例如导线与导通孔)。导电特征224透过导电柱108与高带宽的存储器晶粒102A以及逻辑晶粒102B电连接。为了简洁起见,RDL结构226的额外的详细说明于此便不再赘述。
如图12所示,在一些实施例中,模制材料220可延伸至RDL结构226的底面242与高带宽的存储器晶粒102A的顶面240之间。在一些实施例中,钝化层110的顶面244可与RDL结构226的底面242接触,使得模制化合物220不配置在钝化层110的顶面244与RDL结构226的底面242之间。
额外的封装特征(例如外部连接件(external connectors)228以及其他表面安装组件(surface mount devices,SMDs)230)可被配置在RDL结构226上。连接件228可以是球栅数组(ball grid array,BGA)的焊球、可控塌陷芯片连接(controlled collapse chipconnector,C4)凸块或类似物,其配置在RDL结构226上的球底金属层(under metalmetallurgies,UBMs)232上。连接件228与表面安装组件230可透过通过RDL结构226的方式与一个晶粒102A、102B或更多个晶粒102A、102B电连接。连接件228可用以将组件封装200电连接其他封装构件,例如另一个组件晶粒、中介片(interposers)、封装基板、印刷电路板、主机板(mother board)或类似构件。
图12还示出了可透过移除临时黏着层204,将组件封装200与载体202分离。黏着层204的移除工艺可包括对LTHC层加热、对UV胶带照射UV光或类似工艺。载体202的移除可暴露组件封装200中的额外输入/输出接触。举例来说,背侧RDL结构206中的导电特征(接触垫208’)也可用于将组件封装200电连接其他封装构件,例如存储器晶粒或任何其他封装构件。
此外,一种新的结构提供了以一种方式将逻辑晶粒与高带宽的存储器晶粒一起封装在组件封装中,其可提升高带宽的存储器晶粒的可靠度以及组件封装的良率。如上述详细说明,高带宽的存储器晶粒与逻辑晶粒一起被封装在组件封装中。钝化层形成在逻辑晶粒上。所述钝化层可保护逻辑晶粒,且其可在对所述钝化层上的模制材料进行的研磨工艺中作为“研磨停止”层。所述钝化层可包括高温固化材料,例如聚苯恶唑(PBO)系材料。组件封装中的高带宽的存储器晶粒可能对于固化所述钝化层所需的高温敏感。举例来说,假设将在高温时固化的钝化层安置在DRAM晶粒上并于后续进行固化,此将增加DRAM晶粒的故障可能性,且相对应地降低DRAM晶粒的可靠度。因此,所述高带宽的存储器晶粒不包括高带宽的存储器晶粒上的高温固化的钝化层。而模制化合物直接形成在所述高带宽的存储器晶粒上。另外,提供一种新的结构,其逻辑晶粒与高带宽的存储器晶粒一起被封装在组件封装中,所述新的结构可增加所述组件封装的可靠度并增加所述组件封装的良率。
根据一实施例,组件封装包括逻辑晶粒。第一钝化层位在所述逻辑晶粒上。所述组件封装还包括存储器晶粒。模制化合物沿着所述逻辑晶粒与所述存储器晶粒的侧壁延伸。导通孔延伸通过所述模制化合物。第一重配置层(RDL)结构位在所述模制化合物上。所述模制化合物延伸至所述存储器晶粒的顶面与所述第一重配置层结构的底面之间。所述第一钝化层的顶面与所述第一重配置层结构的所述底面接触。
根据另一实施例,组件封装的形成方法包括提供逻辑晶粒与存储器晶粒。所述方法还包括在所述逻辑晶粒上形成第一导电柱并在所述存储器晶粒上形成第二导电柱。所述方法还包括在所述逻辑晶粒上形成第一钝化层。所述方法还包括形成模制化合物,其沿着所述逻辑晶粒与所述存储器晶粒的侧壁延伸。所述方法还包括薄化所述模制化合物,使得所述模制化合物的上表面与所述第一钝化层的上表面实质上共平面。在薄化后,所述模制化合物的一部分配置在所述存储器晶粒上。所述方法还包括在所述模制化合物上形成重配置层(RDL)结构。所述第一钝化层的所述上表面与所述模制化合物的下表面接触。
根据又一实施例,组件封装的形成方法包括接收第一晶粒,第一钝化层与第一导电柱配置在所述第一晶粒上。所述方法还包括接收第二晶粒,第二导电柱配置在所述第二晶粒上。所述方法还包括形成第一重配置层(RDL)结构。将所述第一晶粒与所述第二晶粒安置在所述第一重配置层结构上。所述方法还包括形成模制化合物,其沿着所述第一晶粒与所述第二晶粒的侧壁延伸。所述方法还包括薄化所述模制化合物以暴露所述第一钝化层、所述第一导电柱、所述第二导电柱以及多个导通孔。所述方法还包括在所述模制化合物上形成第二重配置层结构。所述模制化合物延伸至所述第二重配置层结构的底面与所述第二晶粒的顶面之间。第一钝化层与所述第二重配置层结构的底面接触。
以上概述了数个实施例的特征,使本领域技术人员可更佳了解本揭露的态样。本领域技术人员应理解,其可轻易地使用本揭露作为设计或修改其他工艺与结构的依据,以实行本文所介绍的实施例的相同目的及/或达到相同优点。本领域技术人员还应理解,这种等效的配置并不悖离本揭露的精神与范畴,且本领域技术人员在不悖离本揭露的精神与范畴的情况下可对本文做出各种改变、置换以及变更。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作些许的改动与润饰,均在本发明范围内。
Claims (80)
1.一种组件封装,包括:
逻辑晶粒,第一钝化层位在所述逻辑晶粒上;
存储器晶粒;
模制化合物,沿着所述逻辑晶粒的侧壁与所述存储器晶粒的侧壁延伸;
导通孔,延伸通过所述模制化合物;以及
第一重配置层结构,位在所述模制化合物上,其中所述模制化合物沿着与所述存储器晶粒相交并与所述存储器晶粒的所述侧壁平行的线延伸在所述存储器晶粒的顶面与所述第一重配置层结构的底面之间,且其中所述第一钝化层的顶面与所述第一重配置层结构的所述底面接触。
2.根据权利要求1所述组件封装,其中所述存储器晶粒为动态随机存取存储器晶粒。
3.根据权利要求1所述组件封装,其中所述第一钝化层包括聚苯恶唑。
4.根据权利要求1所述组件封装,其中第二钝化层沿着所述存储器晶粒的表面配置,所述第二钝化层的表面接触所述模制化合物。
5.根据权利要求4所述组件封装,其中所述第一钝化层包括第一材料,所述第二钝化层包括第二材料,且其中所述第一材料与所述第二材料不同。
6.根据权利要求1所述组件封装,其中表面安装组件配置在所述第一重配置层结构上。
7.根据权利要求1所述组件封装,其中导电柱配置在所述存储器晶粒上,其中所述导电柱的顶面接触所述第一重配置层结构的所述底面,且其中所述模制化合物沿着所述导电柱的侧壁延伸。
8.根据权利要求1所述组件封装,还包括第二重配置层结构覆盖所述模制化合物,其中所述导通孔从所述第一重配置层结构延伸至所述第二重配置层结构。
9.一种组件封装,包括:
第一晶粒,包括第一接触窗;
第二晶粒,包括第二接触窗;
第一绝缘层,位于所述第一晶粒上,所述第一接触窗延伸通过所述第一绝缘层;
模制化合物,沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸,其中所述模制化合物的部分表面与所述第一绝缘层的最远离所述第一晶粒的表面齐平;以及
介电层,覆盖所述第一晶粒与所述第二晶粒,一或多个导电件在所述介电层中延伸,其中所述第一接触窗与所述第二接触窗分别电性连接至所述一或多个导电件,且其中所述模制化合物的所述部分表面接触所述介电层的部分表面,所述介电层的所述部分表面横向配置在所述第二晶粒的第一侧壁与所述第二晶粒的第二侧壁之间,所述第一侧壁相对于所述第二侧壁。
10.根据权利要求9所述组件封装,其中所述第一绝缘层接触所述介电层的所述表面。
11.根据权利要求10所述组件封装,其中所述模制化合物接触所述第一绝缘层的侧壁。
12.根据权利要求9所述组件封装,其中所述第一绝缘层覆盖第二绝缘层,所述第二绝缘层沿着所述第一晶粒的表面延伸。
13.根据权利要求9所述组件封装,其中所述模制化合物沿着所述第二接触窗的侧壁延伸。
14.根据权利要求9所述组件封装,其中多个通孔延伸通过所述模制化合物。
15.根据权利要求9所述组件封装,其中所述第一晶粒为逻辑晶粒,而所述第二晶粒为存储器晶粒。
16.一种组件封装,包括:
第一重配置结构,包括一或多个第一介电层以及一或多个第一导电件延伸通过所述一或多个第一介电层;
逻辑晶粒,位于所述第一重配置结构上;
存储器晶粒,位于所述第一重配置结构上,所述存储器晶粒位于所述逻辑晶粒旁;
钝化层,位于所述逻辑晶粒上;
模制材料,沿着所述逻辑晶粒与所述存储器晶粒之间的最短线延伸在所述逻辑晶粒与所述存储器晶粒之间;
第二重配置结构,包括一或多个第二介电层以及一或多个第二导电件延伸通过所述一或多个第二介电层,所述钝化层接触所述第二重配置结构;以及
一或多个连接件,位于所述第二重配置结构上,所述模制材料延伸在所述存储器晶粒的最接近所述第二重配置结构的表面与所述一或多个连接件的最接近所述存储器晶粒的表面之间。
17.根据权利要求16所述组件封装,其中通孔电性连接所述一或多个第一导电件至所述一或多个第二导电件。
18.根据权利要求16所述组件封装,其中第一接触窗延伸通过所述逻辑晶粒与所述第二重配置结构之间的所述钝化层。
19.根据权利要求16所述组件封装,其中第二接触窗延伸通过所述存储器晶粒与所述第二重配置结构之间的所述模制材料。
20.根据权利要求16所述组件封装,还包括表面安装组件连接至所述第二重配置结构。
21.一种组件封装的制造方法,包括:
提供逻辑晶粒与存储器晶粒;
在所述逻辑晶粒上形成第一导电柱并在所述存储器晶粒上形成第二导电柱;
在所述逻辑晶粒上形成第一钝化层;
形成沿着所述逻辑晶粒的侧壁与所述存储器晶粒的侧壁延伸的模制化合物;
薄化所述模制化合物,使得所述模制化合物的上表面与所述第一钝化层的上表面实质上共平面,其中在薄化后,所述模制化合物的一部分配置于所述存储器晶粒上;以及
在所述模制化合物上形成重配置层结构,其中所述第一钝化层的所述上表面与所述重配置层结构的下表面接触。
22.根据权利要求21所述组件封装的制造方法,其中形成所述第一钝化层包括在第一温度下固化所述第一钝化层。
23.根据权利要求22所述组件封装的制造方法,其中所述第一温度介于180°C至230°C之间。
24.根据权利要求21所述组件封装的制造方法,其中所述存储器晶粒不经过固化工艺。
25.根据权利要求21所述组件封装的制造方法,其中所述第一钝化层包括聚苯恶唑,而所述存储器晶粒为动态随机存取存储器晶粒。
26.根据权利要求21所述组件封装的制造方法,其中薄化所述模制化合物包括对所述模制化合物的所述上表面进行研磨工艺,所述研磨工艺在侦测到所述第一钝化层时终止。
27.根据权利要求21所述组件封装的制造方法,还包括在所述存储器晶粒上形成第二钝化层,其中所述第一钝化层与所述第二钝化层包括不同材料。
28.一种组件封装的制造方法,包括:
接收第一晶粒,第一钝化层与第一导电柱配置在所述第一晶粒上;
接收第二晶粒,第二导电柱配置在所述第二晶粒上;
形成第一重配置层结构;
将所述第一晶粒与所述第二晶粒安置在所述第一重配置层结构上;
形成模制化合物,其沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸;
薄化所述模制化合物,以暴露所述第一钝化层、所述第一导电柱、所述第二导电柱以及多个导通孔;以及
在所述模制化合物上形成第二重配置层结构,其中所述模制化合物延伸在所述第二重配置层结构的底面与所述第二晶粒的顶面之间,且其中所述第一钝化层与所述第二重配置层结构的所述底面接触。
29.根据权利要求28所述组件封装的制造方法,其中所述第一导电柱与所述第二导电柱接触所述第二重配置层结构。
30.根据权利要求28所述组件封装的制造方法,其中形成所述第一钝化层包括在第一温度下固化所述第一钝化层。
31.根据权利要求28所述组件封装的制造方法,其中所述第一钝化层包括聚苯恶唑,而所述第二晶粒为动态随机存取存储器晶粒。
32.根据权利要求28所述组件封装的制造方法,还包括在所述第二晶粒上不形成需要固化工艺的钝化层。
33.一种组件封装的制造方法,包括:
在逻辑晶粒上形成第一钝化层;
在所述逻辑晶粒上的所述第一钝化层上沉积第二钝化层;
在第一温度下固化所述第二钝化层;
在所述逻辑晶粒上配置第一连接件,所述第一连接件延伸通过所述第一钝化层与所述第二钝化层;
在存储器晶粒上形成第三钝化层;
在所述存储器晶粒上配置第二连接件,所述第二连接件延伸通过所述第三钝化层;
形成沿着所述逻辑晶粒的侧壁与所述存储器晶粒的侧壁延伸的模制材料,其中所述模制材料接触所述第三钝化层的顶面;以及
在所述模制材料、所述逻辑晶粒以及所述存储器晶粒上形成第一重配置层,所述第一重配置层包括一或多个第一导电特征配置在第一介电层中,其中所述第一连接件与所述第二连接件分别电性连接至所述一或多个第一导电特征。
34.根据权利要求33所述组件封装的制造方法,其中所述第二钝化层的顶面接触所述第一重配置层。
35.根据权利要求33所述组件封装的制造方法,还包括:
将所述逻辑晶粒与所述存储器晶粒安置在第二重配置层上,所述第二重配置层包括一或多个第二导电特征配置在第二介电层中。
36.根据权利要求33所述组件封装的制造方法,其中所述模制材料延伸在所述第三钝化层的顶面与所述第一重配置层之间。
37.根据权利要求33所述组件封装的制造方法,其中所述模制材料接触所述第二连接件的侧壁。
38.根据权利要求33所述组件封装的制造方法,其中所述第二钝化层隔离所述第一连接件与所述模制材料。
39.根据权利要求33所述组件封装的制造方法,其中所述第一温度介于180°C至230°C之间。
40.根据权利要求33所述组件封装的制造方法,还包括进行薄化工艺以薄化所述模制材料,其中所述薄化工艺在侦测到所述第二钝化层时终止。
41.一种组件封装,包括:
第一晶粒;
第一钝化层,覆盖所述第一晶粒;
第二晶粒,邻近所述第一晶粒;
多个重配置层,覆盖所述第一晶粒与所述第二晶粒,其中所述多个重配置层中的每一个重配置层包括一或多个连接件延伸通过相应的介电层,其中所述多个重配置层中的第一重配置层最接近所述第一晶粒与所述第二晶粒,且其中所述第一钝化层接触所述第一重配置层的第一介电层;
模制材料,沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸,其中所述第二晶粒的第一表面最接近所述第一重配置层,其中所述第一重配置层的第一表面最接近所述第二晶粒,且其中所述模制材料延伸在所述第二晶粒的所述第一表面与所述第一重配置层的所述第一表面之间;以及
多个通孔,延伸通过所述模制材料。
42.根据权利要求41所述组件封装,其中所述第一晶粒为逻辑晶粒,而所述第二晶粒为存储器晶粒。
43.根据权利要求41所述组件封装,还包括表面安装组件连接至所述多个重配置层。
44.根据权利要求41所述组件封装,其中所述第一晶粒包括第一接触窗,所述第一接触窗延伸通过所述第一钝化层并接触所述第一介电层。
45.根据权利要求41所述组件封装,其中所述第一钝化层包括聚合物材料。
46.根据权利要求41所述组件封装,其中所述第一钝化层的表面与各所述多个通孔的表面齐平。
47.根据权利要求41所述组件封装,其中所述多个通孔电性耦接至所述多个重配置层。
48.一种组件封装,包括:
第一晶粒,包括第一电性连接件;
第二晶粒,邻近所述第一晶粒,所述第二晶粒包括第二电性连接件;
模制材料,沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸,其中所述模制材料接触所述第一电性连接件的侧壁或所述第二电性连接件的侧壁;
导通孔,延伸通过所述模制材料;以及
第一重配置结构,位于所述第一晶粒与所述第二晶粒上,所述第一重配置结构电性耦接至所述导通孔、所述第一电性连接件以及所述第二电性连接件。
49.根据权利要求48所述组件封装,还包括:
第一钝化层接触所述第一电性连接件的所述侧壁;以及
第二钝化层位于所述第一钝化层上,其中所述第一电性连接件延伸通过所述第二钝化层,且其中所述第一钝化层与所述第二钝化层包括不同材料。
50.根据权利要求49所述组件封装,还包括第三钝化层接触所述第二电性连接件的所述侧壁,其中所述第一钝化层与所述第三钝化层包括相同材料。
51.根据权利要求50所述组件封装,其中所述模制材料接触所述第一钝化层的侧壁、所述第二钝化层的侧壁以及所述第三钝化层的侧壁。
52.根据权利要求48所述组件封装,还包括第二重配置结构位于所述第一晶粒与所述第二晶粒的下方。
53.根据权利要求52所述组件封装,其中所述导通孔电性耦接所述第一重配置结构至所述第二重配置结构。
54.根据权利要求48所述组件封装,还包括表面安装组件电性耦接至所述第一重配置结构,所述第一重配置结构插入至所述表面安装组件与所述模制材料之间。
55.一种组件封装,包括:
第一晶粒,配置在绝缘层上,所述第一晶粒包括第一接触窗延伸通过第一钝化层;
第二晶粒,配置在邻近所述第一晶粒的所述绝缘层上,所述第二晶粒包括第二接触窗延伸通过第二钝化层,其中所述第二钝化层的第一表面包括平坦区与斜角区,其中所述平坦区在第一方向上延伸,所述第一方向平行于所述第二晶粒的主要表面,且其中所述斜角区在第二方向上延伸,所述第二方向与所述第一方向不同;
第三钝化层,覆盖所述第一晶粒;
模制材料,延伸在所述第一晶粒与所述第二晶粒之间,其中所述模制材料接触所述斜角区与所述平坦区中的所述第二钝化层的所述第一表面;以及
重配置结构,覆盖所述第一晶粒与所述第二晶粒,其中所述第三钝化层接触所述重配置结构的介电层,且其中所述第二钝化层的所述第一表面面向所述重配置结构。
56.根据权利要求55所述组件封装,其中所述模制材料接触所述第二接触窗的侧壁。
57.根据权利要求55所述组件封装,还包括多个通孔延伸通过所述模制材料。
58.根据权利要求57所述组件封装,其中所述多个通孔从所述重配置结构延伸至所述绝缘层。
59.根据权利要求55所述组件封装,其中所述第一接触窗延伸通过所述第三钝化层并接触所述重配置结构。
60.根据权利要求55所述组件封装,其中所述第一钝化层与所述第二钝化层包括第一材料,其中所述第三钝化包括第二材料,且其中所述第一材料与所述第二材料不同。
61.一种组件封装,包括:
第一晶粒;
第一钝化层,覆盖所述第一晶粒;
第二晶粒,邻近所述第一晶粒;
第一绝缘层,覆盖所述第一晶粒与所述第二晶粒,其中所述第一钝化层与所述第一绝缘层物理接触;以及
模制材料,沿着所述第一晶粒的侧壁、所述第二晶粒的侧壁以及所述第一钝化层的侧壁延伸,其中所述模制材料延伸在所述第二晶粒与所述第一绝缘层之间。
62.根据权利要求61所述组件封装,还包括多个导电柱延伸通过所述模制材料。
63.根据权利要求61所述组件封装,其中所述第一钝化层与所述第一绝缘层包括相同聚合物材料。
64.根据权利要求61所述组件封装,还包括:
第二钝化层覆盖所述第一晶粒,其中所述第一钝化层插入所述第二钝化层与所述第一绝缘层之间;以及
第三钝化层覆盖所述第二晶粒,其中所述模制材料延伸在所述第三钝化层与所述第一绝缘层之间。
65.根据权利要求64所述组件封装,其中所述第二钝化层与所述第三钝化层包括相同材料。
66.根据权利要求64所述组件封装,其中所述第一钝化层与所述第二钝化层包括不同材料。
67.根据权利要求61所述组件封装,其中所述第一钝化层的表面与所述模制材料的表面齐平。
68.一种组件封装,包括:
第一晶粒,包括第一电性连接件;
第二晶粒,邻近所述第一晶粒,所述第二晶粒包括二电性连接件;
模制材料,沿着所述第一晶粒的侧壁与所述第二晶粒的侧壁延伸,其中所述模制材料与所述第二电性连接件的侧壁物理接触,且其中所述第一电性连接件的侧壁与所述模制材料分隔;以及
第一绝缘层,位于所述第一晶粒与所述第二晶粒上,所述第一绝缘层与所述第一电性连接件、所述第二电性连接件以及所述模制材料物理接触。
69.根据权利要求68所述组件封装,还包括第一导电柱与第二导电柱延伸通过所述模制材料,其中所述第一晶粒与所述第二晶粒插入在所述第一导电柱与所述第二导电柱之间。
70.根据权利要求68所述组件封装,还包括:
第一钝化层环绕所述第一电性连接件;以及
第二钝化层位于所述第一钝化层上,其中所述第一电性连接件延伸通过所述第二钝化层,其中所述第二钝化层与所述第一绝缘层物理接触,且其中所述第一钝化层与所述第二钝化层包括不同材料。
71.根据权利要求70所述组件封装,还包括第三钝化层环绕所述第二电性连接件,其中所述第一钝化层与所述第三钝化层包括相同材料。
72.根据权利要求70所述组件封装,其中所述第二钝化层与所述第一绝缘层包括相同材料。
73.根据权利要求70所述组件封装,其中所述模制材料与所述第一钝化层的侧壁以及所述第二钝化层的侧壁物理接触。
74.根据权利要求68所述组件封装,还包括导电层位于所述第一绝缘层上,所述导电层的第一部分延伸通过所述第一绝缘层并与所述第一电性连接件物理接触,所述导电层的第二部分延伸通过所述第一绝缘层并与所述第二电性连接件物理接触。
75.一种组件封装,包括:
第一晶粒,包括第一接触窗延伸通过第一钝化层;
第二晶粒,包括第二接触窗延伸通过第二钝化层;
第三钝化层,覆盖所述第一钝化层并环绕所述第一接触窗;
模制材料,延伸在所述第一晶粒与所述第二晶粒之间,其中所述模制材料与所述第一钝化层的侧壁、所述第二钝化层的侧壁以及所述第三钝化层的侧壁物理接触;以及
第一绝缘层,覆盖所述第一晶粒与所述第二晶粒,其中所述第三钝化层与所述第一绝缘层物理接触,且其中所述模制材料分隔所述第二钝化层与所述第一绝缘层。
76.根据权利要求75所述组件封装,其中所述模制材料接触所述第二接触窗的侧壁。
77.根据权利要求75所述组件封装,还包括导电柱延伸通过所述模制材料。
78.根据权利要求77所述组件封装,其中所述导电柱的第一表面与所述第一晶粒的表面齐平,其中所述导电柱的第二表面与所述第三钝化层的表面齐平,且其中所述导电柱的所述第一表面相对于所述导电柱的所述第二表面。
79.根据权利要求75所述组件封装,其中所述第一钝化层与所述第二钝化层包括第一材料,且其中所述第三钝化层包括第二材料,所述第二材料与所述第一材料不同。
80.根据权利要求79所述组件封装,其中所述第一绝缘层包括所述第二材料。
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