TWI694564B - 元件封裝及其製造方法 - Google Patents

元件封裝及其製造方法 Download PDF

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TWI694564B
TWI694564B TW105130338A TW105130338A TWI694564B TW I694564 B TWI694564 B TW I694564B TW 105130338 A TW105130338 A TW 105130338A TW 105130338 A TW105130338 A TW 105130338A TW I694564 B TWI694564 B TW I694564B
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Taiwan
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die
layer
passivation layer
reconfiguration
molding material
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TW105130338A
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TW201803055A (zh
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余振華
郭宏瑞
胡毓祥
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台灣積體電路製造股份有限公司
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Abstract

一種元件封裝與形成方法。元件封裝包括邏輯晶粒以及 邏輯晶粒上的第一鈍化層。元件封裝亦包括記憶體晶粒以及沿著所述邏輯晶粒與所述記憶體晶粒的側壁延伸的模製化合物。元件封裝亦包括延伸通過所述模製化合物的導通孔以及所述模製化合物上的第一重配置層結構。所述模製化合物延伸至所述記憶體晶粒的頂面與所述第一重配置層結構的底面之間。所述第一鈍化層的頂面與所述第一重配置層結構的底面接觸。

Description

元件封裝及其製造方法
本發明實施例是有關於一種元件封裝及其製造方法。
在習知的封裝技術中(例如扇出型封裝)，重配置層(redistribution layer，RDL)結構可形成在晶粒上並與晶粒中的主動元件電性連接。輸入/輸出(Input/output，I/O)接墊(例如球底金屬層(under-bump metallurgy，UBM)上的焊球)可於後續形成並藉由RDL結構電性連接至晶粒。此封裝技術的優勢特徵在於形成扇出型封裝體的可能性。因此，位在晶粒上的I/O接墊可被重配置至一大於所述晶粒的面積，藉此增加所述晶粒的表面上所封裝的I/O接墊的數量。
整合扇出型(Integrated Fan Out，InFO)封裝技術變得愈來愈受歡迎，特別是其可與晶圓級封裝(Wafer Level Packaging，WLP)技術結合。如此一來，所得的封裝結構可提供相對低成本的高功能性密度以及高性能的封裝體。通常情況下，聚合物(例如聚醯亞胺、聚苯噁唑(polybenzoxazole，PBO)以及類似聚合物) 可在InFO元件中形成RDL結構時用以當作鈍化層、絕緣層以及/或保護層。
本發明實施例提供一種元件封裝包括邏輯晶粒、第一鈍化層、記憶體晶粒、模製化合物、導通孔以及第一重配置層結構。第一鈍化層位在所述邏輯晶粒上。模製化合物沿著所述邏輯晶粒的側壁與所述記憶體晶粒的側壁延伸。導通孔延伸穿過所述模製化合物。第一重配置層結構位在所述模製化合物上。所述模製化合物沿著與所述記憶體晶粒相交並與所述記憶體晶粒的所述側壁平行的線延伸在所述記憶體晶粒的頂面與所述第一重配置層結構的底面之間。所述第一鈍化層的頂面與所述第一重配置層結構的所述底面接觸。
本發明實施例提供一種元件封裝包括第一晶粒、第二晶粒、第一絕緣層、模製化合物以及介電層。第一晶粒包括第一接觸窗。第二晶粒包括第二接觸窗。第一絕緣層位於所述第一晶粒上。所述第一接觸窗延伸穿過所述第一絕緣層。模製化合物沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸，其中所述模製化合物的部分表面與所述第一絕緣層的最遠離所述第一晶粒的表面齊平。介電層覆蓋所述第一晶粒與所述第二晶粒。一或多個導電件在所述介電層中延伸，其中所述第一接觸窗與所述第二接觸窗分別電性連接至所述一或多個導電件。所述模製化合物的所述 部分表面接觸所述介電層的部分表面。所述介電層的所述部分表面橫向配置在所述第二晶粒的第一側壁與所述第二晶粒的第二側壁之間，所述第一側壁相對於所述第二側壁。
本發明實施例提供一種元件封裝包括第一重配置結構、邏輯晶粒、記憶體晶粒、鈍化層、模製材料、第二重配置結構以及一或多個連接件。第一重配置結構包括一或多個第一介電層以及一或多個第一導電件延伸穿過所述一或多個第一介電層。邏輯晶粒位於所述第一重配置結構上。記憶體晶粒位於所述第一重配置結構上。所述記憶體晶粒位於所述邏輯晶粒旁。鈍化層位於所述邏輯晶粒上。模製材料沿著所述邏輯晶粒與所述記憶體晶粒之間的最短線延伸在所述邏輯晶粒與所述記憶體晶粒之間。第二重配置結構包括一或多個第二介電層以及一或多個第二導電件延伸穿過所述一或多個第二介電層。所述鈍化層接觸所述第二重配置結構。一或多個連接件位於所述第二重配置結構上。所述模製材料延伸在所述記憶體晶粒的最接近所述第二重配置結構的表面與所述一或多個連接件的最接近所述記憶體晶粒的表面之間。
本發明實施例提供一種元件封裝的製造方法包括：提供邏輯晶粒與記憶體晶粒；在所述邏輯晶粒上形成第一導電柱並在所述記憶體晶粒上形成第二導電柱；在所述邏輯晶粒上形成第一鈍化層；形成沿著所述邏輯晶粒的側壁與所述記憶體晶粒的側壁延伸的模製化合物；薄化所述模製化合物，使得所述模製化合物的上表面與所述第一鈍化層的上表面實質上共平面，其中在薄化 後，所述模製化合物的一部分配置於所述記憶體晶粒上；以及在所述模製化合物上形成重配置層(RDL)結構，其中所述第一鈍化層的所述上表面與所述重配置層結構的下表面接觸。
本發明實施例提供一種元件封裝的製造方法包括：接收第一晶粒，第一鈍化層與第一導電柱配置在所述第一晶粒上；接收第二晶粒，第二導電柱配置在所述第二晶粒上；形成第一重配置層(RDL)結構；將所述第一晶粒與所述第二晶粒安置在所述第一重配置層結構上；形成模製化合物，其沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸；薄化所述模製化合物，以暴露所述第一鈍化層、所述第一導電柱、所述第二導電柱以及多個導通孔；以及在所述模製化合物上形成第二重配置層結構，其中所述模製化合物延伸在所述第二重配置層結構的底面與所述第二晶粒的頂面之間，且其中所述第一鈍化層與所述第二重配置層結構的所述底面接觸。
本發明實施例提供一種元件封裝的製造方法包括：在邏輯晶粒上形成第一鈍化層；在所述邏輯晶粒上的所述第一鈍化層上沉積第二鈍化層；在第一溫度下固化所述第二鈍化層；在所述邏輯晶粒上配置第一連接件，所述第一連接件延伸穿過所述第一鈍化層與所述第二鈍化層；在記憶體晶粒上形成第三鈍化層；在所述記憶體晶粒上配置第二連接件，所述第二連接件延伸穿過所述第三鈍化層；形成沿著所述邏輯晶粒的側壁與所述記憶體晶粒的側壁延伸的模製材料，其中所述模製材料接觸所述第三鈍化層 的頂面；以及在所述模製材料、所述邏輯晶粒以及所述記憶體晶粒上形成第一重配置層，所述第一重配置層包括一或多個第一導電特徵配置在第一介電層中，其中所述第一連接件與所述第二連接件分別電性連接至所述一或多個第一導電特徵。
本發明實施例提供一種元件封裝包括第一晶粒、第一鈍化層、第二晶粒、多個重配置層、模製材料以及多個通孔。第一鈍化層覆蓋所述第一晶粒。第二晶粒鄰近所述第一晶粒。多個重配置層覆蓋所述第一晶粒與所述第二晶粒，其中所述多個重配置層中的每一個重配置層包括一或多個連接件延伸穿過相應的介電層，其中所述多個重配置層中的第一重配置層最接近所述第一晶粒與所述第二晶粒，且其中所述第一鈍化層接觸所述第一重配置層的第一介電層。模製材料沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸，其中所述第二晶粒的第一表面最接近所述第一重配置層，其中所述第一重配置層的第一表面最接近所述第二晶粒，且其中所述模製材料延伸在所述第二晶粒的所述第一表面與所述第一重配置層的所述第一表面之間。多個通孔延伸穿過所述模製材料。
本發明實施例提供一種元件封裝包括第一晶粒、第二晶粒、模製材料、導通孔以及第一重配置結構。第一晶粒包括第一電性連接件。第二晶粒鄰近所述第一晶粒，所述第二晶粒包括第二電性連接件。模製材料沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸，其中所述模製材料接觸所述第一電性連接件的側 壁或所述第二電性連接件的側壁。導通孔延伸穿過所述模製材料。第一重配置結構位於所述第一晶粒與所述第二晶粒上，所述第一重配置結構電性耦接至所述導通孔、所述第一電性連接件以及所述第二電性連接件。
本發明實施例提供一種元件封裝包括第一晶粒、第二晶粒、第三鈍化層、模製材料以及重配置結構。第一晶粒配置在絕緣層上，所述第一晶粒包括第一接觸窗延伸穿過第一鈍化層。第二晶粒配置在鄰近所述第一晶粒的所述絕緣層上，所述第二晶粒包括第二接觸窗延伸穿過第二鈍化層，其中所述第二鈍化層的第一表面包括平坦區與斜角區，其中所述平坦區在第一方向上延伸，所述第一方向平行於所述第二晶粒的主要表面，且其中所述斜角區在第二方向上延伸，所述第二方向與所述第一方向不同。第三鈍化層覆蓋所述第一晶粒。模製材料延伸在所述第一晶粒與所述第二晶粒之間，其中所述模製材料接觸所述斜角區與所述平坦區中的所述第二鈍化層的所述第一表面。重配置結構覆蓋所述第一晶粒與所述第二晶粒，其中所述第三鈍化層接觸所述重配置結構的介電層，且其中所述第二鈍化層的所述第一表面面向所述重配置結構。
本發明實施例提供一種元件封裝包括第一晶粒、第一鈍化層、第二晶粒、第一絕緣層以及模製材料。第一鈍化層覆蓋所述第一晶粒。第二晶粒鄰近所述第一晶粒。第一絕緣層覆蓋所述第一晶粒與所述第二晶粒，其中所述第一鈍化層與所述第一絕緣 層物理接觸。模製材料沿著所述第一晶粒的側壁、所述第二晶粒的側壁以及所述第一鈍化層的側壁延伸，其中所述模製材料延伸在所述第二晶粒與所述第一絕緣層之間。
本發明實施例提供一種元件封裝包括第一晶粒、第二晶粒、模製材料以及第一絕緣層。第一晶粒包括第一電性連接件。第二晶粒鄰近所述第一晶粒，所述第二晶粒包括二電性連接件。模製材料沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸，其中所述模製材料與所述第二電性連接件的側壁物理接觸，且其中所述第一電性連接件的側壁與所述模製材料分隔。第一絕緣層位於所述第一晶粒與所述第二晶粒上，所述第一絕緣層與所述第一電性連接件、所述第二電性連接件以及所述模製材料物理接觸。
本發明實施例提供一種元件封裝包括第一晶粒、第二晶粒、第三鈍化層、模製材料以及第一絕緣層。第一晶粒包括第一接觸窗延伸穿過第一鈍化層。第二晶粒包括第二接觸窗延伸穿過第二鈍化層。第三鈍化層覆蓋所述第一鈍化層並環繞所述第一接觸窗。模製材料延伸在所述第一晶粒與所述第二晶粒之間，其中所述模製材料與所述第一鈍化層的側壁、所述第二鈍化層的側壁以及所述第三鈍化層的側壁物理接觸。第一絕緣層覆蓋所述第一晶粒與所述第二晶粒，其中所述第三鈍化層與所述第一絕緣層物理接觸，且其中所述模製材料分隔所述第二鈍化層與所述第一絕緣層。
100A、100B:晶圓
102A:高帶寬的記憶體晶粒
102B:邏輯晶粒
104:接觸墊
106、110:鈍化層
108:導電柱
200:元件封裝
202:載體
204:黏著層
206、226:重配置層結構
208:導電特徵
208’:接觸墊
210、222:聚合物層
212:導通孔
214:光阻
216、218、218’、225:開口
220:模製化合物
224:導電特徵
228:連接件
230:表面安裝元件
232:球底金屬層
240、244:頂面
242:底面
H1:高度
圖1A、圖1B、圖2、圖3A、圖3B以及圖4至圖12繪示為依照一些實施例的一種元件封裝的製造步驟的剖面示意圖。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例，且亦可包括第一特徵與第二特徵之間可形成有額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複使用元件符號及/或字母。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在...上」、「在...上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被 另外定向(旋轉90度或在其他定向)，而本文所用的空間相對術語相應地作出解釋。
在具體地敘述圖式實施例之前，本揭露實施例之某些優勢特徵以及方面將通常描述如下。一般而言，一種新的結構公開了以一種方式將邏輯晶粒與高帶寬(bandwidth)的記憶體晶粒一起封裝在元件封裝中，其改善了高帶寬的記憶體晶粒的可靠度並且增加了元件封裝的良率。舉例來說，多個晶粒被封裝在單一個元件封裝中。在一些實施例中，一個晶粒或更多個晶粒可包括所述晶粒的頂面上的鈍化層。所述鈍化層可在進行研磨製程以平坦化所述晶粒的頂面時提供給晶粒一些優點。舉例來說，所述鈍化層可以是一「研磨停止」層，其用在所述晶粒與所述鈍化層上所進行的研磨製程。然而，用於某些鈍化層(例如聚苯噁唑系材料)的某些材料可能需要在高溫時進行固化。另一方面，某些高帶寬的記憶體晶粒(例如動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒)可能對用於固化所述鈍化層的高溫敏感。假設將在高溫時固化的鈍化層安置在DRAM晶粒上並在後續進行固化，此將增加DRAM晶粒的故障可能性，且相對應地降低DRAM晶粒的可靠度並降低元件封裝的良率。
另外，提供一種新的結構，其中邏輯晶粒與高帶寬的記憶體晶粒一起被封裝在元件封裝中。所述邏輯晶粒包括覆蓋所述邏輯晶粒的鈍化層，所述鈍化層包括高溫固化材料。所述高帶寬的記憶體晶粒不包括覆蓋所述高帶寬的記憶體晶粒的鈍化層，所 述鈍化層包括高溫固化材料。於此所述的實施例可輕易地整合在封裝製程中，且與晶圓級封裝技術相容，並可增加所述高帶寬的記憶體晶粒以及所述元件封裝(其包括所述高帶寬的記憶體晶粒)的可靠度以及良率。
圖1A至圖12繪示為依照各種實施例的一種整合扇出型(InFO)封裝的中間製造步驟。參照圖1A，晶圓100A的一部分具有多個高帶寬的記憶體晶粒102A。高帶寬的記憶體晶粒102A可包括DRAM、混合記憶體立方體(hybrid memory cube，HMC)、磁阻式隨機存取記憶體(Magnetoresistive random-access memory，MRAM)、快閃記憶體(Flash)、奈米尺寸分子動力記憶體(Nanoscale Molecular Dynamics，NAMD)，上述組合或類似晶粒。在一些實施例中，功能性測試(例如電性連接測試以及壓力測試)可在晶圓100A上進行，且高帶寬的記憶體晶粒102A可通過此功能性測試。舉例來說，高帶寬的記憶體晶粒102A可以是已知良好晶粒(known good dies，KGDs)。
各高帶寬的記憶體晶粒102A可以是半導體晶粒且可包括基板、主動元件以及內連線結構(未繪示)。所述基板可以是塊狀矽基板(bulk silicon substrate)，然而，其他半導體材料(包括III族元素、IV族元素以及V族元素)亦可被使用。另外，所述基板可以是絕緣體上有矽(silicon-on-insulator)基板、絕緣體上有鍺(germanium-on-insulator)基板或類似基板。主動元件(例如電晶體)可被形成在所述基板的頂面處。內連線結構可被形成在 所述主動元件以及所述基板上。
所述內連線結構可包括層間介電(inter-layer dielectric，ILD)層以及/或金屬間介電(inter-metal dielectric，IMD)層，其包含使用任何合適方法所形成的導電特徵(例如包括銅、鋁、鎢、其組合或類似材料的導線以及導通孔)。所述ILD層以及IMD層可包括配置在此導電特徵之間的低介電常數的介電材料(low-k dielectric materials)，其具有例如低於約4.0或甚至低於2.8的k值。在一些實施例中，ILD層與IMD層可由例如磷矽玻璃(phosphosilicate glass，PSG)、硼磷矽玻璃(borophosphosilicate glass，BPSG)、氟矽酸鹽玻璃(fluorosilicate glass，FSG)、SiOxCy、旋塗式玻璃(Spin-On-Glass)、旋塗式聚合物(Spin-On-Polymers)、矽碳材料(silicon carbon material)、其化合物、其組成物、其組合或類似材料。所述內連線結構可與各種主動元件電性連接以在各高帶寬的記憶體晶粒102A內形成功能性電路。
輸入/輸出(I/O)與鈍化特徵可形成在所述內連線結構上。舉例來說，接觸墊104可形成在所述內連線結構上且可藉由所述內連線結構中的各種導電特徵與所述主動元件電性連接。接觸墊104可包括導電特徵，例如鋁、銅或類似材料。此外，鈍化層106可形成在內連線結構與接觸墊104上。鈍化層106可當作界面、絕緣以及/或保護層，其用於後續製程步驟中高帶寬的記憶體晶粒102A上的額外封裝特徵的形成。在一些實施例中，鈍化層106可改善附著性、提供絕緣性以及/或防止在後續製程步驟中下 方的內連線結構的損傷。在一些實施例中，鈍化層106可由非有機材料(例如氧化矽、未摻雜矽玻璃、氮氧化矽或類似材料)所形成。然而，其他合適的鈍化材料亦可被使用。部分鈍化層106可覆蓋所述接觸墊104的邊緣部分。
導電柱108可配置在接觸墊104與鈍化層106上。在一些實施例中，導電柱108包括銅，然而，其他合適的材料(例如金屬以及/或金屬合金)亦可用於導電柱108。導電柱108可延伸通過鈍化層106中的開口且電性連接至接觸墊104。導電柱108可例如具有約5微米至約20微米的高度H1。導電柱108還可橫向延伸至鈍化層106的邊緣並覆蓋部分鈍化層106。
在一些實施例中，在上視圖中，導電柱108實質上為矩形。在一些實施例中，導電柱108可以是球形或多邊形。導電柱108亦可不橫向延伸至鈍化層106的邊緣或未覆蓋部分鈍化層106。然而，導電柱108的其他配置亦可被使用。舉例來說，導電柱108可以是任何類型的合適的接觸窗，例如接觸墊、頂金屬化層或類似接觸窗。
高帶寬的記憶體晶粒102A的各種特徵可藉由任何合適的方法形成而不在此詳細說明。此外，上述的高帶寬的記憶體晶粒102A的一般特徵以及配置僅是一種例示實施例，且高帶寬的記憶體晶粒102A可包括任意數量的上述特徵以及其他特徵的任意組合。舉例來說，各高帶寬的記憶體晶粒102A可包括多個接觸墊104與多個導電柱108。
圖1B繪示為具有多個邏輯晶粒102B的晶圓100B的一部分。在一些實施例中，功能性測試(例如，電性連接測試以及壓力測試)可在晶圓100B上進行，且邏輯晶粒102B可通過此功能性測試。舉例來說，邏輯晶粒102B可以是已知良好晶粒(KGDs)。上述討論可與圖1A連結，關於部分晶圓100A與高帶寬的記憶體晶粒102A可適用在如圖1B所示的部分晶圓100B，為了簡潔起見將不再贅述。圖1A與圖1B中的相似標號表示相似構件。
如圖2所示，另一個鈍化層110可形成在邏輯晶粒102B的頂面。鈍化層110暴露出導電柱108的至少一部分。在圖式實施例中，鈍化層110為聚合物層，其可例如包括聚醯亞胺(PI)、聚苯噁唑(PBO)、苯並環丁烯(benzocyclobuten，BCB)、環氧樹脂(epoxy)、矽氧樹脂(silicone)、丙烯酸酯(acrylates)、奈米填充酚樹脂(nano-filled pheno resin)、矽氧烷(siloxane)、含氟高分子(fluorinated polymer)、降冰片烯高分子(polynorbornene)或類似材料。另外，鈍化層110可以是介電層，例如氮化矽、氧化矽、氮氧化矽或類似材料。鈍化層110的材料與用於形成鈍化層106的材料不同。鈍化層110可當作界面、絕緣以及/或保護層，其用於後續製程步驟中邏輯晶粒102B上的額外封裝特徵的形成。在一些實施例中，鈍化層110可改善附著性、提供絕緣性以及/或防止後續製程步驟中下方的鈍化層106的損傷。在一些實施例中，鈍化層110可當作「研磨停止」層，其可指出在鈍化層110 上的層所進行的研磨製程的停止點。
鈍化層110可以被沈積或以其他圖案化方式被形成，以暴露出至少部分導電柱108。舉例來說，鈍化層110可使用旋轉塗佈製程(spin-on coating process)來沈積。旋轉塗佈製程的參數可被選擇，使得鈍化層110的沈積暴露出導電柱108。舉例來說，旋轉速度、所使用的鈍化材料的量以及類似參數可被控制，使得沈積之後的鈍化層110不會覆蓋或延伸在導電柱108的頂面上方。另外，鈍化層110可以一種方式被形成，其使得鈍化層110的頂面高於導電柱108的頂面，並使用薄化製程(例如研磨製程)以薄化鈍化層110進而暴露導電柱108。
在邏輯晶粒102B上形成鈍化層110之後，鈍化層110可經過固化製程。舉例來說，鈍化層110可被加熱至180℃至390℃之間的溫度並持續30分鐘至4小時。
如上述討論，高帶寬的記憶體晶粒102A(如圖1A所示)可能對用於固化鈍化層110的高溫敏感。在一些實施例中，所述高溫可包括高於250℃的溫度，其會增加一些高帶寬的記憶體晶粒102A的故障，然而，低於250℃的溫度亦可能會增加一些高帶寬的記憶體晶粒102A的故障率。高帶寬的記憶體晶粒102A上的鈍化層，其亦經過固化製程且與鈍化層110相似，可能導致一些高帶寬的記憶體晶粒102A的故障、降低所述高帶寬的記憶體晶粒102A的可靠度以及/或減少所形成的元件封裝的良率。所述元件封裝包括一個高帶寬的記憶體晶粒102A或更多個高帶寬的記憶體 晶粒102A。因此，鈍化層不會形成在高帶寬的記憶體晶粒102A上，此鈍化層包括高溫固化材料且類似邏輯晶粒102B上的鈍化層110。
參照圖3A，在一些實施例中，高帶寬的記憶體晶粒102A可被分離。舉例來說，晶圓100A可被薄化至一所需的厚度，例如，藉由在高帶寬的記憶體晶粒102A的背面上進行機械研磨製程、化學機械研磨(chemical mechanical polish，CMP)製程、蝕刻製程或類似製程。黏著層(未繪示)(例如晶粒貼覆膜(die attach film，DAF)或類似膜)可被配置在晶圓100A的背面上。之後，可將高帶寬的記憶體晶粒102A單體化(singulated)。舉例來說，晶粒切割可沿著配置在高帶寬的記憶體晶粒102A之間的切割道(scribe lines)進行，以將各高帶寬的記憶體晶粒102A與晶圓100A分離。
參照圖3B，在一些實施例中，邏輯晶粒102B亦可被分離。鈍化層110形成之後，例如藉由在邏輯晶粒102B的背面上進行機械研磨製程、化學機械研磨(CMP)製程、蝕刻製程或類似製程，晶圓100B可被薄化至一所需的厚度。黏著層(例如晶粒貼覆膜或類似膜)可被配置在晶圓100B的背面上。黏著層(未繪示)可形成在相對於鈍化層110的邏輯晶粒102B的一側上。之後，可將邏輯晶粒102B單體化。舉例來說，晶粒切割可沿著配置在邏輯晶粒102B之間的切割道進行，以將各邏輯晶粒102B與晶圓100B分離。
圖4至圖
Figure 105130338-A0305-02-0019-1
7繪示為在安置高帶寬的記憶體晶粒102A與邏輯晶粒102B之前，形成元件封裝200的各種特徵的各種中間步驟。接著，在圖
Figure 105130338-A0305-02-0019-2
8中，可將高帶寬的記憶體晶粒102A以及邏輯晶粒102B與元件封裝200整合在一起。圖4中，提供載體202。載體202可包括玻璃、陶瓷或其他合適的材料，且載體202在元件封裝200的各種特徵的形成期間可提供結構支撐。在載體202上配置臨時黏著層204(例如膠層、光熱轉換(light-to-heat conversion，LTHC)塗佈層、紫外線(UV)膜或類似膜)。
之後，在黏著層204與載體202上形成背側RDL結構206。RDL結構206可包括形成在一層聚合物層210或更多層聚合物層210中的導電特徵208(例如導線以及/或導通孔)。聚合物層210可使用任何合適的方法(例如旋轉塗佈技術、濺鍍技術或類似技術)以及任何合適材料(例如PI、PBO、BCB、環氧樹脂、矽氧樹脂、丙烯酸酯、奈米填充酚樹脂、矽氧烷、含氟高分子、降冰片烯高分子或類似材料)來形成。
導電特徵208可形成在聚合物層210中。此導電特徵208的形成可包括圖案化聚合物層210(例如使用微影製程與蝕刻製程的組合)並在經圖案化的聚合物層210(例如藉由沈積晶種層並使用罩幕層以定義導電特徵208的形狀)中形成導電特徵208。導電特徵208可被設計以形成功能性電路以及輸入/輸出特徵，並用以後續附著晶粒(例如晶粒102A、102B)。
接著，如圖5所示，在背側RDL結構206與載體202上 可形成圖案化的光阻214。舉例來說，在背側RDL結構206上可沈積如毯覆層(blanket layer)的光阻214。之後，可使用光罩(未繪示)暴露部分光阻214。依據使用負型光阻或正型光阻，使得被暴露或未被暴露的部分光阻214隨後被移除。所得的圖案化的光阻214可包括開口216，其可被沈積在載體202的周邊區域。開口216還暴露背側RDL結構206中的導電特徵208。
圖6繪示將例如銅、銀、金等的導電材料填入開口216以形成導通孔212。開口216的填入可包括先沈積晶種層(未繪示)並以導電材料電鍍開口216(例如電化學電鍍法、無電電鍍法或類似方法)。導電材料可溢出(overfill)開口216，並可進行CMP以移除光阻214上的過多的部分導電材料。
接著，如圖7所示，移除光阻214。電漿灰化製程或濕式剝除製程可被使用以移除光阻214。在電漿灰化製程之後，可選擇性地在硫酸(H2SO4)溶液中進行濕式浸入，以清潔元件封裝200並移除殘留的光阻材料。
因此，導通孔212可形成在背側RDL結構206上。另外，導通孔212亦可被導電間柱(conductive studs)或導線(例如銅線、金線或銀線)所取代。導通孔212可藉由開口218彼此分離。相鄰導通孔212之間的至少一開口218’可足夠大以配置一個晶粒或更多個晶粒(例如晶粒102A與晶粒102B)在其中。
接著，如圖8所示，一個高帶寬的記憶體晶粒102A或更多個高帶寬的記憶體晶粒102A以及一個邏輯晶粒102B或更多個 邏輯晶粒102B(例如，如圖1至圖5中所形成)被安置在元件封裝200上。如圖所示，元件封裝200可包括載體202以及一個內連線層或更多個內連線層(例如，具有導電特徵208的背側RDL結構206)。其他內連線結構(例如與背側RDL結構206中的導電特徵208電性連接的導通孔212)亦可被包括。黏著層(未繪示)可被使用以將晶粒102A與晶粒102B附著在背側RDL結構206上。在圖式實施例中，一個高帶寬的記憶體晶粒102A與一個邏輯晶粒102B被安置在元件封裝200上，然而，亦可考慮安置超過兩個晶粒。
圖8繪示為一種實施例之高帶寬的記憶體晶粒102A與邏輯晶粒102B被並排安置，且導通孔212被配置在元件封裝200的外緣上。圖8所繪示的構件位置為一示例，亦可考量以其他方式放置高帶寬的記憶體晶粒102A、邏輯晶粒102B以及導通孔212。圖8亦繪示為一種實施例之高帶寬的記憶體晶粒102A上的導電柱108的頂面與邏輯晶粒102B上的導電柱108的頂面實質上共平面。在一些實施例中，高帶寬的記憶體晶粒102A上的導電柱108的頂面與邏輯晶粒102B上的導電柱108的頂面亦可不共平面。
接著參照圖9，在高帶寬的記憶體晶粒102A與邏輯晶粒102B被安置在背側RDL結構206的開口218’中之後，可將模製化合物220形成在元件封裝200上。模製化合物220可被分散以填入高帶寬的記憶體晶粒102A、邏輯晶粒102B以及導通孔212之間的空隙中。模製化合物220延伸至邏輯晶粒102B上的鈍化層 110上。由於高帶寬的記憶體晶粒102A不包括鈍化層110，因此模製材料可直接延伸至鈍化層106上並沿著高帶寬的記憶體晶粒102A上的導電柱108的側壁延伸。
模製化合物220可包括任何合適的材料，例如環氧樹脂、模製底膠(molding underfill)或類似材料。形成模製化合物220的合適方法可包括壓縮成型法(compressive molding)、移轉成型法(transfer molding)、液態包封成型法(liquid encapsulent molding)或類似方法。舉例來說，模製化合物220可以液態形式被分散在晶粒102A、晶粒102B以及導通孔212之間。之後，進行一固化製程以固化模製化合物220。模製化合物220的填入可溢出高帶寬的記憶體晶粒102A、邏輯晶粒102B以及導通孔212，使得模製化合物220覆蓋高帶寬的記憶體晶粒102A、邏輯晶粒102B以及導通孔212的頂面。
在圖10所繪示的製程步驟中，模製化合物220可被平坦化(例如使用CMP、研磨法或類似方法)以減少整體厚度，並藉此暴露導通孔212與導電柱108。在一些實施例中，研磨製程可終止在鈍化層110的偵測上。因此，鈍化層110可當作「研磨停止」層。由於所得結構包括延伸通過模製化合物220的導通孔212，導通孔212可被視為模製導通孔(through molding vias)、間導通孔(through intervias，TIVs)或類似結構。導通孔212提供電性連接至元件封裝200中的背側RDL結構206中的導電特徵208。
如圖10所繪示的實施例中，邏輯晶粒102B上的導電柱 108的頂面可與鈍化層110的頂面實質上共平面。另外，鈍化層110的頂面與模製化合物220的頂面實質上共平面。高帶寬的記憶體晶粒102A上的導電柱108的頂面亦可與模製化合物220的頂面實質上共平面，而模製化合物220延伸至高帶寬的記憶體晶粒102A上的鈍化層106上。
圖11與圖12繪示為形成RDL結構226(如圖12所示)的製造步驟，所述RDL結構226具有與導電柱108電性連接的導電特徵224(例如導通孔以及/或接觸窗)。圖11繪示為具有開口225的圖案化的聚合物層222的形成。聚合物層222可包括P1、PBO、BCB、環氧樹脂、矽氧樹脂、丙烯酸酯、奈米填充酚樹脂、矽氧烷、含氟高分子、降冰片烯高分子或類似材料。在一些實施例中，聚合物層222可包括與鈍化層110相同的材料，但其他合適材料亦可適用於聚合物層222。
聚合物層222可使用毯覆式沈積製程(例如旋轉塗佈法、濺鍍法或類似方法)形成在模製化合物220與導電柱108上。沈積之後，可使用例如微影製程以及/或蝕刻製程圖案化聚合物層222以形成開口225。開口225可暴露導電柱108與導通孔212。
然後，可將導電材料填入開口225中。舉例來說，可在開口225中形成晶種層(未繪示)，並使用電化學電鍍製程、無電電鍍製程或類似製程將導電材料電鍍至開口225中。聚合物層222中的所得導通孔(如圖12所示)可電性連接至導電柱108以及/或導通孔212。
具有導電特徵的額外聚合物層亦可形成在聚合物層222上。舉例來說，圖12繪示了具有導電特徵224在其中的RDL結構226。RDL結構226在組成以及形成過程中皆可與背側RDL結構206實質上相似。舉例來說，RDL結構226可包括配置在各種聚合物層之間的導電特徵224(例如導線與導通孔)。導電特徵224藉由導電柱108與高帶寬的記憶體晶粒102A以及邏輯晶粒102B電性連接。為了簡潔起見，RDL結構226之額外的詳細說明於此便不再贅述。
如圖12所示，在一些實施例中，模製材料220可延伸至RDL結構226的底面242與高帶寬的記憶體晶粒102A的頂面240之間。在一些實施例中，鈍化層110的頂面244可與RDL結構226的底面242接觸，使得模製化合物220不配置在鈍化層110的頂面244與RDL結構226的底面242之間。
額外的封裝特徵(例如外部連接件(external connectors)228以及其他表面安裝元件(surface mount devices，SMDs)230)可被配置在RDL結構226上。連接件228可以是球格陣列(ball grid array，BGA)的焊球、可控塌陷晶片連接(controlled collapse chip connector，C4)凸塊或類似物，其配置在RDL結構226上的球底金屬層(under metal metallurgies，UBMs)232上。連接件228與表面安裝元件230可藉由通過RDL結構226的方式與一個晶粒102A、102B或更多個晶粒102A、102B電性連接。連接件228可用以將元件封裝200電性連接至其他封裝構件，例如另一個元件 晶粒、中介片(interposers)、封裝基板、印刷電路板、主機板(mother board)或類似構件。
圖12還繪示了可藉由移除臨時黏著層204，將元件封裝200與載體202分離。黏著層204的移除製程可包括對LTHC層加熱、對UV膠帶照射UV光或類似製程。載體202的移除可暴露元件封裝200中的額外輸入/輸出接觸。舉例來說，背側RDL結構206中的導電特徵(接觸墊208’)亦可用於將元件封裝200電性連接至其他封裝構件，例如記憶體晶粒或任何其他封裝構件。
此外，一種新的結構提供了以一種方式將邏輯晶粒與高帶寬的記憶體晶粒一起封裝在元件封裝中，其可提升高帶寬的記憶體晶粒的可靠度以及元件封裝的良率。如上述詳細說明，高帶寬的記憶體晶粒與邏輯晶粒一起被封裝在元件封裝中。鈍化層形成在邏輯晶粒上。所述鈍化層可保護邏輯晶粒，且其可於對所述鈍化層上的模製材料進行的研磨製程中作為「研磨停止」層。所述鈍化層可包括高溫固化材料，例如聚苯噁唑(PBO)系材料。元件封裝中的高帶寬的記憶體晶粒可能對於固化所述鈍化層所需的高溫敏感。舉例來說，假設將在高溫時固化的鈍化層安置在DRAM晶粒上並於後續進行固化，此將增加DRAM晶粒的故障可能性，且相對應地降低DRAM晶粒的可靠度。因此，所述高帶寬的記憶體晶粒不包括高帶寬的記憶體晶粒上的高溫固化的鈍化層。而模製化合物直接形成在所述高帶寬的記憶體晶粒上。另外，提供一種新的結構，其邏輯晶粒與高帶寬的記憶體晶粒一起被封 裝在元件封裝中，所述新的結構可增加所述元件封裝的可靠度並增加所述元件封裝的良率。
根據一實施例，元件封裝包括邏輯晶粒。第一鈍化層位在所述邏輯晶粒上。所述元件封裝亦包括記憶體晶粒。模製化合物沿著所述邏輯晶粒與所述記憶體晶粒的側壁延伸。導通孔延伸通過所述模製化合物。第一重配置層(RDL)結構位在所述模製化合物上。所述模製化合物延伸至所述記憶體晶粒的頂面與所述第一重配置層結構的底面之間。所述第一鈍化層的頂面與所述第一重配置層結構的所述底面接觸。
根據另一實施例，元件封裝的形成方法包括提供邏輯晶粒與記憶體晶粒。所述方法亦包括在所述邏輯晶粒上形成第一導電柱並在所述記憶體晶粒上形成第二導電柱。所述方法亦包括在所述邏輯晶粒上形成第一鈍化層。所述方法亦包括形成模製化合物，其沿著所述邏輯晶粒與所述記憶體晶粒的側壁延伸。所述方法亦包括薄化所述模製化合物，使得所述模製化合物的上表面與所述第一鈍化層的上表面實質上共平面。在薄化後，所述模製化合物的一部分配置於所述記憶體晶粒上。所述方法亦包括在所述模製化合物上形成重配置層(RDL)結構。所述第一鈍化層的所述上表面與所述模製化合物的下表面接觸。
根據又一實施例，元件封裝的形成方法包括接收第一晶粒，第一鈍化層與第一導電柱配置在所述第一晶粒上。所述方法亦包括接收第二晶粒，第二導電柱配置在所述第二晶粒上。所述 方法亦包括形成第一重配置層(RDL)結構。將所述第一晶粒與所述第二晶粒安置在所述第一重配置層結構上。所述方法亦包括形成模製化合物，其沿著所述第一晶粒與所述第二晶粒的側壁延伸。所述方法亦包括薄化所述模製化合物以暴露所述第一鈍化層、所述第一導電柱、所述第二導電柱以及多個導通孔。所述方法亦包括在所述模製化合物上形成第二重配置層結構。所述模製化合物延伸至所述第二重配置層結構的底面與所述第二晶粒的頂面之間。第一鈍化層與所述第二重配置層結構的底面接觸。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
102A:高帶寬的記憶體晶粒
102B:邏輯晶粒
106、110:鈍化層
108:導電柱
200:元件封裝
206、226:重配置層結構
208:導電特徵
208’:接觸墊
210:聚合物層
212:導通孔
220:模製化合物
224:導電特徵
228:連接件
230:表面安裝元件
232:球底金屬層
240、244:頂面
242:底面

Claims (12)

  1. 一種元件封裝，包括：邏輯晶粒，第一鈍化層位在所述邏輯晶粒上；記憶體晶粒；模製化合物，沿著所述邏輯晶粒的側壁與所述記憶體晶粒的側壁延伸；導通孔，延伸穿過所述模製化合物；以及第一重配置層結構，位在所述模製化合物上，其中所述模製化合物沿著與所述記憶體晶粒相交並與所述記憶體晶粒的所述側壁平行的線延伸在所述記憶體晶粒的頂面與所述第一重配置層結構的底面之間，且其中所述第一鈍化層的頂面與所述第一重配置層結構的所述底面接觸。
  2. 一種元件封裝，包括：第一晶粒，包括第一接觸窗；第二晶粒，包括第二接觸窗；第一絕緣層，位於所述第一晶粒上，所述第一接觸窗延伸穿過所述第一絕緣層；模製化合物，沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸，其中所述模製化合物的部分表面與所述第一絕緣層的最遠離所述第一晶粒的表面齊平；以及介電層，覆蓋所述第一晶粒與所述第二晶粒，一或多個導電件在所述介電層中延伸，其中所述第一接觸窗與所述第二接觸窗 分別電性連接至所述一或多個導電件，且其中所述模製化合物的所述部分表面接觸所述介電層的部分表面，所述介電層的所述部分表面橫向配置在所述第二晶粒的第一側壁與所述第二晶粒的第二側壁之間，所述第一側壁相對於所述第二側壁。
  3. 一種元件封裝，包括：第一重配置結構，包括一或多個第一介電層以及一或多個第一導電件延伸穿過所述一或多個第一介電層；邏輯晶粒，位於所述第一重配置結構上；記憶體晶粒，位於所述第一重配置結構上，所述記憶體晶粒位於所述邏輯晶粒旁；鈍化層，位於所述邏輯晶粒上；模製材料，沿著所述邏輯晶粒與所述記憶體晶粒之間的最短線延伸在所述邏輯晶粒與所述記憶體晶粒之間；第二重配置結構，包括一或多個第二介電層以及一或多個第二導電件延伸穿過所述一或多個第二介電層，所述鈍化層接觸所述第二重配置結構；以及一或多個連接件，位於所述第二重配置結構上，所述模製材料延伸在所述記憶體晶粒的最接近所述第二重配置結構的表面與所述一或多個連接件的最接近所述記憶體晶粒的表面之間。
  4. 一種元件封裝的製造方法，包括提供邏輯晶粒與記憶體晶粒；在所述邏輯晶粒上形成第一導電柱並在所述記憶體晶粒上形 成第二導電柱；在所述邏輯晶粒上形成第一鈍化層；形成沿著所述邏輯晶粒的側壁與所述記憶體晶粒的側壁延伸的模製化合物；薄化所述模製化合物，使得所述模製化合物的上表面與所述第一鈍化層的上表面實質上共平面，其中在薄化後，所述模製化合物的一部分配置於所述記憶體晶粒上；以及在所述模製化合物上形成重配置層(RDL)結構，其中所述第一鈍化層的所述上表面與所述重配置層結構的下表面接觸。
  5. 一種元件封裝的製造方法，包括接收第一晶粒，第一鈍化層與第一導電柱配置在所述第一晶粒上；接收第二晶粒，第二導電柱配置在所述第二晶粒上；形成第一重配置層(RDL)結構；將所述第一晶粒與所述第二晶粒安置在所述第一重配置層結構上；形成模製化合物，其沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸；薄化所述模製化合物，以暴露所述第一鈍化層、所述第一導電柱、所述第二導電柱以及多個導通孔；以及在所述模製化合物上形成第二重配置層結構，其中所述模製化合物延伸在所述第二重配置層結構的底面與所述第二晶粒的頂 面之間，且其中所述第一鈍化層與所述第二重配置層結構的所述底面接觸。
  6. 一種元件封裝的製造方法，包括在邏輯晶粒上形成第一鈍化層；在所述邏輯晶粒上的所述第一鈍化層上沉積第二鈍化層；在第一溫度下固化所述第二鈍化層；在所述邏輯晶粒上配置第一連接件，所述第一連接件延伸穿過所述第一鈍化層與所述第二鈍化層；在記憶體晶粒上形成第三鈍化層；在所述記憶體晶粒上配置第二連接件，所述第二連接件延伸穿過所述第三鈍化層；形成沿著所述邏輯晶粒的側壁與所述記憶體晶粒的側壁延伸的模製材料，其中所述模製材料接觸所述第三鈍化層的頂面；以及在所述模製材料、所述邏輯晶粒以及所述記憶體晶粒上形成第一重配置層，所述第一重配置層包括一或多個第一導電特徵配置在第一介電層中，其中所述第一連接件與所述第二連接件分別電性連接至所述一或多個第一導電特徵。
  7. 一種元件封裝，包括：第一晶粒；第一鈍化層，覆蓋所述第一晶粒；第二晶粒，鄰近所述第一晶粒； 多個重配置層，覆蓋所述第一晶粒與所述第二晶粒，其中所述多個重配置層中的每一個重配置層包括一或多個連接件延伸穿過相應的介電層，其中所述多個重配置層中的第一重配置層最接近所述第一晶粒與所述第二晶粒，且其中所述第一鈍化層接觸所述第一重配置層的第一介電層；模製材料，沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸，其中所述第二晶粒的第一表面最接近所述第一重配置層，其中所述第一重配置層的第一表面最接近所述第二晶粒，且其中所述模製材料延伸在所述第二晶粒的所述第一表面與所述第一重配置層的所述第一表面之間；以及多個通孔，延伸穿過所述模製材料。
  8. 一種元件封裝，包括：第一晶粒，包括第一電性連接件；第二晶粒，鄰近所述第一晶粒，所述第二晶粒包括第二電性連接件；模製材料，沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸，其中所述模製材料接觸所述第一電性連接件的側壁或所述第二電性連接件的側壁；導通孔，延伸穿過所述模製材料；以及第一重配置結構，位於所述第一晶粒與所述第二晶粒上，所述第一重配置結構電性耦接至所述導通孔、所述第一電性連接件以及所述第二電性連接件。
  9. 一種元件封裝，包括：第一晶粒，配置在絕緣層上，所述第一晶粒包括第一接觸窗延伸穿過第一鈍化層；第二晶粒，配置在鄰近所述第一晶粒的所述絕緣層上，所述第二晶粒包括第二接觸窗延伸穿過第二鈍化層，其中所述第二鈍化層的第一表面包括平坦區與斜角區，其中所述平坦區在第一方向上延伸，所述第一方向平行於所述第二晶粒的主要表面，且其中所述斜角區在第二方向上延伸，所述第二方向與所述第一方向不同；第三鈍化層，覆蓋所述第一晶粒；模製材料，延伸在所述第一晶粒與所述第二晶粒之間，其中所述模製材料接觸所述斜角區與所述平坦區中的所述第二鈍化層的所述第一表面；以及重配置結構，覆蓋所述第一晶粒與所述第二晶粒，其中所述第三鈍化層接觸所述重配置結構的介電層，且其中所述第二鈍化層的所述第一表面面向所述重配置結構。
  10. 一種元件封裝，包括：第一晶粒；第一鈍化層，覆蓋所述第一晶粒；第二晶粒，鄰近所述第一晶粒；第一絕緣層，覆蓋所述第一晶粒與所述第二晶粒，其中所述第一鈍化層與所述第一絕緣層物理接觸；以及 模製材料，沿著所述第一晶粒的側壁、所述第二晶粒的側壁以及所述第一鈍化層的側壁延伸，其中所述模製材料延伸在所述第二晶粒與所述第一絕緣層之間。
  11. 一種元件封裝，包括：第一晶粒，包括第一電性連接件；第二晶粒，鄰近所述第一晶粒，所述第二晶粒包括二電性連接件；模製材料，沿著所述第一晶粒的側壁與所述第二晶粒的側壁延伸，其中所述模製材料與所述第二電性連接件的側壁物理接觸，且其中所述第一電性連接件的側壁與所述模製材料分隔；以及第一絕緣層，位於所述第一晶粒與所述第二晶粒上，所述第一絕緣層與所述第一電性連接件、所述第二電性連接件以及所述模製材料物理接觸。
  12. 一種元件封裝，包括：第一晶粒，包括第一接觸窗延伸穿過第一鈍化層；第二晶粒，包括第二接觸窗延伸穿過第二鈍化層；第三鈍化層，覆蓋所述第一鈍化層並環繞所述第一接觸窗；模製材料，延伸在所述第一晶粒與所述第二晶粒之間，其中所述模製材料與所述第一鈍化層的側壁、所述第二鈍化層的側壁以及所述第三鈍化層的側壁物理接觸；以及第一絕緣層，覆蓋所述第一晶粒與所述第二晶粒，其中所述 第三鈍化層與所述第一絕緣層物理接觸，且其中所述模製材料分隔所述第二鈍化層與所述第一絕緣層。
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