TW201340196A - 薄化半導體封裝之方法與裝置 - Google Patents

薄化半導體封裝之方法與裝置 Download PDF

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TW201340196A
TW201340196A TW102109771A TW102109771A TW201340196A TW 201340196 A TW201340196 A TW 201340196A TW 102109771 A TW102109771 A TW 102109771A TW 102109771 A TW102109771 A TW 102109771A TW 201340196 A TW201340196 A TW 201340196A
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semiconductor package
polishing
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semiconductor
vacuum
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Gi-Hwan Bae
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Knj Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

本發明有關一種用於拋光半導體封裝的模具表面，薄化半導體封裝以減少半導體封裝厚度之方法與裝置。該裝置包括一平台，用於在該平台上安置一半導體封裝；及一拋光單元，用於拋光該安置在該平台上的半導體封裝。

Description

薄化半導體封裝之方法與裝置
本發明有關一種用於薄化半導體封裝體之方法與裝置，更具體而言，有關一種用於藉由拋光半導體封裝的模具表面，薄化半導體封裝體以減少半導體封裝厚度之方法與裝置。
隨著一最近的半導體製造技術發展，半導體封裝正發展中，包括適合在短暫時間內處理大量資料的半導體器件。
一半導體封裝可視為一種藉由晶粒黏著半導體晶片至一基材墊，諸如一導線架或一印刷電路板(Printed Circuit Board，PCB)；線焊半導體晶片至導線架或印刷電路板(PCB)的端子；然後鑄模該等接合半導體晶片的周圍與使用樹脂複合材料(環氧樹脂複合材料，EMC)的線接所加以製造之封裝，以保護半導體晶片與線接。
圖1與圖2顯示一傳統半導體封裝(100)。請即參考圖1與圖2，一半導體晶片(120)為線焊至一印刷電路板(PCB)(110)，且一模具部件(130)形成在半導體晶片上。半導體晶片(120)包括一晶圓(121)與引線接合件(122)。
不過，半導體封裝需要印刷電路板(PCB)(110)或導線架，用於在堆積半導體晶片與用於保護半導體晶片的模具部件(130)之間的信號溝通，致使增加半導體封裝(100)的整體厚度(t0)。
此一問題造成不容易邁向電子器具縮小化的實現及薄化資訊溝通裝置。
本發明想要解決如上所述的問題，且本發明之一態樣是要提供一種藉由拋光半導體封裝的模具表面以薄化半導體封裝之方法與裝置。
根據本發明之一態樣，一種用於薄化半導體封裝之裝置包括：一平台，該平台上面安置半導體封裝；及一拋光單元，用於拋光安置在該平台上的半導體封裝。
該平台使用一真空孔形成。
該裝置可更包括一真空單元，用於透過該真空孔施加特定真空程度。
該裝置可更包括一供料單元，用於彼此水平移動該平台或該拋光單元。
該拋光單元可包括一拋光輪，用於拋光該半導體封裝；及一 轉軸，用於旋轉該拋光輪。
該拋光輪可拋光該半導體封裝的模具表面。
根據本發明的另一態樣，一種用於薄化半導體封裝之方法包括：安置該半導體封裝在一平台上；及拋光該安置在該平台上的半導體封裝。
安置半導體封裝可包括將該半導體封裝真空抽吸至該平台。
拋光半導體封裝可包括使用一拋光輪以拋光該半導體封裝。
拋光半導體封裝可包括拋光該半導體封裝的模具表面。
拋光半導體封裝可包括當水平往復移動該拋光輪、或該在上面安置半導體封裝的平台時，拋光該半導體封裝。
拋光半導體封裝可包括當水平往復移動該拋光輪或該在上面安置半導體封裝的平台時，可在取得預定拋光量以前，重複拋光該半導體封裝。
拋光半導體封裝可包括根據該拋光輪的寬度，在寬度方向，藉由使半導體封裝分成複數個部分以連續拋光該半導體封裝。
同樣地，根據本發明，方法與裝置可拋光該半導體封裝的該模具表面，藉此減少該半導體封裝的厚度。
此外，方法與裝置可拋光該模具表面以減少該半導體封裝的厚度，藉此改善熱耗散。
1‧‧‧裝置
10‧‧‧平台
11‧‧‧真空槽
12‧‧‧真空孔
20‧‧‧拋光單元
21‧‧‧拋光輪
22‧‧‧轉軸
30‧‧‧供料單元
100‧‧‧傳統半導體封裝
110‧‧‧印刷電路板
120‧‧‧半導體晶片
121‧‧‧晶圓
122‧‧‧引線接合件
130‧‧‧模具部件
本發明的上述及其他特徵可從下面連同附圖的具體實施例詳細描述變得更明白，其中：圖1為一傳統半導體封裝的圖式；圖2為沿著圖1線條A-A的截面圖；圖3與圖4為根據本發明之一具體實施例用於薄化半導體封裝之裝置的圖式；及圖5至圖7為根據本發明之一具體實施例用於薄化半導體封裝之方法的圖式。
本發明的具體實施例現將參考附圖詳細描述。
請即參考圖3與圖4，根據本發明之一具體實施例用於薄化半導體封裝之裝置(1)包括一平台(10)、一供料單元(30)、與一拋光單元(20)。
該平台(10)用來真空抽吸一半導體封裝。該平台有一板狀，該板狀的面積大於該半導體封裝的面積。該平台包括複數個真空槽(11)。該等真空槽之每一者係使用複數個真空孔(12) 形成，其中一真空單元(未在圖顯示)經由連接以施加特定真空程度。
該供料單元(30)可水平往復移動該平台(10)。當保持住平台(10)時，該供料單元(30)可由一驅動單元(未在圖顯示)操作以沿著一導軌往復移動。
該拋光單元(20)包括一拋光輪(21)，用於拋光該半導體封裝；及一轉軸(22)，用於旋轉該拋光輪(21)。
雖然該供料單元(30)在此具體實施例中係示意說明為水平往復移動該平台(10)，但該供料單元可水平往復移動該拋光輪，而不是該平台。該供料單元可採用一傳統器件，諸如一線性導軌(LM GUIDE)、一氣缸等。
然後，用於薄化半導體封裝之裝置的操作將與用於薄化半導體封裝之方法一起描述。
請即參考圖5，一半導體封裝(100)先真空抽吸至該平台(10)，且該拋光輪(21)會根據預定拋光量降低。如此，當該平台(10)水平移動時，該拋光輪(21)可旋轉以拋光該半導體封裝(100)，藉此薄化該半導體封裝。
雖然可進行拋光以達成預定拋光量，但在此情況，該半導體 封裝可能過載。因此，在取得預定拋光量以前，可重複拋光數次。在此情況，當該平台(10)水平往復移動時，可在取得預定拋光量以前，拋光輪(21)可根據一些階段逐漸降低。
請即參考圖6，當該拋光輪(21)的寬度(t1)小於該半導體封裝的寬度(t2)時，該半導體封裝(100)可藉由根據該拋光輪的寬度，使該半導體封裝分成複數個部分以重複拋光。在此情況，除了用於水平往復移動該平台(10)的該供料單元以外，一第二供料單元(未在圖顯示)可個別用來移動垂直於該供料單元的供料方向的該平台(10)或該拋光輪。
請即參考圖7，該半導體封裝(100)為藉由拋光該模具表面以較薄製成。該半導體封裝(100)的拋光厚度(t3)可視需要加以設定。因此，視需要，除了模具部件(130)以外，可拋光該半導體晶片(120)的該晶圓(121)之一部分。
雖然根據本發明的方法與裝置描述有關半導體封裝，包括安裝在印刷電路板上的半導體晶片，但應明白，根據本發明的方法與裝置亦可適用於包括在一導線架上所安裝半導體晶片的半導體封裝。
雖然已描述一些具體實施例，但應明白，這些具體實施例只是說明且未限制本發明的範疇，且熟安此技者可進行各種不同修改與變更，不致悖離本發明的精神與範疇，且只受限於 文後申請專利範圍及其同等物。
1‧‧‧裝置
10‧‧‧平台
20‧‧‧拋光單元
21‧‧‧拋光輪
22‧‧‧轉軸
30‧‧‧供料單元

Claims (13)

  1. 一種用於薄化半導體封裝之裝置，包括：一平台，用於在該平台上安置該半導體封裝；及一拋光單元，用於拋光該安置在該平台上的半導體封裝。
  2. 如申請專利範圍第1項所述之裝置，其中該平台使用一真空孔形成。
  3. 如申請專利範圍第2項所述之裝置，更包括一真空單元，用於透過該真空孔施加特定真空程度。
  4. 如申請專利範圍第1項所述之裝置，更包括一供料單元，用於彼此水平移動該平台或該拋光單元。
  5. 如申請專利範圍第1項所述之裝置，其中該拋光單元包括一拋光輪，用於拋光該半導體封裝；及一轉軸，用於旋轉該拋光輪。
  6. 如申請專利範圍第5項所述之裝置，其中該拋光輪為拋光該半導體封裝的模具表面。
  7. 一種用於薄化半導體封裝之方法，包括：安置該半導體封裝在一平台上；及拋光該安置在該平台上的半導體封裝。
  8. 如申請專利範圍第7項所述之方法，其中該安置半導體 封裝包括將該半導體封裝真空抽吸至該平台。
  9. 如申請專利範圍第7項所述之方法，其中該拋光半導體封裝包括使用一拋光輪以拋光該半導體封裝。
  10. 如申請專利範圍第9項所述之方法，其中該拋光半導體封裝包括拋光該半導體封裝的模具表面。
  11. 如申請專利範圍第9項所述之方法，其中該拋光半導體封裝包括當水平往復移動該拋光輪或該在上面安置半導體封裝的平台時，拋光該半導體封裝。
  12. 如申請專利範圍第11項所述之方法，其中該拋光半導體封裝包括當水平往復移動該拋光輪或該在上面安置半導體封裝的平台時，可在取得預定拋光量以前，重複拋光該半導體封裝。
  13. 如申請專利範圍第11項所述之方法，其中該拋光半導體封裝包括根據該拋光輪的寬度，藉由在寬度方向使該半導體封裝分成複數個部分以連續拋光該半導體封裝。
TW102109771A 2012-03-21 2013-03-20 薄化半導體封裝之方法與裝置 TW201340196A (zh)

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