TW201330268A - 具有不對稱閘極的垂直電晶體 - Google Patents
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- 239000004020 conductor Substances 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000003989 dielectric material Substances 0.000 claims abstract description 11
- 230000005669 field effect Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 32
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 229910002367 SrTiO Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910021193 La 2 O 3 Inorganic materials 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 2
- -1 and Al 2 O. 3 Inorganic materials 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 description 53
- 239000002184 metal Substances 0.000 description 53
- 239000004065 semiconductor Substances 0.000 description 24
- 230000008569 process Effects 0.000 description 15
- 239000013078 crystal Substances 0.000 description 8
- 239000002243 precursor Substances 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 229910001339 C alloy Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QISGROBHHFQWKS-UHFFFAOYSA-N [C].[Nb] Chemical compound [C].[Nb] QISGROBHHFQWKS-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- SITVSCPRJNYAGV-UHFFFAOYSA-L tellurite Chemical compound [O-][Te]([O-])=O SITVSCPRJNYAGV-UHFFFAOYSA-L 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910001362 Ta alloys Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- KCFIHQSTJSCCBR-UHFFFAOYSA-N [C].[Ge] Chemical compound [C].[Ge] KCFIHQSTJSCCBR-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 238000000889 atomisation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- XMHIUKTWLZUKEX-UHFFFAOYSA-N hexacosanoic acid Chemical class CCCCCCCCCCCCCCCCCCCCCCCCCC(O)=O XMHIUKTWLZUKEX-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L29/66409—Unipolar field-effect transistors
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Abstract
形成電晶體結構,該電晶體結構包含基板及於該基板上方之源極、汲極、以及通道,該通道垂直地位於該源極與該汲極之間。該通道耦接至閘極導電體,該閘極導電體經由閘極介電材料層圍繞該通道,該閘極介電材料層圍繞該通道。該閘極導電體係由具有第一功函數的第一導電材料與具有第二功函數的第二導電材料組成,該第一導電材料圍繞該通道之長度之第一部分,該第二導電材料圍繞該通道之該長度之第二部分。亦揭示一種製造該電晶體結構之方法,可將該電晶體結構描繪成一種具有不對稱閘極之垂直場效電晶體。
Description
本發明之例示性實施例大體關於電晶體裝置,更具體而言,係關於不對稱閘極垂直電晶體裝置及其製造方法。
不對稱的電晶體裝置可以提供強化的電流處理並提高輸出電阻。然而,很難製造具有橫向結構且其閘極特性以平行於下方通道的方式改變之不對稱電晶體裝置。
各種垂直通道的電晶體裝置在先前已被提出,舉例來說,可以參考IEEE TRANSACTIONS ON ELECTRON DEVICES 2006年5月第53卷第5期中Enrico Gili、V.Dominik Kunz、Takashi Uchino、Mohammad M.Al Hakim、C.H.de Groot、Peter Ashburn及Stephen Hall的「Asymmetric Gate-Induced Drain Leakage and Body Leakage in Vertical MOSFETS With Reduced Parasitic Capacitance」;以及IEEE TRANSACTIONS ON ELECTRON DEVICES 2003年5月第50卷第5期中Haitao Liu、Zhibin Xiong以及Johnny K.O.Sin的「An U1trathin Vertical Channel MOSFET for Sub-100-nm Applications」。也可以參考2004年2月3日Leo Mathew與Michael Sadd的美國專利第6,686,245號「Vertical MOSFET with Asymmetric Gate structure」。
在本發明之例示性實施例之第一態樣中,本發明之例示性實施例提供一種電晶體結構,該電晶體結構包含基板及於該基板上方之源極、汲極、以及通道,該通道垂直地位於該源極與該汲極之間。該通道耦接至閘極導電體,該閘極導電體經由閘極介電材料層圍繞該通道,該閘極介電材料層圍繞該通道。該閘極導電體係由具有第一功函數的第一導電材料與具有第二功函數的第二導電材料組成,該第一導電材料圍繞該通道之長度之第一部分,該第二導電材料圍繞該通道之該長度之第二部分。
在另外的態樣中,本發明之例示性實施例提供一種製造電晶體結構之方法,該方法包含以下步驟:提供基板;於該基板之表面上形成源極、汲極及通道,該通道垂直地位於該源極與該汲極之間;至少於該通道之側壁上形成閘極介電層;以及形成閘極導電體,該閘極導電體圍繞該通道與該閘極介電層。形成該閘極導電體以包含具有第一功函數的第一導電材料與具有第二功函數的第二導電材料,該第一導電材料圍繞該通道之長度之第一部分,該第二導電材料圍繞該通道之該長度之第二部分。
MOSFET裝置的一個重要參數是閘極的有效功函數
(Φeff),閘極係與閘極介電質接觸。Φeff影響裝置的平帶電壓(Vfb)並因而控制MOSFET的臨界電壓(Vt)。
第1-12圖圖示依據本發明的例示性實施例不對稱閘極、垂直通道電晶體裝置(具體為nFET 50)之製造。
參照第1圖,依據本發明的例示性半導體結構包含半導體基板10與形成於半導體基板10上方的材料層堆疊。半導體基板10具有半導體材料,該半導體材料可選自但不限於矽、鍺、矽鍺合金、矽碳合金、矽鍺碳合金、砷化鎵、砷化銦、磷化銦、III-V族化合物半導體材料、II-VI族化合物半導體材料、有機半導體材料以及其他的化合物半導體材料。典型地,半導體基板10的半導體材料含有矽。
在半導體基板10的半導體材料為單晶的含矽半導體材料之案例中,該單晶的含矽半導體材料較佳係選自單晶矽、單晶矽碳合金、單晶矽鍺合金以及單晶矽鍺碳合金。
半導體基板10的半導體材料可被適當地摻雜p型摻雜原子或是n型摻雜原子中之任一者,或者該材料可以是實質上未摻雜的(本質的)。半導體基板10的摻雜濃度可以從1.0x1015/cm3至1.0x1019/cm3,而且通常是從1.0x1016/cm3至3.0x1018/cm3,雖然本文中亦考量較少或較多的摻雜濃度。半導體基板10可以為單晶而且可為大塊基板、絕緣底半導體(SOI)基板或混成基板。雖然以大塊基板描述本發明,但將本發明實施於SOI基板上或
混成基板上亦為本文所明確考量者。淺溝槽隔離結構(未圖示)可以存在並且可以包含介電材料,如氧化矽或氮化矽,而且可以藉由本技術領域中廣為習知的方法形成。
所描述者為適合用來製造具有不對稱閘極結構的垂直n型場效電晶體(nFET)之製程流程。以某些以下詳述的修改,該製程流程亦可應用於製造p型FET(pFET)。
在基板10上方藉由磊晶生長以原位摻雜(若需要的話)形成複數的層,該複數的層將會在後續被區分(第2圖)為源極接面12、n+ Si源極區14、p型Si通道區16、n+ Si汲極區18,之後再沉積SiO2硬罩(HM)20。源極接面12可以是例如Si基板10的n++摻雜區而且可以具有在約10 nm至約200 nm範圍中的例示性厚度。源極接面12也可以是由接觸區(CA)金屬組成的含金屬層,接觸區金屬如與銅(Cu)層結合的鎢(W),或者接觸區金屬可以只有鎢。n+ Si源極區14可以摻雜n型,例如P或As,且摻雜濃度在約4x1020(及更低)至約5x1020(及更高)的範圍中,而且n+ Si源極區14可以具有在約10 nm至約200 nm範圍中的例示性厚度。p型Si通道區16可以摻雜p型,例如B或Al,且摻雜濃度在約1016(及更低)至約1019(及更高)的範圍中,而且p型Si通道區16可以具有在約10 nm至約40 nm範圍中的例示性厚度。n+ Si汲極區18可以摻雜n型,例如P或As,且摻雜濃度在約4x1020(及更低)至約5x1020(及更高)的範圍中,而且n+ Si汲極區18可以具有在
約10 nm至約200 nm範圍中的例示性厚度。SiO2硬罩(HM)20可以具有在約2 nm至約50 nm範圍中的厚度。
第2圖為進行反應性離子蝕刻(RIE)程序之後材料層堆疊之剖面圖。RIE程序之結果為形成含有一部分n+ Si源極區14、p型Si通道區16、n+ Si汲極區18以及上面的SiO2硬罩20之柱狀物或圓柱。可將該柱狀物或圓柱指稱為最終的電晶體結構30之前驅物,而且該柱狀物或圓柱可以具有任意的直徑,如在約50 nm或更小至約100 nm或更大的範圍中之直徑。如可被理解的,在RIE製程期間可以在基板10上面形成任何需要數量的相同前驅物電晶體結構30。
第3圖為側壁上形成有間隔32之後的前驅物電晶體結構30之剖面圖。該間隔可以例如為SiN,而且可以具有例如約3 nm或更厚的厚度。如以下將被注意的,間隔32是一個犧牲結構而且會在第5圖圖示的製程中被去除。
第4圖圖示進行熱氧化製程之選擇性步驟,該熱氧化製程在n+ Si源極區14的曝露材料上方形成氧化層34(SiO2)。氧化層34可以具有約10 nm及更厚的厚度。形成氧化層34的一個益處在於氧化層34可以發揮降低完成的電晶體之閘極與源極之間的寄生電容之功能。
第5圖圖示去除SiN間隔32之後的結構30。SiN間隔32可藉由化學濕式蝕刻去除,如一者使用熱磷酸(H3PO4)或一者使用氫氟酸(HF)。
注意到假使未使用氧化層34,則可將第3、4及5圖中圖示的處理視為選擇性的。
第6圖圖示進行形成閘極介電層36的製程之結果。可以使用任何適當的閘極介電材料,包括SiO2或SiON(氮氧化矽),然而,較佳可使用高介電常數材料(高k材料),如包含介電金屬氧化物者,該介電金屬氧化物具有大於氮化矽的介電常數(7.5)之介電常數。高k介電層36可藉由習知的方法形成,如化學氧相沉積(CVD)、原子層沉積(ALD)、分子束沉積(MBD)、脈衝雷射沉積(PLD)、液態源霧化化學沉積(LSMCD)等。該介電金屬氧化物包含金屬與氧以及選擇性的氮及/或矽。例示性的高k介電材料包括HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、以上材料之矽酸鹽以及以上材料之合金。每個x值係獨立為從0.5至3而且每個y值係獨立為從0至2。高k閘極介電層36的厚度可以從1 nm至10 nm而且可具有在約5 Å等級或更厚的有效氧化厚度(EOT)。
第7圖至第11圖圖示依據本發明的實施例在垂直配置的通道16附近形成不對稱閘極,通道16具有等於p Si層16的厚度之通道長度(例如在約10 nm至約40 nm的範圍中),其中通道長度尺寸與基板10的表面垂直。在圖示的實施例中,約50%的通道長度被第一金屬閘極導電材料層38圍繞,而且剩餘的約50%通道長度係被第二
金屬閘極導電材料層40圍繞,其中第一金屬閘極導電材料層38具有比第二金屬閘極導電材料層40更高的功函數(WF)。作為實例,第一金屬閘極導電材料層38之WF可為約5.1 eV,而第二金屬閘極導電材料層40之WF可為約4.1 eV。作為非限制性實例,第一金屬閘極導電材料層38可由W組成,而第二金屬閘極導電材料層40可由TiN或Al組成,每個係使用電漿蒸汽沉積(PVD)或ALD或CVD所沉積。在本文繪示的nFET實施例中,具有較高WF的金屬閘極導電材料係位於較接近源極之處,而具有較低WF的金屬閘極導電材料係位於較接近汲極之處。在pFET實施例中,除了改變摻雜類型之外,亦顛倒閘極金屬的順序,使得具有較高WF的金屬閘極導電材料位於較接近汲極之處,而具有較低WF的金屬閘極導電材料係位於較接近源極之處。注意到,在其他實施例中,可以調整具有較高WF的金屬閘極導電材料與具有較低WF的金屬閘極導電材料之50-50通道覆蓋比例,以便成為非50-50覆蓋比例。在所有的實施例中,通道的全部長度皆被具有較高WF的金屬閘極導電材料與具有較低WF的金屬閘極導電材料圍繞是理想的。
至少由於存在具有至少二個不同的功函數且位於沿著通道的長度之不同的空間位置的閘極導電體,閘極被視為是不對稱的。
應理解到,雖然本文中描述為使用二個不同類型的閘極導電材料而且每個具有相關的且不同的功函數,本發
明的實施例也涵蓋使用二個以上不同類型的閘極導電體材料,且每個具有相關的且不同的功函數。
根據前述,第7圖圖示毯式沉積第一金屬閘極導電材料層38(在本實例中具有較高的WF)於閘極介電質36上方之結果。
第8圖圖示從前驅物電晶體結構的側壁選擇性去除第一金屬閘極導電材料層38之結果。此步驟亦減少第一金屬閘極導電材料層38的厚度,使得第一金屬閘極導電材料層38圍繞大約50%的p-Si通道層16之厚度(即第一金屬閘極導電材料層38圍繞約50%的垂直通道長度)。
第9圖圖示毯式沉積第二金屬閘極導電材料層40(在本實例中具有較低的WF)於剩餘的第一金屬閘極導電材料層38上方且於閘極介電質36的上曝露部分上方之結果。
第10圖圖示進行化學機械研磨(CMP)製程之結果。位於HM 20上方的閘極介電材料層36功能是作為CMP製程之阻擋層。
第11圖圖示進行金屬閘極凹部蝕刻製程(例如反應性離子蝕刻(RIE)製程)之結果,該金屬閘極凹部蝕刻製程用以減少第二金屬閘極導電材料層40的厚度,使得第二金屬閘極導電材料層40至少覆蓋並圍繞p型Si通道層16的上部(即第二金屬閘極導電材料層38圍繞剩餘50%的垂直通道長度)。結果,表面上下方50%的通道層16厚度被第一金屬閘極導電材料層38圍繞,而表面上
上方50%的通道層16厚度被第二金屬閘極導電材料層40圍繞。
第12圖圖示進行未摻雜矽酸鹽玻璃(USG)處理、圖形化以及通孔形成以製造閘極接點44A與汲極接點44B的結果,形成了nFET電晶體結構50。也形成了源極接點(未圖示)來接觸源極接面層12。作為非限制性實例,層42可以是由SiN組成之介電層,而閘極與汲極接點44A、44B可以是W或W與Cu的組合。閘極接點區金屬可以僅是Cu,而汲極接點區金屬可以是W,該W位於Cu層下方,以將Cu與半導體材料物理性隔離。閘極接點44A與第二金屬閘極導電材料層40電連接,第二金屬閘極導電材料層40接著與第一金屬閘極導電材料層38電連接。
第13圖(由圖13A與圖13B組成)圖示與沿著通道的長度具有單一功函數閘極導電體的習知裝置(指稱為H閘極)相比,依據本發明的實施例之不對稱閘極裝置(指稱為HL閘極)在通道中的源極注入區具有較高的電場。
第14圖圖示與沿著通道的長度(例如32 nm)具有均勻單一功函數閘極導電體的H閘極相比,在HL閘極裝置的裝置效能上有約15%-20%的改良。
應指出,源極與汲極的位置可以顛倒(即汲極在裝置底部而源極在裝置頂部)。假使源極與汲極的位置顛倒了,則亦顛倒功函數金屬,以例如對於nFET實施例在
接近源極側具有高的功函數金屬,而且在接近汲極側具有低的功函數金屬。
亦應指出,源極與汲極的厚度不需要相同。
本文中使用的命名只是為了描述特定實施例的目的,而且非意圖為本發明之限制。除非內文以其他方式清楚指明,否則本文中使用的單數形「一」及「該」亦意圖包括複數形。應進一步瞭解到,用語「包含」當用於本說明書中時係明確說明所述特徵、整數、步驟、操作、元件及/或成分之存在,但不排除一或多個其他特徵、整數、步驟、操作、元件、成分及/或基團之存在或添加。
本說明書中相關的結構、材料、動作以及均等物係意圖包括例如任何結構、材料、層厚度與層組成、特徵尺寸以及處理模式(例如蝕刻模式),以與其他具體主張的要求元件組合而執行功能。已經為了說明與描述的目的呈現本發明之描述,但本發明之描述在所揭示的形式中並非意圖為詳盡無遺的或為對本發明之限制。對於本技術領域中具有通常知識者而言,在不偏離本發明的範圍與精神下,許多的修飾與變化都將是顯而易見的。舉例來說,各種的材料、厚度、功函數以及製造設備與技術都是非限制性實例,而且可以與本文中具體揭示者不同。選擇該等實施例並描述之,以最佳地說明本發明之原則與實際應用,並使其他本技術領域中具有通常知識者能夠瞭解本發明,因為各種具有各式各樣修飾的實施例都是適合考量的特定使用。
如此一來,對本技術領域中具有通常知識者而言,鑒於以上描述並連同附圖與附加的申請專利範圍一起研讀時,各種修飾與適用可變為顯而易見的。但對於一些實例,本技術領域中具有通常知識者可使用其他類似或均等的數學表示。然而,所有這種對於本發明的教示之類似修飾仍將落入本發明之範圍內。
10‧‧‧基板
12‧‧‧源極接面
14‧‧‧n+ Si源極區
16‧‧‧p型Si通道區
18‧‧‧n+ Si汲極區
20‧‧‧SiO2硬罩(HM)
30‧‧‧電晶體結構
32‧‧‧間隔
34‧‧‧氧化層
36‧‧‧介電層
38‧‧‧第一金屬閘極導電材料層
40‧‧‧第二金屬閘極導電材料層
42‧‧‧層
44A‧‧‧閘極接點
44B‧‧‧汲極接點
50‧‧‧nFET電晶體結構
第1至12圖各為圖示本發明的實施例之放大剖面圖,其中各個層厚度及其他元件未依比例繪製,其中:第1圖圖示包含半導體基板及形成於半導體基板上的材料層堆疊之例示性半導體結構;第2圖圖示在進行反應性離子蝕刻程序以形成前驅物電晶體結構之後之材料層堆疊,該前驅物電晶體結構具有位於源極層與汲極層之間的通道層;第3圖圖示在前驅物電晶體結構之側壁上形成間隔之後之前驅物電晶體結構;第4圖圖示進行熱氧化製程之選擇性步驟,該熱氧化製程於源極區之曝露材料上形成氧化層;第5圖圖示去除第3圖中形成的間隔之後之結構;第6圖圖示製程的結果為形成閘極介電層;第7圖圖示於閘極介電層上毯式沉積第一金屬閘極導電材料層(具有第一功函數)之結果;
第8圖圖示選擇性從該前驅物電晶體結構之側壁去除該第一金屬閘極導電材料層之結果,使得該第一金屬閘極導電材料層至少覆蓋並圍繞該通道層之下部;第9圖圖示於剩餘的第一金屬閘極導電材料層上與該閘極介電層之上方曝露部分上毯式沉積第二金屬閘極導電材料層(具有第二、不同的功函數)之結果;第10圖圖示實施化學機械研磨製程之結果;第11圖圖示金屬閘極凹部蝕刻製程之結果,該金屬閘極凹部蝕刻製程減少該第二金屬閘極導電材料層之厚度,使得該第二金屬閘極導電材料層至少覆蓋並圍繞該通道層之上部;以及第12圖圖示進行未摻雜矽酸鹽玻璃製程、圖形化以及通孔形成以製造閘極觸點與汲極觸點之結果所形成之nFET電晶體結構。
第13A圖及第13B圖為圖示與沿著通道的長度具有單一功函數閘極導電體的習知裝置(指稱為H閘極)相比,依據本發明的實施例之不對稱閘極裝置(指稱為HL閘極)在通道中的源極注入區具有較高的電場之圖。
第14圖為圖示與沿著通道的長度具有均勻單一功函數閘極導電體的習知H閘極裝置相比,在HL閘極裝置的裝置效能上有約15%-20%的改良之圖。
10‧‧‧基板
12‧‧‧源極接面
14‧‧‧n+ Si源極區
16‧‧‧p型Si通道區
18‧‧‧n+ Si汲極區
20‧‧‧SiO2硬罩(HM)
Claims (15)
- 一種電晶體結構,包含:一基板,及於該基板上方之一源極;一汲極;以及一通道,該通道垂直地位於該源極與該汲極之間並耦接至一閘極導電體,該閘極導電體經由一閘極介電材料層圍繞該通道,該閘極介電材料層圍繞該通道,其中該閘極導電體係由具有一第一功函數的一第一導電材料與具有一第二功函數的一第二導電材料組成,該第一導電材料圍繞該通道之一長度之一第一部分,該第二導電材料圍繞該通道之該長度之一第二部分。
- 如請求項1所述之電晶體結構,其中該長度之該第一部分與該第二部分各約為該通道之該長度之50%。
- 如請求項1所述之電晶體結構,其中該第一功函數為約5.1 eV,以及其中該第二功函數為約4.1 eV。
- 如請求項1所述之電晶體結構,其中該電晶體為一n型場效電晶體,以及其中該第一閘極導電體之一功函數大於該第二閘極導電體之一功函數,且該第一閘極導電體比該第二閘極導電體位於較靠近該源極處。
- 如請求項1所述之電晶體結構,其中該電晶體為一p型場效電晶體,以及其中該第一閘極導電體之一功函數大於該第二閘極導電體之一功函數,且該第一閘極導電體比該第二閘極導電體位於較靠近該汲極處。
- 如請求項1所述之電晶體結構,其中該閘極介電材料係由SiO2或SiON組成。
- 如請求項1所述之電晶體結構,其中該閘極介電材料係由一高介電常數材料組成,該高介電常數材料係由HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、以上材料之矽酸鹽以及以上材料之合金中之至少一者所組成,其中每個x值係獨立為從0.5至3而且每個y值係獨立為從0至2。
- 如請求項1所述之電晶體結構,其中該通道之該長度為約40 nm或更小;或其中具有該第一功函數之該導電材料係由鎢組成,以及其中該第二導電材料係由氮化鎢或鋁中之一者組成;或其中該源極係位於該基板上方且進一步包含一源極接面 層,該源極接面層夾置於該源極與該基板之間。
- 一種製造一電晶體結構之方法,該方法包含以下步驟:提供一基板;於該基板之一表面上形成一源極、一汲極及一通道,該通道垂直地位於該源極與該汲極之間;至少於該通道之側壁上形成一閘極介電層;以及形成一閘極導電體,該閘極導電體圍繞該通道與該閘極介電層,其中形成該閘極導電體以包含具有一第一功函數的一第一導電材料與具有一第二功函數的一第二導電材料,該第一導電材料圍繞該通道之一長度之一第一部分,該第二導電材料圍繞該通道之該長度之一第二部分。
- 如請求項11所述之方法,其中該長度之該第一部分與該第二部分各約為該通道之該長度之50%。
- 如請求項11所述之方法,其中該第一功函數為約5.1 eV,以及其中該第二功函數為約4.1 eV。
- 如請求項11所述之方法,其中該電晶體為一n型場效電晶體,以及其中該第一閘極導電體之一功函數大於該第二閘極導電體之一功函數,且該第一閘極導電體比 該第二閘極導電體位於較靠近該源極處;或其中該電晶體為一p型場效電晶體,以及其中該第一閘極導電體之一功函數大於該第二閘極導電體之一功函數,且該第一閘極導電體比該第二閘極導電體位於較靠近該汲極處。
- 如請求項11所述之方法,其中形成該閘極介電材料為由SiO2或SiON組成。
- 如請求項11所述之方法,其中形成該閘極介電材料為由一高介電常數材料組成,該高介電常數材料係由HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、以上材料之矽酸鹽以及以上材料之合金中之至少一者所組成,其中每個x值係獨立為從0.5至3而且每個y值係獨立為從0至2。
- 如請求項11所述之方法,其中該通道之該長度為約40 nm或更小;或其中具有該第一功函數之該導電材料係由鎢組成,以及其中該第二導電材料係由氮化鎢或鋁中之一者組成;或 其中該源極係位於該基板上方且進一步包含形成一源極接面層之一初始步驟,以使該源極接面層夾置於該源極與該基板之間。
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US13/271,812 US8866214B2 (en) | 2011-10-12 | 2011-10-12 | Vertical transistor having an asymmetric gate |
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Also Published As
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WO2013054212A1 (en) | 2013-04-18 |
US8866214B2 (en) | 2014-10-21 |
CN103843120A (zh) | 2014-06-04 |
US20130095623A1 (en) | 2013-04-18 |
US9142660B2 (en) | 2015-09-22 |
US20130093000A1 (en) | 2013-04-18 |
CN103843120B (zh) | 2016-12-14 |
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