US10998414B2 - Metal gate structure with multi-layer composition - Google Patents
Metal gate structure with multi-layer composition Download PDFInfo
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- US10998414B2 US10998414B2 US15/619,103 US201715619103A US10998414B2 US 10998414 B2 US10998414 B2 US 10998414B2 US 201715619103 A US201715619103 A US 201715619103A US 10998414 B2 US10998414 B2 US 10998414B2
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- a field-effect transistor such as a metal-oxide-semiconductor field-effect transistors (MOSFETs).
- FET field-effect transistor
- MOSFETs metal-oxide-semiconductor field-effect transistors
- Metal gate stacks are often planarized, such as by chemical-mechanical polishing (CMP), and it is common to have the resulting gate height after CMP be relatively short. This can result in undesired consequences, such as increased defects (e.g., hump defects) and poor on/off (Ion/Ioff) device performance. Therefore, a structure of a metal gate stack and a method making the same are needed to address the issues identified above.
- CMP chemical-mechanical polishing
- FIGS. 1 and 3 are a flowchart of a method for making a semiconductor device having a metal gate stack constructed according to various aspects of the present disclosure.
- FIGS. 2 and 4 are sectional views of a semiconductor device having a metal gate stack at various fabrication stages constructed according to various aspects of the present disclosure in one or more embodiments.
- first and second features are formed in direct contact
- additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
- FIG. 1 is a flowchart of one embodiment of a dummy-gate method 100 for use in making a semiconductor device having a gate stack constructed according to aspects of the present disclosure.
- FIG. 2 provides a sectional view of one embodiment of a semiconductor structure 200 having a gate stack at various fabrication stages. The semiconductor structure 200 and the method 100 of making the same are collectively described with reference to FIGS. 1 and 2 . It is understood that a dummy gate (or gate-last) process is described as an exemplary embodiment, which is not intended to be limiting except and unless as explicitly recited in the claims.
- the method 100 begins at step 102 by providing a semiconductor substrate 202 .
- the semiconductor substrate 202 includes silicon.
- the substrate 202 includes germanium or silicon germanium.
- the substrate 202 may use another semiconductor material such as diamond, silicon carbide, gallium arsenic, GaAsP, AlInAs, AlGaAs, GaInP, or other proper combination thereof.
- the semiconductor substrate also includes various doped regions such as n-well and p-wells formed by a proper technique, such as ion implantation.
- the semiconductor substrate 202 also includes various isolation features, such as shallow trench isolation (STI) 204 , formed in the substrate to separate various devices.
- the formation of the STI may include etching a trench in a substrate and filling the trench by insulator materials such as silicon oxide, silicon nitride, or silicon oxynitride.
- the filled trench may have a multi-layer structure such as a thermal oxide liner layer with silicon nitride filling the trench.
- the STI structure may be created using a process sequence such as: growing a pad oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning an STI opening using photoresist and masking, etching a trench in the substrate, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with CVD oxide, and using chemical mechanical planarization (CMP) to polish and planarize.
- LPCVD low pressure chemical vapor deposition
- CMP chemical mechanical planarization
- a high k dielectric material layer 212 is formed on the semiconductor substrate 202 .
- the high-k dielectric layer 212 includes a dielectric material having the dielectric constant higher than that of thermal silicon oxide, about 3.9.
- the high k dielectric material layer 212 is formed by a suitable process such as ALD.
- Other methods to form the high k dielectric material layer include metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), UV-Ozone Oxidation or molecular beam epitaxy (MBE).
- the high k dielectric material includes HfO 2 .
- the high k dielectric material layer includes metal nitrides, metal silicates or other metal oxides.
- an interfacial layer may be formed between the high-k dielectric material layer 212 and the substrate 202 .
- a polysilicon layer 220 is formed above the high-k dielectric material layer 212 .
- the polysilicon layer 220 is formed by a proper technique, such as CVD.
- the polysilicon layer 220 is non-doped.
- the polysilicon layer 220 has a thickness between about 500 angstrom and about 1000 angstrom.
- the polysilicon layer 220 is patterned, as shown in FIG. 2 . Patterning the polysilicon layer 220 can be performed in various manners, such as by using a patterned mask, followed by an etch process. In the present embodiment, the gate dielectric 212 is also patterned. As a result, a dummy gate is formed, as shown in FIG. 2 .
- step 104 in which source and drain features 206 are formed in the substrate 202 .
- a gate spacer 214 is formed on the sidewalls of the dummy gate 220 .
- the gate spacer 214 includes one or more dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or combinations thereof.
- the source and drain 206 include doping species introduced to the semiconductor substrate 202 by a proper technique, such as ion implantation.
- the gate stack is configured in the active region for an n-type field effect transistor (nFET), and the dopant of the source and drain is n-type dopant, such as phosphorus or arsenic.
- nFET n-type field effect transistor
- the gate stack is configured in the active region for a p-type field effect transistor (pFET), and the dopant of the source and drain is p-type dopant, such as boron or gallium.
- the source and drain 206 include light doped drain (LDD) and heavily doped features, as shown in FIG. 2 .
- the method 100 proceeds to step 106 by forming an interlayer dielectric (ILD) 230 on the substrate.
- the ILD 230 is deposited by a proper technique, such as CVD.
- the ILD 230 includes a dielectric material, such as silicon oxide, low k dielectric material or a combination.
- a chemical mechanical polishing (CMP) process may be applied thereafter to planarize the surface of the ILD 230 .
- the method 100 proceeds to step 108 by removing the polysilicon layer 220 , resulting a gate trench.
- the polysilicon is removed by a suitable etching process, such as wet etch.
- a metal gate stack is formed in the gate trench, which is discussed in greater detail below with reference to FIGS. 3 and 4 .
- forming the metal gate stack begins at step 112 by forming a first metal layer 402 having a proper work function.
- the first metal is also referred to as work function metal.
- the first metal 402 has a work function substantially equals to or less than about 4.4 eV, referred to as n metal.
- the first metal 402 has a work function substantially equals to or greater than about 4.8 eV, referred to as p metal.
- NWF n metal work function
- the p metal includes tantalum or titanium aluminum.
- the p metal includes titanium nitride or tantalum nitride.
- the work function metal 402 is deposited by a suitable technique. In the present embodiment, the NWF is deposited by PVD.
- a blocking layer 404 is formed above the work function metal.
- the blocking layer is a TiN layer.
- the TiN layer is titanium-rich, meaning that Ti/N >1.
- the TiN is deposited by PVD.
- a fill metal material 420 is deposited in the trench, above the blocking layer 404 .
- the fill metal material 420 includes aluminum, although it is understood that other embodiments may be provided, such as aluminum copper alloy.
- the fill metal material 420 is deposited by a suitable technique, such as PVD or plating.
- the metal gate is planarized. In one embodiment, a CMP process is applied to remove the excessive metals, including any metals disposed on the ILD 230 .
- the combination of the layers 402 , 404 , and 420 form a replacement metal gate for the trench left over from the polysilicon dummy gate 220 ( FIG. 2 ). It is understood that additional layers may also be included in the replacement metal gate.
- a capping layer is formed over the replacement metal gate.
- a non-silane oxide layer 425 is deposited on the replacement metal gate, such as by chemical vapor deposition (CVD) or atomic layer deposition (ALD).
- a second ILD 430 is formed on the substrate.
- the ILD 430 is deposited by a proper technique, such as CVD or spin-on glass.
- the ILD 430 includes a dielectric material, such as silicon oxide, low k dielectric material or a combination.
- a chemical mechanical polishing (CMP) process may be applied thereafter to planarize the surface of the ILD 430 .
- an interconnect structure is formed on the substrate and is designed to couple various transistors and other devices to form a functional circuit.
- the interconnect structure includes various conductive features, such as metal lines for horizontal connections and contacts/vias for vertical connections.
- the various interconnect features may implement various conductive materials including copper, tungsten and silicide.
- a damascene process is used to form copper-based multilayer interconnect structure.
- tungsten is used to form tungsten plug in the contact holes.
- the semiconductor structure 200 includes a filed effect transistor, such as a metal-oxide-silicon (MOS) transistor, and may be extended to other integrated circuit having a metal gate stack.
- the semiconductor structure 200 may include a dynamic random access memory (DRAM) cell, a single electron transistor (SET), and/or other microelectronic devices (collectively referred to herein as microelectronic devices).
- the semiconductor structure 200 includes FinFET transistors.
- aspects of the present disclosure are also applicable and/or readily adaptable to other type of transistor, including single-gate transistors, double-gate transistors and other multiple-gate transistors, and may be employed in many different applications, including sensor cells, memory cells, logic cells, and others.
- the gate electrode may alternatively or additionally include other suitable metal.
- the footing procedure may implement other effective cleaning procedure.
- the disclosed method is used to but not limited to form one transistor, such as an n-type metal-oxide-semiconductor field-effect-transistor (nMOSFET).
- nMOSFET n-type metal-oxide-semiconductor field-effect-transistor
- nMOSFETs and pMOSFETs are formed in the same substrate, the nMOSFETs and pMOSFETs are formed in a collective procedure where some features are respectively formed.
- the n metal is formed in the nMOSFET regions while pMOSFET regions are covered from the deposition of n metal.
- the semiconductor substrate may include an epitaxial layer.
- the substrate may have an epitaxial layer overlying a bulk semiconductor.
- the substrate may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer.
- SOI semiconductor-on-insulator
- the substrate may include a buried dielectric layer such as a buried oxide (BOX) layer, such as that formed by a method referred to as separation by implantation of oxygen (SIMOX) technology, wafer bonding, selective epitaxial growth (SEG), or other proper method.
- SOI semiconductor-on-insulator
- BOX buried oxide
- SIMOX separation by implantation of oxygen
- SEG selective epitaxial growth
- the present disclosure describes a semiconductor structure.
- the semiconductor structure includes a semiconductor substrate and a gate stack disposed on the semiconductor substrate.
- the gate stack includes a high-k dielectric material layer, a titanium-rich TiN layer over the high-k dielectric layer, and a metal layer disposed over the titanium-rich TiN layer.
- the metal layer includes aluminum.
- the present disclosure also describes another semiconductor structure, including a semiconductor substrate and a gate stack disposed on the semiconductor substrate.
- the gate stack in this embodiment includes a high-k dielectric material layer, a metal layer disposed over the high-k dielectric material layer, and a non-silane based oxide capping the metal layer.
- the metal layer includes aluminum.
- the present disclosure also describes a method of forming a semiconductor structure.
- the method includes forming a working function layer over the semiconductor substrate, forming a titanium-rich TiN layer over the working function layer, and forming a metal gate structure over the titanium-rich TiN layer.
- the metal gate includes aluminum.
- the method includes forming a capping layer over the metal gate structure; the capping layer formed using a non-silane oxide process.
Abstract
Description
TEOS+O2 w/i HF plasma=>SiO2 (1)
SAM24+O2 w/i HF plasma=>SiO2 (2)
Equation (1) is an example of plasma-enhanced TEOS, and equation (2) is an example of ALD oxide.
Claims (20)
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US8890262B2 (en) | 2012-11-29 | 2014-11-18 | Globalfoundries Inc. | Semiconductor device having a metal gate recess |
CN106531618B (en) | 2015-09-15 | 2021-05-18 | 联华电子股份有限公司 | Work function adjusting method for semiconductor element with metal gate structure |
US10658486B2 (en) * | 2017-05-18 | 2020-05-19 | Taiwan Semiconductor Manufacutring Co., Ltd. | Mitigation of time dependent dielectric breakdown |
US10559676B2 (en) | 2018-04-23 | 2020-02-11 | International Business Machines Corporation | Vertical FET with differential top spacer |
Citations (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6054355A (en) | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
US20030022422A1 (en) | 2001-07-27 | 2003-01-30 | Kazuyoshi Torii | Semiconductor device and its manufacturing method |
US20060163630A1 (en) | 2005-01-13 | 2006-07-27 | International Business Machines Corporation | TiC as a thermally stable p-metal carbide on high k SiO2 gate stacks |
KR20070078975A (en) | 2006-01-31 | 2007-08-03 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US20080081104A1 (en) * | 2006-09-28 | 2008-04-03 | Kazuhide Hasebe | Film formation method and apparatus for forming silicon oxide film |
JP2008511176A (en) | 2004-08-24 | 2008-04-10 | マイクロン テクノロジー インコーポレイテッド | Method for manufacturing a storage gate pixel structure |
US20100052075A1 (en) * | 2008-08-26 | 2010-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating a first contact structure in a gate last process |
US20100155860A1 (en) * | 2008-12-24 | 2010-06-24 | Texas Instruments Incorporated | Two step method to create a gate electrode using a physical vapor deposited layer and a chemical vapor deposited layer |
US20110140206A1 (en) | 2009-07-27 | 2011-06-16 | United Microelectronics Corp. | Semiconductor device |
US20110221012A1 (en) | 2010-03-11 | 2011-09-15 | International Business Machines Corporation | High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof |
US20110223774A1 (en) * | 2010-03-09 | 2011-09-15 | Applied Materials, Inc. | REDUCED PATTERN LOADING USING BIS(DIETHYLAMINO)SILANE (C8H22N2Si) AS SILICON PRECURSOR |
US20110221009A1 (en) * | 2010-03-10 | 2011-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for reducing gate resistance |
US20110241130A1 (en) * | 2010-04-02 | 2011-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a blocking structure and method of manufacturing the same |
US20120052641A1 (en) | 2010-09-01 | 2012-03-01 | Hye-Lan Lee | Methods of Manufacturing MOS Transistors |
US20120211844A1 (en) * | 2011-02-17 | 2012-08-23 | Globalfoundries Inc. | Semiconductor Device Comprising Self-Aligned Contact Elements and a Replacement Gate Electrode Structure |
CN102903741A (en) | 2011-07-28 | 2013-01-30 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing the same |
US20130078792A1 (en) | 2011-09-28 | 2013-03-28 | Pong-Wey Huang | Semiconductor process |
US20130087856A1 (en) * | 2011-10-05 | 2013-04-11 | International Business Machines Corporation | Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate |
US20130130405A1 (en) * | 2011-11-23 | 2013-05-23 | Steven Verhaverbeke | Apparatus and methods for silicon oxide cvd resist planarization |
US20130161754A1 (en) | 2011-12-21 | 2013-06-27 | Hao Su | Semiconductor device and fabricating method thereof |
US20130200393A1 (en) | 2012-02-08 | 2013-08-08 | Chieh-Te Chen | Semiconductor structure and process thereof |
US20130224927A1 (en) * | 2012-02-29 | 2013-08-29 | Globalfoundries Inc. | Methods for fabricating integrated circuits with narrow, metal filled openings |
US20130249010A1 (en) | 2012-03-20 | 2013-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") | Metal gate semiconductor device |
US20130264652A1 (en) | 2012-04-05 | 2013-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cost-Effective Gate Replacement Process |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8294202B2 (en) * | 2009-07-08 | 2012-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate structure of a semiconductor device |
US9263566B2 (en) * | 2011-07-19 | 2016-02-16 | Semiconductor Manufacturing International (Beijing) Corporation | Semiconductor device and manufacturing method thereof |
-
2013
- 2013-04-26 US US13/871,555 patent/US9679984B2/en active Active
- 2013-07-04 CN CN201310279559.8A patent/CN103811538B/en active Active
- 2013-08-22 KR KR1020130099621A patent/KR20140059120A/en active Application Filing
-
2016
- 2016-02-26 KR KR1020160023494A patent/KR101761054B1/en active IP Right Grant
-
2017
- 2017-06-09 US US15/619,103 patent/US10998414B2/en active Active
Patent Citations (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6054355A (en) | 1997-06-30 | 2000-04-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device which includes forming a dummy gate |
US20030022422A1 (en) | 2001-07-27 | 2003-01-30 | Kazuyoshi Torii | Semiconductor device and its manufacturing method |
JP2008511176A (en) | 2004-08-24 | 2008-04-10 | マイクロン テクノロジー インコーポレイテッド | Method for manufacturing a storage gate pixel structure |
US20060163630A1 (en) | 2005-01-13 | 2006-07-27 | International Business Machines Corporation | TiC as a thermally stable p-metal carbide on high k SiO2 gate stacks |
KR20070078975A (en) | 2006-01-31 | 2007-08-03 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US20080081104A1 (en) * | 2006-09-28 | 2008-04-03 | Kazuhide Hasebe | Film formation method and apparatus for forming silicon oxide film |
US20100052075A1 (en) * | 2008-08-26 | 2010-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrating a first contact structure in a gate last process |
US20100155860A1 (en) * | 2008-12-24 | 2010-06-24 | Texas Instruments Incorporated | Two step method to create a gate electrode using a physical vapor deposited layer and a chemical vapor deposited layer |
US20110140206A1 (en) | 2009-07-27 | 2011-06-16 | United Microelectronics Corp. | Semiconductor device |
US20110223774A1 (en) * | 2010-03-09 | 2011-09-15 | Applied Materials, Inc. | REDUCED PATTERN LOADING USING BIS(DIETHYLAMINO)SILANE (C8H22N2Si) AS SILICON PRECURSOR |
US20110221009A1 (en) * | 2010-03-10 | 2011-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for reducing gate resistance |
US20110221012A1 (en) | 2010-03-11 | 2011-09-15 | International Business Machines Corporation | High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof |
US20110241130A1 (en) * | 2010-04-02 | 2011-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a blocking structure and method of manufacturing the same |
US20120052641A1 (en) | 2010-09-01 | 2012-03-01 | Hye-Lan Lee | Methods of Manufacturing MOS Transistors |
US20120211844A1 (en) * | 2011-02-17 | 2012-08-23 | Globalfoundries Inc. | Semiconductor Device Comprising Self-Aligned Contact Elements and a Replacement Gate Electrode Structure |
CN102903741A (en) | 2011-07-28 | 2013-01-30 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing the same |
US20130026578A1 (en) * | 2011-07-28 | 2013-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing the same |
US20130078792A1 (en) | 2011-09-28 | 2013-03-28 | Pong-Wey Huang | Semiconductor process |
US20130087856A1 (en) * | 2011-10-05 | 2013-04-11 | International Business Machines Corporation | Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate |
US20130130405A1 (en) * | 2011-11-23 | 2013-05-23 | Steven Verhaverbeke | Apparatus and methods for silicon oxide cvd resist planarization |
US20130161754A1 (en) | 2011-12-21 | 2013-06-27 | Hao Su | Semiconductor device and fabricating method thereof |
US20130200393A1 (en) | 2012-02-08 | 2013-08-08 | Chieh-Te Chen | Semiconductor structure and process thereof |
US20130224927A1 (en) * | 2012-02-29 | 2013-08-29 | Globalfoundries Inc. | Methods for fabricating integrated circuits with narrow, metal filled openings |
US8652890B2 (en) | 2012-02-29 | 2014-02-18 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits with narrow, metal filled openings |
US20130249010A1 (en) | 2012-03-20 | 2013-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") | Metal gate semiconductor device |
US20130264652A1 (en) | 2012-04-05 | 2013-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cost-Effective Gate Replacement Process |
Non-Patent Citations (1)
Title |
---|
National Center for Biotechnology Information. PubChem Compound Database; CID=6517, http://pubchem.ncbi.nlm.nih.gov/compund/6517 (accessed Jan. 26, 2015). * |
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CN103811538A (en) | 2014-05-21 |
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US20170278941A1 (en) | 2017-09-28 |
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