TW201301417A - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

Info

Publication number
TW201301417A
TW201301417A TW101116085A TW101116085A TW201301417A TW 201301417 A TW201301417 A TW 201301417A TW 101116085 A TW101116085 A TW 101116085A TW 101116085 A TW101116085 A TW 101116085A TW 201301417 A TW201301417 A TW 201301417A
Authority
TW
Taiwan
Prior art keywords
ball
gas
semiconductor device
ball forming
manufacturing
Prior art date
Application number
TW101116085A
Other languages
English (en)
Inventor
Masahiko Sekihara
Masaki Furukawa
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW201301417A publication Critical patent/TW201301417A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/002Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
    • B23K20/004Wire welding
    • B23K20/005Capillary welding
    • B23K20/007Ball bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/43Manufacturing methods
    • H01L2224/438Post-treatment of the connector
    • H01L2224/4383Reworking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48799Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/781Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/78268Discharge electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8503Reshaping, e.g. forming the ball or the wedge of the wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8503Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85045Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85053Bonding environment
    • H01L2224/85054Composition of the atmosphere
    • H01L2224/85065Composition of the atmosphere being reducing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85053Bonding environment
    • H01L2224/85054Composition of the atmosphere
    • H01L2224/85075Composition of the atmosphere being inert
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518Translational movements
    • H01L2224/85181Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00015Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/1016Shape being a cuboid
    • H01L2924/10162Shape being a cuboid with a square active surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本發明提供一種於使用易被氧化之導電性導線形成初始滾珠,並將該初始滾珠壓附於焊墊上而形成壓接滾珠之技術中,藉由抑制初始滾珠之形狀不良而可降低對焊墊之損害的技術。於滾珠形成單元BFU中設置排出抗氧化氣體之氣體排出部GOP,將該氣體排出部GOP之排出路徑設置於與將抗氧化氣體導入至滾珠形成部BFP之方向不同之方向上。藉此,可使排出抗氧化氣體之區域增加,故而可抑制自滾珠形成部BFP之一側面側供給之氣流於對向之另一方之側面使氣流反射而形成亂流。

Description

半導體裝置之製造方法
本發明係關於一種半導體裝置之製造技術,尤其係關於應用於以下步驟而有效之技術,即,於自毛細管之前端部引出之導電性導線之前端部形成初始滾珠(Free-Air Ball),並將該初始滾珠焊接至半導體晶片上之焊墊上。
於日本專利特開2009-105114號公報(專利文獻1)中,記載有以下技術:遍及毛細管之周圍而設置複數個氣體噴出噴嘴,一面自該等氣體噴出噴嘴噴出惰性氣體,一面於毛細管之前端部形成初始滾珠。
於日本專利特開昭60-244034號公報(專利文獻2)中,記載有以下技術:在設置於圓筒外殼上之貫通構件上配置毛細管之前端部,一面使惰性氣體自與該貫通構件連通之氣體吸入孔向貫通構件之內部空間流動,一面於毛細管之前端部形成初始滾珠。
於日本專利特開2008-130825號公報(專利文獻3)中,記載有以下技術:在設置於多孔質構件上之貫通孔中配置毛細管之前端部,一面遍及毛細管之周圍而自多孔質構件供給惰性氣體,一面於毛細管之前端部形成初始滾珠。
[先前技術文獻] [專利文獻] [專利文獻1]
日本專利特開2009-105114號公報
[專利文獻2]
日本專利特開昭60-244034號公報
[專利文獻3]
日本專利特開2008-130825號公報
半導體裝置包含MOSFET(Metal Oxide Semiconductor Field Effect Transistor,金屬氧化物半導體場效電晶體)等之半導體元件、形成有多層配線之半導體晶片、及以覆蓋該半導體晶片之方式而形成之封裝。封裝具有以下功能等:(1)將形成於半導體晶片上之半導體元件與外部電路電性連接;及(2)保護半導體晶片不受濕度或溫度等之外部環境之影響,防止由振動或衝擊而導致之破損或半導體晶片之特性劣化。進而,封裝亦兼具以下功能:(3)使半導體晶片之操作容易;及(4)釋散半導體晶片動作時之熱,使半導體元件之功能最大限度地發揮。
封裝中,例如為了實現將形成於半導體晶片上之半導體元件與外部電路電性連接之功能,將半導體晶片搭載於配線板上,將形成於半導體晶片上之焊墊、及形成於配線板上之端子以導電性導線而連接。
此處,於以導電性導線而連接形成於半導體晶片上之焊墊、及形成於配線板上之端子之情形時,首先,於毛細管之前端部形成初始滾珠,其後,將形成於毛細管之前端部之初始滾珠壓附於焊墊上。具體而言,藉由毛細管之負載 與超音波振動而將初始滾珠壓附於焊墊上。藉此,初始滾珠變形,形成可充分確保與焊墊之接觸面積之壓接滾珠。此時,為了於毛細管之前端部形成初始滾珠,首先,將毛細管之前端部配置於滾珠形成單元內之滾珠形成部之後,使焊炬電極、與於毛細管之前端部引出之導線之間放電。藉由該放電而產生熱,並藉由該產生之熱而使導線之前端部熔融。然後,熔融之導線因表面張力而成為球狀,藉此可於毛細管之前端部形成球狀之初始滾珠。
但是,導電性導線例如包含易被氧化之金屬,故而有時由放電產生之熱會使初始滾珠之表面氧化。該結果為,初始滾珠之形狀並非真球形狀,而是產生如前端突起形狀等之形狀不良之虞變高。亦即,於使用易被氧化之導電性導線作為導線之情形時,因初始滾珠之表面被氧化而易產生初始滾珠之形狀不良。
因此,當使用易被氧化之導電性導線之情形時,為了使初始滾珠之表面難以氧化,於惰性氣體等之抗氧化氣體環境中形成初始滾珠。然而,即便於抗氧化氣體環境中形成初始滾珠之情形時,於形成初始滾珠之時,若周圍之抗氧化氣體環境濃度不充分,則亦容易產生上述之初始滾珠之形狀不良。又,於形成初始滾珠之時,若周圍之抗氧化氣體之流量不穩定,則所形成之初始滾珠之直徑會產生不均。進而,於形成初始滾珠之時,在抗氧化氣體相對於導電性導線而為不均勻之情形時,所形成之初始滾珠相對於導電性導線而偏芯之虞變高。
若產生此種初始滾珠之形狀不良,則在將初始滾珠壓附於半導體晶片之焊墊上而形成壓接滾珠時,易對焊墊造成損害。
本發明之目的在於提供一種於使用易被氧化之導電性導線形成初始滾珠,並將該初始滾珠壓附於焊墊上而形成壓接滾珠之技術中,藉由抑制初始滾珠之形狀不良而可降低對焊墊之損害的技術。
本發明之上述以及其他目的與新穎之特徵可根據本說明書之記述及隨附圖式而明確瞭解。
本申請案所揭示之發明中,若簡單地說明代表性發明之概要,則如下所述。
代表性之實施形態之半導體裝置之製造方法的特徵在於,於滾珠形成單元中,將毛細管之前端部配置於滾珠形成部而形成初始滾珠,上述滾珠形成單元包含:滾珠形成部;將抗氧化氣體導入至滾珠形成部之氣體導入部;及自滾珠形成部排出抗氧化氣體之氣體排出部。此時,上述氣體排出部係設置於與將上述抗氧化氣體導入至上述滾珠形成部之方向不同之方向上。
本申請案所揭示之發明中,若簡單地說明藉由代表性發明而取得之效果,則如下所述。
於使用銅導線形成初始滾珠,且將該初始滾珠壓附於焊墊上而形成壓接滾珠之技術中,藉由抑制初始滾珠之形狀 不良而可降低對焊墊之損害。
於以下實施形態中,為方便起見,必要時分割成複數個區或實施形態進行說明,但除特別明示之情形外,其等並非相互無關者,而是存在一方為另一方之一部分或全部之變形例、詳情、補充說明等之關係。
又,於以下實施形態中,當提及要素之數目等(包含個數、數值、量、範圍等)時,除特別明示之情形及原理上明確限定為特定之數目之情形等外,並非限定於上述特定之數目,可為特定之數目以上,亦可為特定之數目以下。
進而,於以下實施形態中,其構成要素(亦包括要素步驟等)除特別明示之情形及認為原理上明確為必需之情形等以外,當然未必為必需者。
同樣地,於以下實施形態中,當提及構成要素等之形狀、位置關係等時,除特別明示之情形及認為原理上明確為並非如此之情形等以外,包含實質上與其形狀等近似或類似者等。該情形對於上述數值及範圍亦為相同。
又,於用以說明實施形態之所有圖式中,對於相同之構件,原則上標註相同之符號,省略其重複之說明。再者,為了易於理解圖式,即便為平面圖,有時亦標註陰影。
(實施形態1)
<半導體裝置(BGA(Ball Grid Array,球形陣列)封裝)之構成例>
於半導體裝置之封裝構造中,有例如BGA(Ball Grid Array)封裝、QFP(Quad Flat Package,四方扁平封裝)封裝等之各式種類。本發明之技術思想可應用於該等封裝,以下,對包含BGA封裝之半導體裝置之構成例、及包含QFP封裝之半導體裝置之構成例進行說明。
首先,一面參照圖式,一面對包含BGA封裝之半導體裝置之構成例進行說明。圖1係俯視觀察包含BGA封裝之半導體裝置SA1之平面圖。如圖1所示,本實施形態中之半導體裝置SA1形成為矩形形狀,半導體裝置SA1之上表面由樹脂(密封體)MR覆蓋。
繼而,圖2係俯視觀察半導體裝置SA1之圖,其係透視樹脂MR而表示之圖。如圖2所示,於透視半導體裝置SA1之樹脂MR所觀察之內部中,存在有矩形形狀之配線基板WB,於該配線基板WB上配置有半導體晶片CHP。該半導體晶片CHP亦形成為矩形形狀。半導體晶片CHP之大小為小於配線基板WB之大小,半導體晶片CHP係以平面上包含於配線基板WB內之方式而配置。尤其配置成使半導體晶片CHP之四邊分別與配線基板WB之四邊相互平行。
於上述半導體晶片CHP上形成有積體電路。具體而言,於構成半導體晶片CHP之半導體基板上,形成有複數個MOSFET等之半導體元件。而且,於半導體基板之上層經由層間絕緣膜而形成有多層配線,該等多層配線與形成於半導體基板上之複數個MOSFET電性連接而構成積體電路。亦即,半導體晶片CHP包含:形成有複數個MOSFET之半導體基板;及形成於該半導體基板之上方之多層配 線。如此於半導體晶片CHP上,藉由複數個MOSFET與多層配線而形成積體電路,但為了取得該積體電路與外部電路之介面,於半導體晶片CHP上形成有焊墊PD。該焊墊PD係藉由使形成於多層配線之最上層之最上層配線之一部分露出而形成。
如圖2所示,於半導體晶片CHP之主面(表面、上表面)上,形成有複數個焊墊PD。具體而言,以沿著形成為矩形形狀之半導體晶片CHP之四邊之各邊的方式而形成複數個焊墊PD。然後,以與形成於半導體晶片CHP上之複數個焊墊PD相對之方式沿著配線基板WB之四邊之各邊而形成複數個焊盤端子LD1。然後,形成於半導體晶片CHP上之焊墊PD與形成於配線基板WB上之焊盤端子LD1經由導電性構件而電性連接。再者,本實施形態中之導電性構件例如係包含銅(Cu)之導線W。
其次,圖3係自背面觀察本實施形態1中之半導體裝置SA1之圖。如圖3所示,於半導體裝置SA1之背面上,陣列狀(行列狀)地配置有複數個焊錫球SB。該焊錫球SB係作為半導體裝置SA1之外部連接端子而發揮功能者。
圖4係沿圖1之A-A線切斷後之剖面圖。圖4中,於配線基板WB之上表面上形成有焊盤端子LD1,另一方面,於配線基板WB之下表面上形成有端子(凸塊焊盤、電極)LD2。於配線基板WB之內部形成有多層配線及通道,形成於配線基板WB之上表面上之焊盤端子LD1與形成於配線基板WB之下表面上之端子LD2係藉由形成於配線基 板WB之內部之多層配線、及形成於通道之內部之通道配線而電性連接。形成於配線基板WB之下表面上之端子LD2係配置成陣列狀,且於該端子LD2上搭載有焊錫球SB。藉此,於配線基板WB之背面(下表面)上,陣列狀地配置有與端子LD2連接之焊錫球SB。
於配線基板WB之上表面(表面、主面)上,搭載有半導體晶片CHP,該半導體晶片CHP係由絕緣性之接著材料AD而與配線基板WB接著。而且,形成於半導體晶片CHP之主面上之焊墊PD、及形成於配線基板WB之上表面上之焊盤端子LD1係由導線W而連接。進而,於配線基板WB之上表面上,以覆蓋半導體晶片CHP及導線W之方式形成有樹脂(密封體)MR。
根據如此構成之半導體裝置SA1,形成於半導體晶片CHP上之焊墊PD經由導線W而與形成於配線基板WB上之焊盤端子LD1連接,該焊盤端子LD1藉由形成於配線基板WB之內部之配線及通道配線而與形成於配線基板WB之背面上之端子LD2電性連接。由此可知,形成於半導體晶片CHP上之積體電路係以焊墊PD→導線W→焊盤端子LD1→端子LD2→焊錫球SB之路徑而最終與焊錫球SB連接。由此可知,將外部電路電性連接於形成於半導體裝置SA1上之焊錫球SB,藉此可將形成於半導體晶片CHP上之積體電路與外部電路加以連接。
<半導體裝置(BGA封裝)之製造方法>
包含BGA封裝之半導體裝置SA1係以上述方式而構成, 以下,對其製造方法進行簡單地說明。圖5係表示製造包含BGA封裝之半導體裝置SA1之步驟之流程的流程圖。
首先,於半導體基板(半導體晶圓)之各自之晶片區域上形成半導體元件(MOSFET)、多層配線及焊墊。然後,實施半導體基板之背面研削而使半導體基板之厚度變薄之後,切割形成於半導體基板上之晶片區域,藉此形成複數個半導體晶片。
其次,準備配線基板,該配線基板係於表面上形成有複數個焊盤端子,且於與表面相反側之背面上形成有複數個端子。然後,對存在於配線基板之表面上之晶片搭載部(晶片搭載區域)塗佈接著材料。其後,經由塗佈於配線基板之晶片搭載部上之接著材料而搭載半導體晶片(晶片接合步驟)(S101)。
繼而,將形成於半導體晶片上之焊墊、與形成於配線基板上之焊盤端子以導線而連接(打線接合步驟)(S102)。具體而言,首先,將毛細管壓附於形成於半導體晶片上之焊墊上進行快速焊接。其後,使毛細管移動,將導線二次焊接至形成於配線基板上之焊盤端子上。以此方式,可將形成於半導體晶片上之焊墊、及形成於配線基板上之焊盤端子以導線而連接。
其次,以覆蓋半導體晶片、導線、及配線基板之表面之方式,例如形成包含樹脂之密封體(鑄模步驟)(S103)。其後,在形成於配線基板之背面之端子上,例如安裝包含焊料之焊錫球(外部連接端子)(焊錫球安裝步驟)(S104)。然 後,於密封體之表面,例如藉由雷射而刻印包含製造號碼等之標記(標記步驟)(S105)。以此方式製造之半導體裝置SA1藉由最終實施檢查(測試步驟)(S106)而分別選出良品與不良品,將判斷為良品之半導體裝置SA1出貨。
上述半導體裝置SA1係包含BGA封裝之半導體裝置,但可應用本發明之技術思想之封裝形態並不限於此。例如,亦可應用於使用引線框架而非配線基板作為搭載半導體晶片之基材(配線板)之封裝形態。具體而言,本發明之技術思想亦可廣泛應用於QFP封裝或QFN(Quad Flat No-lead,四方扁平無引腳)封裝。以下,尤其對包含QFP封裝之半導體裝置之構成例進行說明。
<半導體裝置(QFP封裝)之構成例>
首先,一面參照圖式一面對包含QFP封裝之半導體裝置之構成進行說明。圖6係俯視觀察包含QFP封裝之半導體裝置SA2之平面圖。如圖6所示,半導體裝置SA2形成為矩形形狀,半導體裝置SA2之上表面由樹脂(密封體)RM覆蓋。而且,外引腳OL自規定樹脂RM之外形之四邊向外側突出。
繼而,對半導體裝置SA2之內部構造進行說明。圖7係沿圖6之A-A線切斷後之剖面圖。如圖7所示,晶片搭載部TAB之背面由樹脂RM覆蓋。另一方面,於晶片搭載部TAB之上表面上搭載有半導體晶片CHP,於半導體晶片CHP之主面上形成有焊墊PD。而且,形成於半導體晶片CHP上之焊墊PD與內引腳IL係由導線W而電性連接。該等半導體晶 片CHP、導線W及內引腳IL係由樹脂RM覆蓋,與內引腳IL一體化之外引腳OL自樹脂RM突出。自樹脂RM突出之外引腳OL成形為鷗翼形狀,且於其表面上形成有電鍍膜PF。
晶片搭載部TAB、內引腳IL、及外引腳OL例如包含銅材或鐵與鎳之合金即42合金(42Alloy)等,導線W例如包含銅線。半導體晶片CHP例如包含矽或化合物半導體(GaAs等),於該半導體晶片CHP上,形成有MOSFET等之複數個半導體元件。而且,於半導體元件之上方經由層間絕緣膜而形成有多層配線,於該多層配線之最上層形成有與多層配線連接之焊墊PD。因此,形成於半導體晶片CHP上之半導體元件經由多層配線而與焊墊PD電性連接。亦即,藉由形成於半導體晶片CHP上之半導體元件與多層配線而形成積體電路,作為連接該積體電路與半導體晶片CHP之外部之端子而發揮功能者為焊墊PD。該焊墊PD係經導線W而與內引腳IL連接,且與和內引腳IL一體形成之外引腳OL連接。由此可知,形成於半導體晶片CHP上之積體電路可藉由焊墊PD→導線W→內引腳IL→外引腳OL→外部連接機器之路徑而與半導體裝置SA2之外部電性連接。亦即可知,自形成於半導體裝置SA2上之外引腳OL輸入電信號,藉此可控制形成於半導體晶片CHP上之積體電路。而且可知,亦可將來自積體電路之輸出信號自外引腳OL取出至外部。
<半導體裝置(QFP封裝)之製造方法>
包含QFP封裝之半導體裝置SA2係以上述方式而構成, 以下,對其製造方法進行簡單地說明。圖8係表示於半導體晶片上形成積體電路之後,製造包含QFP封裝之半導體裝置之步驟之流程的流程圖。首先,在形成於引線框架上之晶片搭載部上搭載半導體晶片之後(S201之晶片接合步驟),將形成於半導體晶片上之焊墊與內引腳經導線而連接(S202之打線接合步驟)。其後,由樹脂而密封晶片搭載部、半導體晶片、導線、及內引腳(S203之鑄模步驟)。然後,切斷形成於引線框架上之擋閘之後(S204之擋閘切斷步驟),於自樹脂露出之外引腳之表面形成電鍍膜(S205之電鍍步驟)。繼而,於樹脂之表面形成標記之後(S206之標記步驟),成形自樹脂突出之外引腳(S207之引線成形步驟)。以此方式形成半導體裝置SA2之後,實施電性特性檢查(S208之測試步驟),將判斷為良品之半導體裝置SA2作為製品而出貨。
<打線接合步驟之詳情>
如上所述,舉出包含BGA封裝之半導體裝置SA1、包含QFP封裝之半導體裝置SA2作為半導體裝置之封裝構造例,但本發明之技術思想係關於兩者共通之打線接合步驟(圖5之S102,圖8之S202)者。因此,以下,對打線接合步驟之詳情,舉例說明使用有引線框架之QFP。圖9(a)~圖14(a)係表示於打線接合步驟中,使毛細管動作之情形之部分剖面圖,圖9(b)~圖14(b)係自上方觀察之上述使毛細管動作之情形之平面圖。如圖9(a)及圖9(b)所示,於加熱板HP上配置有構成引線框架之引線LD與晶片搭載部TAB, 於晶片搭載部TAB上搭載半導體晶片CHP。於該半導體晶片CHP之表面(上表面)上,形成焊墊PD。加熱板HP作為熱源而發揮功能,使配置於加熱板HP上之引線LD被加熱,並且使經由晶片搭載部TAB而配置於加熱板HP上之半導體晶片CHP亦被加熱。
此處,打線接合步驟中,首先,如圖9(a)及圖9(b)所示,使於前端部形成有初始滾珠IBL之毛細管CAP下降。具體而言,於以夾持器CMP固定導線W之狀態下,使毛細管CAP下降至半導體晶片CHP之焊墊PD上。
繼而,如圖10(a)及圖10(b)所示,使形成於毛細管CAP之前端部之初始滾珠IBL落至半導體晶片CHP之焊墊PD上之後,對該初始滾珠IBL施加毛細管CAP之負載、自加熱板HP向半導體晶片CHP傳播之熱、及施加至毛細管CAP上之超音波振幅(超音波振動)。藉此,初始滾珠IBL變形,形成與焊墊PD之接觸面積較大之壓接滾珠PBL。以此方式,進行於半導體晶片CHP之焊墊PD上形成壓接滾珠PBL之快速焊接。
其次,如圖11(a)及圖11(b)所示,一面打開夾持器CMP,一面使毛細管CAP上升而引出形成廻路所必要之導線之後,閉合夾持器CMP,使毛細管CAP移動至引線LD上。然後,如圖12(a)及圖12(b)所示,一面施加毛細管CAP之負載、自加熱板HP向引線LD傳播之熱、及施加至毛細管CAP上之超音波振幅(超音波振動),一面將自毛細管CAP抽出之導線W焊接至引線LD上。此時,在導線W與 引線LD之連接部分之導線W上,形成有三個日月形狀之訂合部(新月形部)STCH。以此方式,進行連接導線W與引線LD之二次焊接。
其後,如圖13(a)及圖13(b)所示,於打開夾持器CMP之狀態下使毛細管CAP上升,藉此引出形成初始滾珠所必要之導線W。然後,如圖14(a)及圖14(b)所示,於閉合夾持器CMP之狀態下使毛細管CAP上升,藉此由訂合部STCH切斷二次焊接至引線LD上之導線W。其次,使毛細管CAP進一步上升,藉此將毛細管CAP之前端部配置於滾珠形成單元BFU內。
圖15係表示將毛細管CAP之前端部配置於滾珠形成單元BFU內之情形之圖。如圖15所示,於滾珠形成單元BFU中,設置有配置有毛細管CAP之前端部之滾珠形成部(滾珠形成部位、滾珠形成部分)BFP,且以自該滾珠形成部BFP之內壁突出而露出之方式設置有焊炬電極TCH。進而,於滾珠形成單元BFU中,設置有將抗氧化氣體導入至滾珠形成部BFP中之氣體導入部GIP。作為自氣體導入部GIP導入至滾珠形成部BFP中之抗氧化氣體,可舉出例如氮氣或氬氣等之惰性氣體、或將作為惰性氣體之氮氣與作為還原性氣體之氫氣混合而成之組成氣體等。
於如此構成之滾珠形成單元BFU中,以貫通滾珠形成單元BFU之厚度方向之方式形成滾珠形成部BFP,且可將毛細管CAP插入至該滾珠形成部BFP中。然後,如圖15所示,將毛細管CAP之前端部配置於滾珠形成部BFP之內部 之後,使自毛細管之前端部引出之導線W與焊炬電極TCH之間產生電弧放電。由此,藉由該電弧放電而產生熱,且藉由該產生之熱而使自毛細管CAP之前端部引出之導線W熔融。然後,如圖16所示,熔融之導線W於表面張力作用下成為球狀,藉此可於毛細管CAP之前端部形成球狀之初始滾珠(原始滾珠)IBL。以此方式,於毛細管CAP之前端部形成初始滾珠IBL之後,反覆實施上述打線接合步驟,藉此可將形成於半導體晶片CHP上之複數個焊墊PD、與複數個引線LD分別藉由導線W而電性連接。
<本發明者發現之課題>
於上述打線接合步驟中,如圖15或圖16所示,一面自氣體導入部GIP將抗氧化氣體導入至滾珠形成部BFP,一面於毛細管CAP之前端部形成初始滾珠IBL,此係根據以下所示之理由。
一般而言,使用金作為打線接合步驟中所使用之導線W之材料。該情形時,金不會被氧化,故而於毛細管CAP之前端部形成初始滾珠IBL之時,將抗氧化氣體導入至滾珠形成部BFP中之必要性減少。但是,伴隨近年來金價之上升,金導線於半導體裝置之成本中所占之比例亦變高,為抑制此現象,正在研討使用包含價格較金便宜之銅之銅導線。尤其是銅導線具有不僅成本低、而且電阻率較金導線低之特性,故而電氣特性亦優異,受到關注。
然而,於以銅導線構成導線之情形時,由於銅係易被氧化之金屬,故而藉由電弧放電而產生之熱會加速初始滾珠 IBL之表面之氧化。該結果為,初始滾珠IBL之形狀並非真球形狀,而是產生如前端突起形狀等之形狀不良之虞變高。亦即,於使用易被氧化之銅導線作為導線之情形時,因初始滾珠IBL之表面被氧化而易產生初始滾珠IBL之形狀不良。
因此,於使用銅等之易被氧化之導線W之情形時,為了使初始滾珠IBL之表面不被氧化,於惰性氣體等之抗氧化氣體環境中形成初始滾珠IBL。由於此種理由,故而於上述打線接合步驟中,如圖15或圖16所示,一面自氣體導入部GIP將抗氧化氣體導入至滾珠形成部BFP,一面於毛細管CAP之前端部形成初始滾珠IBL。亦即,於本實施形態1之打線接合步驟中,以使用銅或焊料等之易被氧化之金屬作為導線W為前提,而非使用金等之不會被氧化之金屬作為導線W。如此,本實施形態1之技術思想係關於使用易被氧化之金屬作為導線W之打線接合步驟之技術,且將使用易被氧化之金屬作為導線W之情形作為廣泛之對象。以下,特別以使用銅導線之情形為例進行說明。
如上述打線接合步驟般,於抗氧化氣體環境中形成初始滾珠IBL之情形時,於形成初始滾珠IBL之時,若周圍之抗氧化氣體環境濃度不充分,則易產生上述之初始滾珠IBL之形狀不良。又,於形成初始滾珠IBL之時,若周圍之抗氧化氣體之流量不穩定,則會使所形成之初始滾珠IBL之直徑產生不均。進而,於形成初始滾珠IBL之時,在抗氧化氣體相對於銅導線而為不均勻之情形時,所形成之初始 滾珠IBL相對於銅導線而偏芯之虞變高。本發明者發現,若產生此種初始滾珠IBL之形狀不良,則在將初始滾珠IBL壓附於半導體晶片CHP之焊墊PD上而形成壓接滾珠PBL之時,易對焊墊PD造成損害。尤其是銅比金堅硬,故而為了使初始滾珠IBL變形而形成壓接滾珠PBL,多數情形時施加更大之負載(例如,為使用金時之負載之1.5倍~2倍左右)。因此,銅導線之初始滾珠IBL之形狀不良與負載之增大一併成為加速對焊墊之損害之要因。
<基於初始滾珠之具體形狀不良而對焊墊造成之損害之說明>
以下,舉出初始滾珠IBL之形狀不良之具體例,詳細地說明對焊墊PD造成之損害。首先,對初始滾珠IBL之形狀為正常之情形進行說明。圖17及圖18係表示將正常形狀之初始滾珠IBL焊接(快速焊接)至焊墊PD上之步驟之剖面圖。如圖17所示,形成於半導體晶片上之焊墊PD為自形成於鈍化膜(表面保護膜)PAS上之開口部露出之構成。而且,於該露出之焊墊PD上配置有毛細管CAP。於該毛細管CAP之前端部形成有初始滾珠IBL。此時,圖17所示之初始滾珠IBL處於如下之正常狀態:為真球,滾珠直徑為適當,並且無偏芯,表面未被氧化。此種初始滾珠IBL形成於毛細管CAP之前端部,使該毛細管CAP下降,藉此使初始滾珠IBL落至焊墊PD上。然後,如圖18所示,落至焊墊PD上之初始滾珠IBL藉由來自毛細管CAP之負載及超音波振動、以及來自配置於半導體晶片之下之加熱板之熱能而 變形,成為壓接滾珠PBL。該壓接滾珠PBL包含:基座部PE;形成於基座部PE上之錐部CN;及形成於錐部CN上之孔插入部HI。此時,由於圖17所示之初始滾珠IBL處於正常狀態,故而藉由上述負載、超音波振動及熱負荷而形成適當形狀之壓接滾珠PBL。因此,不會對存在於壓接滾珠PBL之下層之焊墊PD施加設想外之損害,從而可將壓接滾珠PBL形成於焊墊PD上。
其次,對初始滾珠IBL1相對於導線W而偏芯之異常狀態之情形進行說明。圖19及圖20係表示將相對於導線W而偏芯之初始滾珠IBL1快速焊接至焊墊PD上之步驟之剖面圖。如圖19所示,於毛細管CAP之前端部形成有初始滾珠IBL1,但圖19所示之初始滾珠IBL1處於相對於導線W而偏芯之異常狀態。此種初始滾珠IBL1形成於毛細管CAP之前端部,使該毛細管CAP下降,藉此使初始滾珠IBL1落至焊墊PD上。然後,如圖20所示,落至焊墊PD上之初始滾珠IBL1藉由來自毛細管CAP之負載及超音波振動、以及來自配置於半導體晶片之下之加熱板之熱負荷而變形,成為壓接滾珠PBL1。該壓接滾珠PBL1包含:基座部PE1;形成於基座部PE1上之錐部CN1;及形成於錐部CN1上之孔插入部HI1。此時,將上述之負載、超音波振動及熱負荷施加至圖19所示之初始滾珠IBL1上。但是,圖19所示之初始滾珠IBL1處於相對於導線W而偏芯之異常狀態,故而初始滾珠IBL1於自毛細管CAP之中心偏移之狀態下焊接至焊墊PD上。因此,壓接滾珠PBL1之基座部PE1產生偏向而損壞。 因此,基座部PE1之形狀成為偏向之不均勻形狀,故而於與基座部PE1相接之焊墊PD上,施加有反映基座部PE1之不均勻形狀之局部之損害。進而,處於相對於導線W而偏芯之異常狀態之初始滾珠IBL1產生偏向而損壞,故而偏向之側之基座部PE1自焊墊PD露出,觸碰到鈍化膜PAS上。此意味著於鈍化膜PAS上施加有因基座部PE1觸碰而產生之負載,且存在有由於該負載而於鈍化膜PAS上產生龜裂之虞。若鈍化膜PAS上產生龜裂,則水分或異物會自此侵入至半導體晶片之內部,使半導體裝置之可靠性降低。又,於圖19所示之初始滾珠IBL之偏芯嚴重之情形時,於初始滾珠IBL1產生偏向而損壞時,基座部PE1甚至會接觸到鄰接之壓接滾珠PBL1。藉此,鄰接之壓接滾珠PBL1彼此短路,引起半導體裝置之動作不良。可知,如此於初始滾珠IBL1相對於導線W而偏芯之情形時,半導體裝置之可靠性降低。
繼而,對初始滾珠IBL2之滾珠直徑不均且使初始滾珠IBL2之滾珠直徑小於適當之滾珠直徑之異常狀態之情形進行說明。圖21及圖22係表示將小直徑之初始滾珠IBL2快速焊接至焊墊PD上之步驟之剖面圖。如圖21所示,於毛細管CAP之前端部形成有初始滾珠IBL2,但圖21所示之初始滾珠IBL2處於直徑小於適當之滾珠直徑之異常狀態。此種初始滾珠IBL2形成於毛細管CAP之前端部,使該毛細管CAP下降,藉此使初始滾珠IBL2落至焊墊PD上。然後,如圖22所示,落至焊墊PD上之初始滾珠IBL2藉由來自毛細管 CAP之負載及超音波振動、以及來自配置於半導體晶片之下之加熱板之熱負荷而變形,成為壓接滾珠PBL2。該壓接滾珠PBL2包含:基座部PE2;形成於基座部PE2上之錐部CN2;及形成於錐部CN2上之孔插入部HI2。此時,將上述之負載、超音波振動及熱負荷施加至圖21所示之初始滾珠IBL2上。但是,圖21所示之初始滾珠IBL2處於滾珠直徑小於適當之滾珠直徑之異常狀態,故藉由初始滾珠IBL2變形而形成之基座部PE2之體積變小。因此,若使來自毛細管CAP之負載不發生變化,則基座部PE2之體積變小意味著施加至基座部PE2之每單位體積之負載變大。此意味著對與基座部PE2之下層接觸之焊墊PD施加之每單位體積之負載變大,該結果為,施加至焊墊PD上之損害變大,半導體裝置之可靠性降低。
其次,對初始滾珠IBL3之形狀並非正常形狀、初始滾珠IBL3之前端部成為突起形狀之異常狀態之情形進行說明。圖23及圖24係表示將前端突起形狀之初始滾珠IBL3快速焊接至焊墊PD上之步驟之剖面圖。如圖23所示,於毛細管CAP之前端部形成有初始滾珠IBL3,但圖23所示之初始滾珠IBL3處於使初始滾珠IBL3之前端部成為突起形狀之異常狀態。此種初始滾珠IBL3形成於毛細管CAP之前端部,使該毛細管CAP下降,藉此使初始滾珠IBL3落至焊墊PD上。然後,如圖24所示,落至焊墊PD上之初始滾珠IBL3藉由來自毛細管CAP之負載及超音波振動、以及來自配置於半導體晶片之下之加熱板之熱負荷而變形,成為壓接滾珠 PBL3。該壓接滾珠PBL3包含:基座部PE3;形成於基座部PE3上之錐部CN3;及形成於錐部CN3上之孔插入部HI3。此時,將上述之負載、超音波振動及熱負荷施加至圖23所示之初始滾珠IBL3上。但是,圖23所示之初始滾珠IBL3之形狀處於使初始滾珠IBL3之前端部成為突起形狀之異常狀態,故而藉由初始滾珠IBL3變形而形成之基座部PE3之底面反映初始滾珠IBL3之前端突起形狀,存在有凸部。此意味著於存在於基座部PE3上之凸部上集中施加有負載。因此,自基座部PE3之凸部對焊墊PD之局部之一部分施加有較大之負載。該結果為,施加至焊墊PD上之損害變大,半導體裝置之可靠性降低。
由以上所述可知,為了抑制對打線接合步驟中之焊墊PD之損害,重要的是使形成於毛細管CAP之前端部之初始滾珠IBL處於如下之正常狀態:為真球,滾珠直徑為適當,並且無偏芯,表面未被氧化。換言之可知,使初始滾珠IBL之形狀儘可能不為異常形狀自抑制對焊墊PD之損害、使半導體裝置之可靠性提高之觀點而言為必要。
<研討構造中,初始滾珠之異常形狀產生之機制>
本發明者研討後明確瞭解,上述初始滾珠之異常形狀之產生容易受到滾珠形成單元中自氣體導入部流入至滾珠形成部中之抗氧化氣體之流動之影響。以下,舉出本發明者所研討之研討例1及研討例2,對初始滾珠之異常形狀頻發之機制進行說明。
圖25係表示本發明者所研討之研討例1中之滾珠形成單 元BFU之構成之圖。特別是,圖25(a)係表示研討例1中之滾珠形成單元BFU之一部分之平面圖,圖25(b)係沿圖25(a)之A-A線切斷後之剖面圖。又,圖25(c)係沿圖25(a)之B-B線切斷後之剖面圖。
首先,圖25(a)中,於研討例1之滾珠形成單元BFU中,設置配置有毛細管CAP之前端部之滾珠形成部BFP,且以自該滾珠形成部BFP之內壁突出而露出之方式設置焊炬電極TCH。進而,於滾珠形成單元BFU中,設置將抗氧化氣體導入至滾珠形成部BFP中之氣體導入部GIP。作為自氣體導入部GIP導入至滾珠形成部BFP中之抗氧化氣體,可舉出例如氮氣或氬氣等之惰性氣體、或將作為惰性氣體之氮氣與作為還原性氣體之氫氣混合而成之組成氣體。然後,如圖25(b)及圖25(c)所示,滾珠形成部BFP可貫通滾珠形成單元BFU之厚度方向,且可將毛細管CAP插入至該滾珠形成部BFP中。於如此構成之研討例1之滾珠形成單元BFU中,將毛細管CAP之前端部配置於滾珠形成部BFP之內部之後,一面將抗氧化氣體供給至滾珠形成部BFP之內部,一面使自毛細管之前端部引出之導線W與焊炬電極TCH之間產生電弧放電。藉此,可於毛細管CAP之前端部形成初始滾珠。
此處,於研討例1之滾珠形成單元BFU中形成初始滾珠後判明,所形成之初始滾珠之滾珠直徑中產生不均。若產生此種滾珠直徑之不均,則意味著會形成直徑小於適當之滾珠直徑之異常狀態之初始滾珠。於形成此種小直徑之初 始滾珠之情形時,藉由初始滾珠變形而形成之基座部之體積變小。該結果為,對基座部之每單位體積施加之負載變大,故而施加至與基座部之下層接觸之焊墊之每單位體積之負載變大。因此,施加至焊墊上之損害變大,半導體裝置之可靠性降低。
因此,調查於研討例1之滾珠形成單元BFU中形成之初始滾珠之滾珠直徑產生不均之原因。實際上,使用用於可視化之白色之氣體,並觀察其流動。其結果認為,初始滾珠之滾珠直徑之不均係由以下所示之要因而產生者。對該要因進行說明。
圖26係表示研討例1中之抗氧化氣體之流動之模式圖,圖26(a)~圖26(c)之各自與圖25(a)~圖25(c)之各自對應,以箭頭表示抗氧化氣體之流動。首先,於研討例1中,認為初始滾珠之滾珠直徑產生不均之第1要因係如下所述者。即,如圖26(a)或圖26(b)所示,認為自氣體導入部GIP導入至滾珠形成部BFP中之抗氧化氣體自貫通滾珠形成單元BFU之厚度方向之滾珠形成部BFP的上下方向排出。該情形時,首先認為,自滾珠形成部BFP之一側面側供給之氣流一面與經對向之另一方之側面反射之氣流發生碰撞而成為亂流,一面自滾珠形成部BFP之上下方向排出。亦即,研討例1之構成中,認為自滾珠形成部BFP之一側面側供給之氣流與經對向之另一方之側面反射之氣流發生碰撞而形成亂流。該結果為,於毛細管CAP之前端部引出之導線附近之氣流之流動因亂流而產生波動,故而認為初始滾珠之 滾珠直徑為不均。
進而,於研討例1中,認為初始滾珠之滾珠直徑產生不均之第2要因係如下所述者。即,如圖26(b)及圖26(c)所示,認為朝滾珠形成部BFP之上方排出之抗氧化氣體因所插入之毛細管CAP而妨礙流動從而無法順利地排出。亦即,朝滾珠形成部BFP之上方排出之抗氧化氣體之流動藉由毛細管CAP而受到妨礙從而成為螺旋狀,其結果認為,抗氧化氣體之流速變得不穩定,初始滾珠之滾珠直徑為不均。
繼而,圖27係表示本發明者研討之研討例2中之滾珠形成單元BFU之構成的圖。特別是,圖27(a)係表示研討例2中之滾珠形成單元BFU之一部分之平面圖,圖27(b)係沿圖27(a)之A-A線切斷後之剖面圖。又,圖27(c)係沿圖27(a)之B-B線切斷後之剖面圖。
首先,於圖27(a)中,於研討例2之滾珠形成單元BFU中,設置配置有毛細管CAP之前端部之滾珠形成部BFP,且以自該滾珠形成部BFP之內壁突出而露出之方式設置焊炬電極TCH。進而,於滾珠形成單元BFU中,設置將抗氧化氣體導入至滾珠形成部BFP中之氣體導入部GIP。作為自氣體導入部GIP導入至滾珠形成部BFP中之抗氧化氣體,可舉出例如氮氣或氬氣等之惰性氣體、或將作為惰性氣體之氮氣與作為還原性氣體之氫氣混合而成之組成氣體。此時,研討例2中,自氣體導入部GIP供給至滾珠形成部BFP之內部之抗氧化氣體係以自設置於滾珠形成部BFP 之周圍之複數個噴出孔HL導入至滾珠形成部BFP之內部的方式而構成。進而,如圖27(b)及圖27(c)所示,滾珠形成部BFP可貫通滾珠形成單元BFU之厚度方向,且可將毛細管CAP插入至該滾珠形成部BFP中。而且可知,於滾珠形成部BFP之側面設置有用以導入抗氧化氣體之複數個噴出孔HL。於如此構成之研討例2之滾珠形成單元BFU中,將毛細管CAP之前端部配置於滾珠形成部BFP之內部之後,一面將抗氧化氣體自複數個噴出孔HL供給至滾珠形成部BFP之內部,一面使自毛細管之前端部引出之導線W與焊炬電極TCH之間產生電弧放電。藉此,可於毛細管CAP之前端部形成初始滾珠。
此處,於研討例2之滾珠形成單元BFU中形成初始滾珠後判明,所形成之初始滾珠中產生偏芯或滾珠直徑之小徑化。初始滾珠之偏芯或滾珠直徑之小徑化之弊病如研討例1中以上所述。
因此,以與上述研討例1相同之方法調查於研討例2之滾珠形成單元BFU中形成之初始滾珠之偏芯或小徑化產生之原因。其結果認為,初始滾珠之偏芯或小徑化係由以下所示之要因而產生。對該要因進行說明。
圖28係表示研討例2中之抗氧化氣體之流動之模式圖,圖28(a)~圖28(c)之各自與圖27(a)~圖27(c)之各自對應,以箭頭表示抗氧化氣體之流動。首先,於研討例2中,認為初始滾珠中產生偏芯之要因係如下所述者。即,如圖28(a)所示,將抗氧化氣體自氣體導入部GIP藉由複數個噴出孔 HL而導入至滾珠形成部BFP。此時,於自配置於滾珠形成部BFP之周圍之複數個噴出孔HL均勻地供給抗氧化氣體之情形時,推測不會產生初始滾珠之偏芯。但是,實際上,如圖28(a)所示,自各個噴出孔HL噴出之氣體會因複數個噴出孔HL之配置部位而彼此碰撞,故而氣流之流動之大小產生偏向。藉此,碰撞到初始滾珠之氣流因方向而不同,故而認為所形成之初始滾珠會偏芯。
進而,於研討例2中,認為初始滾珠之滾珠直徑產生小徑化之要因係如下所述者。即,如圖28(b)及圖28(c)所示,各個噴出孔HL之開口面積變小,故而較氣體導入部GIP中之抗氧化氣體之流速,自開口面積較小之噴出孔HL向滾珠形成部BFP之內部噴出之抗氧化氣體之流速變大。此意味著碰撞到初始滾珠之抗氧化氣體之流速變大,藉此,意味著由抗氧化氣體產生之初始滾珠之冷卻效果變大。因此,於初始滾珠成為適當之滾珠直徑之前,熔融之導線變硬,故而認為產生初始滾珠之小徑化。
如上所述可知,於研討例1及研討例2之任一者之情形時,初始滾珠中之異常形狀之產生原因均係由於容易受到滾珠形成單元中自氣體導入部流入至滾珠形成部中之抗氧化氣體之流動之影響。因此,本實施形態1中,為了抑制初始滾珠中之異常形狀之產生,在改善(最佳化)滾珠形成單元中之抗氧化氣體之流動方面進行鑽研。以下,對進行該鑽研後之本實施形態1之技術思想進行說明。
<實施形態1中之滾珠形成單元之構造(本案發明之特 徵)>
圖29係表示本實施形態1中之滾珠形成單元BFU之構成之圖。特別是,圖29(a)係表示本實施形態1中之滾珠形成單元BFU之一部分之平面圖,圖29(b)係沿圖29(a)之A-A線切斷後之剖面圖。又,圖29(c)係沿圖29(a)之B-B線切斷後之剖面圖。
首先,圖29(a)中,於本實施形態1之滾珠形成單元BFU中,設置配置有毛細管CAP之前端部之滾珠形成部BFP,且以自該滾珠形成部BFP之內壁突出而露出之方式設置焊炬電極TCH。進而,於滾珠形成單元BFU中,設置將抗氧化氣體導入至滾珠形成部BFP中之氣體導入部GIP。作為自氣體導入部GIP導入至滾珠形成部BFP中之抗氧化氣體,可舉出例如氮氣或氬氣等之惰性氣體、或將作為惰性氣體之氮氣與作為還原性氣體之氫氣混合而成之組成氣體。再者,於使用由氮氣與氫氣混合而成之組成氣體之情形時,自防止氫氣爆炸之觀點而言,需使氫氣之濃度於未滿5%之範圍內進行添加。而且,如圖29(b)及圖29(c)所示,滾珠形成部BFP可貫通滾珠形成單元BFU之厚度方向,且可將毛細管CAP插入至該滾珠形成部BFP中。如此構成之本實施形態1之滾珠形成單元BFU中,將毛細管CAP之前端部配置於滾珠形成部BFP之內部之後,一面將抗氧化氣體供給至滾珠形成部BFP之內部,一面使自毛細管之前端部引出之導線W與焊炬電極TCH之間產生電弧放電。藉此,可於毛細管CAP之前端部形成初始滾珠。如此,於 滾珠形成單元BFU中,使自毛細管之前端部引出之導線W與焊炬電極TCH之間產生電弧放電,故而對構成滾珠形成單元BFU之構件要求絕緣性。進而,將滾珠形成單元BFU例如以圖14(a)所示之方式配置於加熱板HP之上方。因此,滾珠形成單元BFU附近之環境溫度因來自加熱板HP之輻射熱而成為100℃~120℃左右,故而對滾珠形成單元BFU要求耐受100℃~120℃左右之溫度之耐熱性。如上所述,對構成滾珠形成單元BFU之構件,要求絕緣性與耐熱性。自該觀點而言,滾珠形成單元BFU使用例如聚醯胺醯亞胺樹脂、陶瓷、或玻璃等。尤其於使用聚醯胺醯亞胺樹脂之情形時,由於聚醯胺醯亞胺樹脂具有加工性容易、且難以破裂之性質,故而可使滾珠形成單元BFU之加工性提高,並且可使可靠性提高。
此處,本實施形態1之特徵點在於,如圖29(a)所示,於滾珠形成單元BFU中設置有排出抗氧化氣體之氣體排出部GOP,將該氣體排出部GOP之排出路徑設置於與將抗氧化氣體導入至滾珠形成部BFP之方向不同之方向上。換言之,本實施形態1之特徵點在於以下點:氣體導入部GIP之抗氧化氣體之導入方向(供給方向)、與氣體排出部GOP之抗氧化氣體之排出方向不同。藉此,根據本實施形態1,可使排出抗氧化氣體之區域增加,故而可抑制自滾珠形成部BFP之一側面側供給之氣流於對向之另一方之側面使氣流反射而形成亂流。該結果為,可使滾珠形成部BFP之氣流之流動穩定化。
例如,於上述研討例1(參照圖25)之情形時,自氣體導入部GIP供給至滾珠形成部BFP之抗氧化氣體之排出路徑僅存在於貫通滾珠形成單元BFU之厚度方向之滾珠形成部BFP之上下方向。進而,滾珠形成部BFP之上部配置有毛細管CAP之前端部,故而抗氧化氣體排出之路徑變得非常狹窄,導入至滾珠形成部BFP中之抗氧化氣體難以排出。因此,自氣體導入部GIP供給至滾珠形成部BFP中之氣體難以順利地排出,導入至滾珠形成部BFP中之抗氧化氣體碰撞到與所供給之滾珠形成部BFP之一側面側對向之另一方之側面的概率變高。藉此,自滾珠形成部BFP之一側面側供給之氣流與經對向之另一方之側面反射之氣流易發生碰撞而形成亂流。若形成亂流,則於毛細管CAP之前端部引出之導線附近之氣流之流動因亂流而產生波動,故而產生初始滾珠之滾珠直徑不均之問題點。
相對於此,以下,對本實施形態1中之滾珠形成單元BFU進行說明。圖30係表示本實施形態1中之抗氧化氣體之流動之模式圖,圖30(a)~圖30(c)之各自與圖29(a)~圖29(c)之各自對應,以箭頭表示抗氧化氣體之流動。本實施形態1之滾珠形成單元BFU中,如圖30(a)所示,設置有排出抗氧化氣體之氣體排出部GOP。亦即,本實施形態1中,作為自氣體導入部GIP導入之抗氧化氣體之排出路徑,不僅存在於貫通滾珠形成單元BFU之厚度方向之滾珠形成部BFP之上下方向,此外亦存在於氣體排出部GOP。因此,根據本實施形態1,於抗氧化氣體之排出路徑上追 加有氣體排出部GOP,故而供給至滾珠形成部BFP之抗氧化氣體可順利地自氣體排出部GOP有效地排出。尤其於氣體排出部GOP之內部,並未配置毛細管CAP本身,且未配置抗氧化氣體排出時成為障礙之構件,故而可使抗氧化氣體自氣體排出部GOP充分地排出。即,本實施形態1中,自氣體導入部GIP供給至滾珠形成部BFP之抗氧化氣體之大多數係自新設置的氣體排出部GOP排出(參照圖30(a)及圖30(b))。因此,根據本實施形態1,供給至滾珠形成部BFP之抗氧化氣體中,未自氣體排出部GOP排氣之抗氧化氣體之流量變少,故而亦可自排氣容量較少之滾珠形成部BFP之上下方向順利地排出該殘存之抗氧化氣體,而不會使其滯留(參照圖30(b)及圖30(c))。亦即,本實施形態1中,可取得直接的第1效果,即,藉由設置排氣容量較大之氣體排出部GOP而可將供給至滾珠形成部BFP之抗氧化氣體效率良好地排出。進而,可取得間接的第2效果,即,由於使大部分之抗氧化氣體自氣體排出部GOP排出,故而可使未自氣體排出部GOP排氣之抗氧化氣體之流量變少。而且,根據該第2效果,自排氣容量較少之滾珠形成部BFP之上下方向亦可順利地排出該殘存之抗氧化氣體,而不會使其滯留。即,根據本實施形態1,藉由上述第1效果與第2效果之協同效果,可將自氣體導入部GIP導入至滾珠形成部BFP中之抗氧化氣體順利地排出。此意味著自滾珠形成部BFP之一側面側供給之抗氧化氣體之大多數會順利地排出,而不會碰撞到對向之另一方之側面而形成亂 流。藉此,根據本實施形態1,可充分抑制自滾珠形成部BFP之一側面側供給之氣流與經對向之另一方之側面反射之氣流發生碰撞而形成亂流。換言之,即便自滾珠形成部BFP之一側面側供給之氣流經對向之另一方之側面反射,反射後之氣流變亦會自氣體排出部GOP順利地排出,故而可抑制自滾珠形成部BFP之一側面側供給之氣流與經對向之另一方之側面反射之氣流發生碰撞而產生亂流。因此,根據本實施形態1,可使滾珠形成部BFP之氣流之流動穩定化。
進而,本實施形態1中之特徵點在於以下之點:氣體導入部GIP之抗氧化氣體之導入方向(供給方向)、與氣體排出部GOP之抗氧化氣體之排出方向不同。例如,自順利地排出從氣體導入部GIP導入至滾珠形成部BFP中之抗氧化氣體之觀點而言,認為較理想的是抗氧化氣體之導入方向(供給方向)、與抗氧化氣體之排出方向一致。然而,此種構成之情形時,會產生如下所示之不良。例如,於抗氧化氣體之導入方向(供給方向)、與抗氧化氣體之排出方向一致之情形時,抗氧化氣體自氣體導入部GIP向氣體排出部GOP而朝一方向流動。藉此,始終流動有相對於形成於毛細管CAP之前端部之初始滾珠而偏向一方之氣流。此意味著藉由偏向一方之氣流而使初始滾珠易偏芯。即,自於毛細管CAP之前端部形成無偏芯之初始滾珠之觀點而言,必需儘可能避免使偏向一方之氣流流動。為了形成無偏芯之初始滾珠,重要的是,一方面保持滾珠形成部BFP內之抗 氧化氣體濃度穩定之狀態,一方面可不滯留地順利地更換自氣體導入部GIP供給之新的抗氧化氣體與自氣體排出部GOP排出之舊的抗氧化氣體。因此,本實施形態1中,以使氣體導入部GIP之抗氧化氣體之導入方向(供給方向)、與氣體排出部GOP之抗氧化氣體之排出方向不同之方式而構成。具體而言,例如,如圖29(a)所示,以使氣體導入部GIP之抗氧化氣體之導入方向(供給方向)、與氣體排出部GOP之抗氧化氣體之排出方向成為90°之方式而構成。藉此,可抑制總是流動有相對於形成於毛細管CAP之前端部之初始滾珠而偏向一方之氣流。該結果為,本實施形態中,可抑制藉由偏向一方之氣流而使初始滾珠偏芯。
繼而,對本實施形態1之進一步的特徵點進行說明。例如,如圖29(a)~圖29(c)所示,本實施形態1中,特徵點在於氣體排出部GOP貫通滾珠形成單元BFU之厚度方向。藉此,可使氣體排出部GOP之剖面積為最大(滾珠形成單元BFU之厚度之量),故而可加大自氣體排出部GOP排出抗氧化氣體之排氣容量。藉此,相對於自氣體導入部GIP導入至滾珠形成部BFP中之抗氧化氣體,可減小排氣阻力而自氣體排出部GOP有效地排出。進而,以使氣體排出部GOP貫通滾珠形成單元BFU之厚度方向之方式而構成,藉此可使氣體排出部GOP之剖面積大於設置於滾珠形成單元BFU之內部之氣體導入部GIP之剖面積。因此,根據本實施形態1,可使自滾珠形成部BFP向氣體排出部GOP可排出之抗氧化氣體之流量(排氣容量)大於自氣體導入部GIP流入至 滾珠形成部BFP中之抗氧化氣體之流量(流入容量)。因此,根據本實施形態1,可自滾珠形成部BFP順利地排出抗氧化氣體。
又,除氣體排出部GOP貫通滾珠形成單元BFU之厚度方向之構成外,使氣體排出部GOP之剖面之寬度為毛細管CAP之寬度以上,藉此亦可取得以下所示之優點。例如,由於毛細管CAP亦存在壽命,故而必需進行更換毛細管CAP之作業。此時,於如研討例1所示之滾珠形成單元BFU中,使毛細管CAP本身上升,自滾珠形成單元BFU內之滾珠形成部BFP引出至外側之後,更換毛細管CAP。然後,於更換毛細管CAP之後,必需再次使毛細管CAP下降,將毛細管CAP之前端部插入至滾珠形成單元BFU內之滾珠形成部BFP中。
相對於此,本實施形態1之滾珠形成單元BFU中,取得如下構成:設置有氣體排出部GOP,該氣體排出部GOP貫通滾珠形成單元BFU之厚度方向,並且使氣體排出部GOP之剖面之寬度為毛細管CAP之寬度以上。取得該構成後,於更換毛細管CAP之情形時,無需使毛細管CAP本身上升,可使其於橫方向上滑動,自氣體排出部GOP將毛細管CAP取出至外側空間。然後,於取出之狀態下,更換毛細管CAP之後,可再次使更換後之毛細管CAP於橫方向上滑動,將毛細管CAP之前端部插入至滾珠形成單元BFU內之滾珠形成部BFP中。如此,根據本實施形態1,於毛細管CAP之更換作業之時,無需使毛細管CAP本身上下移動, 故而取得可提高作業效率之優點。
進而,本實施形態1中,例如較理想的是,如圖29(a)所示,使氣體排出部GOP之剖面之寬度為滾珠形成部BFP之寬度以下。其原因在於,為了將抗氧化氣體自滾珠形成部BFP有效地排氣,只要使氣體排出部GOP之剖面之寬度為與滾珠形成部BFP之寬度相同之程度以下則足夠。亦即,其原因在於,例如,若使氣體排出部GOP之剖面之寬度大於滾珠形成部BFP之寬度,則認為抗氧化氣體之排出效率會進一步提高,但實際上,若不僅不使氣體排出部GOP之剖面之寬度變化為與滾珠形成部BFP之寬度相同程度之情形,或者相反地使氣體排出部GOP之剖面之寬度過大,則存在於外部之空氣通過氣體排出部GOP而流入至滾珠形成部BFP中之虞變高。若存在於外部之空氣通過氣體排出部GOP而流入至滾珠形成部BFP中,則由於所流入之空氣而產生使初始滾珠之表面氧化之不良情形之虞變高。因此,由將抗氧化氣體自滾珠形成部BFP有效地排氣,並且防止存在於外部之空氣流入之觀點而言,較理想的是使氣體排出部GOP之剖面之寬度為與滾珠形成部BFP之寬度相同之程度以下。
具體而言,於本實施形態1之滾珠形成單元BFU中,例如,滾珠形成單元BFU之厚度為2.5 mm,氣體導入部GIP之直徑為2.0 mm,滾珠形成部BFP之直徑(寬度)為2.2 mm,氣體排出部之剖面之寬度為1.6 mm。
其次,一面與研討例1或研討例2加以比較,一面說明本 實施形態1之優異性。圖31係表示初始滾珠之滾珠直徑與抗氧化氣體之氣體流量之關係之圖表。圖31中,將本實施形態1、研討例1、及研討例2加以比較而表示。於圖31中,橫軸表示氣體流量(l/min),縱軸中之左軸表示初始滾珠之滾珠直徑之最大值、最小值、及平均值(μm),縱軸中之右軸表示初始滾珠之滾珠直徑之偏差(μm)。如圖31所示可知,與本實施形態1相比,研討例1及研討例2中,初始滾珠之滾珠直徑之平均值或偏差伴隨氣體流量之變化而具有不均。亦即,根據本實施形態1可知,與研討例1或研討例2相比具有如下優異性:(1)所形成之初始滾珠之滾珠直徑之不均較小;(2)伴隨氣體流量之變化,滾珠直徑之變化較小;(3)即便氣體流量變大,初始滾珠亦不會偏芯。此意味著根據本實施形態1,即便導入至滾珠形成單元中之抗氧化氣體之流量稍微產生變化,所形成之初始滾珠之滾珠直徑亦穩定。換言之可知,意味著根據本實施形態1中之滾珠形成單元,對於抗氧化氣體之氣體流量之變化,可確保充分之容限,該結果為,可穩定地形成適當之初始滾珠。以上所述可認為,根據本實施形態1,由於設置有氣體排出部GOP,故而即便抗氧化氣體之氣體流量發生變化,亦可確保順利地排出。
由以上所述,根據本實施形態1,於將銅或焊料等之易被氧化之金屬用作導線之打線接合步驟中,可抑制對焊墊之損害。即,根據本實施形態1可知,可充分地實現使形成於毛細管之前端部之初始滾珠處於如下之正常狀態:為 真球,滾珠直徑為適當,並且無偏芯,表面未被氧化。其結果為,因初始滾珠之偏芯而對打線接合時之焊墊之損害等受到抑制,故而可使半導體裝置之可靠性提高。
<變形例1(氣體排出部之排出方向)>
上述實施形態1中,對氣體導入部之抗氧化氣體之導入方向(供給方向)、與氣體排出部之抗氧化氣體之排出方向相差90°之例進行了說明,但本變形例1中,對上述之導入方向與排出方向相差90°±45°之例進行說明。
圖32係表示本變形例1中之滾珠形成單元BFU之構成之圖。特別是,圖32(a)係表示本變形例1中之滾珠形成單元BFU之一部分之平面圖,圖32(b)係沿圖32(a)之A-A線切斷後之剖面圖。又,圖32(c)係沿圖32(a)之B-B線切斷後之剖面圖。又,圖33係表示本變形例1中之其他滾珠形成單元BFU之構成之圖。特別是,圖33(a)係表示本變形例1中之滾珠形成單元BFU之一部分之平面圖,圖33(b)係沿圖33(a)之A-A線切斷後之剖面圖。又,圖33(c)係沿圖33(a)之B-B線切斷後之剖面圖。
本變形例1與上述實施形態1之不同點為以下之點:上述實施形態1中,氣體導入部之抗氧化氣體之導入方向(供給方向)、與氣體排出部之抗氧化氣體之排出方向相差90°,相對於此,本變形例1中,上述之導入方向與排出方向相差90°±45°。如此構成之本變形例1中,亦可取得與上述實施形態1相同之效果。即,本變形例1中亦為,於滾珠形成單元BFU中設置有排出抗氧化氣體之氣體排出部GOP,將 該氣體排出部GOP之排出路徑設置於與將抗氧化氣體導入至滾珠形成部BFP中之方向不同之方向上。藉此,根據本變形例1,可使排出抗氧化氣體之區域增加,故而可抑制自滾珠形成部BFP之一側面側供給之氣流於對向之另一方之側面使氣流反射而形成亂流。該結果為,可使滾珠形成部BFP之氣流之流動穩定化。特別是本變形例1中,以使氣體導入部GIP之抗氧化氣體之導入方向(供給方向)、與氣體排出部GOP之抗氧化氣體之排出方向為90°±45°之方式而構成。藉此,可抑制始終流動有相對於形成於毛細管CAP之前端部之初始滾珠而偏向一方之氣流。該結果為,本實施形態中,可抑制藉由偏向一方之氣流而使初始滾珠偏芯。
如此,本案發明之技術思想中,較理想的是氣體排出部之抗氧化氣體之排出方向相對於氣體導入部之抗氧化氣體之導入方向(供給方向)而包含於90°±45°之範圍內。其原因在於,於設置具有上述範圍外之角度之氣體排出部GOP之情形時,如下問題點會顯著化,即,無法保持氣體環境濃度;對於抗氧化氣體之排出,排出阻力變大,產生亂流或流速變動之虞提高。
<變形例2(氣體排出部之剖面積)>
氣體排出部GOP之剖面積較理想的是不妨礙抗氧化氣體之排出之大小,具體而言,在將氣體排出部GOP貫通滾珠形成單元BFU之厚度方向時之剖面積設為100%(最大剖面積)之情形時,較理想的是以相對於該剖面積而具有 50%~100%之剖面積之方式設置氣體排出部GOP。
以下,對具有上述範圍內之剖面積之氣體排出部GOP之構成例進行說明。圖34係表示本變形例2中之滾珠形成單元BFU之構成之圖。特別是,圖34(a)係表示本變形例2中之滾珠形成單元BFU之一部分之平面圖,圖34(b)係沿圖34(a)之A-A線切斷後之剖面圖。又,圖34(c)係沿圖34(a)之B-B線切斷後之剖面圖。
如圖34(a)~圖34(c)所示,本變形例2中之氣體排出部GOP1貫通滾珠形成單元BFU之厚度方向。因此,圖34所示之氣體排出部GOP1之剖面積成為最大(100%),可將抗氧化氣體自氣體排出部GOP1有效地排出。
繼而,圖35係表示本變形例2中之其他滾珠形成單元BFU之構成之圖。特別是,圖35(a)係表示本變形例2中之其他滾珠形成單元BFU之一部分之平面圖,圖35(b)係沿圖35(a)之A-A線切斷後之剖面圖。又,圖35(c)係沿圖35(a)之B-B線切斷後之剖面圖。
如圖35(a)~圖35(c)所示,本變形例2中之氣體排出部GOP2未貫通滾珠形成單元BFU之厚度方向,尤其如圖35(b)所示,自滾珠形成單元BFU之底面側遍及上表面附近而形成有開口部。具體而言,以如下方式構成:圖35所示之氣體排出部GOP2之剖面積相對於最大剖面積而成為75%之剖面積,並非圖34所示之情形之程度,但可將抗氧化氣體自氣體排出部GOP2充分地排出。
其次,圖36係表示本變形例2中之其他滾珠形成單元 BFU之構成之圖。特別是,圖36(a)係表示本變形例2中之其他滾珠形成單元BFU之一部分之平面圖,圖36(b)係沿圖36(a)之A-A線切斷後之剖面圖。又,圖36(c)係沿圖36(a)之B-B線切斷後之剖面圖。
如圖36(a)~圖36(c)所示,本變形例2中之氣體排出部GOP3未貫通滾珠形成單元BFU之厚度方向,尤其如圖36(b)所示,自滾珠形成單元BFU之上表面側遍及底面附近而形成有開口部。具體而言,以如下方式而構成:圖36所示之氣體排出部GOP3之剖面積相對於最大剖面積而成為75%之剖面積,並非圖34所示之情形之程度,但可將抗氧化氣體自氣體排出部GOP3充分地排出。
<變形例3(氣體排出部之剖面形狀)>
氣體排出部GOP之剖面形狀除貫通滾珠形成單元之厚度方向而形成之開口形狀外,只要具有變形例2中說明之剖面積,則亦可為矩形形狀或圓形形狀等。
圖37係表示本變形例3中之滾珠形成單元BFU之構成之圖。特別是,圖37(a)係表示本變形例3中之滾珠形成單元BFU之一部分之平面圖,圖37(b)係沿圖37(a)之A-A線切斷後之剖面圖。又,圖37(c)係沿圖37(a)之B-B線切斷後之剖面圖。
如圖37(a)~圖37(c)所示,本變形例3中之氣體排出部GOP4未貫通滾珠形成單元BFU之厚度方向,尤其如圖37(b)所示,於滾珠形成單元BFU之中央部附近形成有開口部。具體而言,圖37所示之氣體排出部GOP4之剖面積相 對於最大剖面積而為50%以上之剖面積,開口部之剖面形狀成為矩形形狀。於如此構成之情形時,亦可將抗氧化氣體自氣體排出部GOP4充分地排出。
圖38係表示本變形例3中之其他滾珠形成單元BFU之構成之圖。特別是,圖38(a)係表示本變形例3中之其他滾珠形成單元BFU之一部分之平面圖,圖38(b)係沿圖38(a)之A-A線切斷後之剖面圖。又,圖38(c)係沿圖38(a)之B-B線切斷後之剖面圖。
如圖38(a)~圖38(c)所示,本變形例3中之氣體排出部GOP5未貫通滾珠形成單元BFU之厚度方向,尤其如圖38(b)所示,遍及滾珠形成單元BFU之中央部附近而形成有開口部。具體而言,圖38所示之氣體排出部GOP5之剖面積相對於最大剖面積而為50%以上之剖面積,開口部之剖面形狀成為圓形形狀。於如此構成之情形時,亦可將抗氧化氣體自氣體排出部GOP5充分地排出。
(實施形態2)
本實施形態2中,對在相對於對毛細管之前端部而與氣體導入部相反之側設置有氣體積存部之例進行說明。
圖39係表示本實施形態2中之滾珠形成單元BFU之構成之圖。特別是,圖39(a)係表示本實施形態2中之滾珠形成單元BFU之一部分之平面圖,圖39(b)係沿圖39(a)之A-A線切斷後之剖面圖。又,圖39(c)係沿圖39(a)之B-B線切斷後之剖面圖。
本實施形態2與上述實施形態1之不同點為以下之點:本 實施形態2之滾珠形成單元中,在相對於毛細管CAP之前端部而與氣體導入部GIP相反之側設置有氣體積存部GCP。根據如此構成之本實施形態2中之滾珠形成單元BFU,可降低自氣體導入部GIP供給之氣流、與經氣體積存部GCP彈回之氣流因碰撞而產生之亂流,並且即便產生亂流,亦可較上述實施形態1之情形更遠離該亂流之形成位置。該結果為,根據本實施形態2,上述亂流對形成於毛細管CAP之前端部之初始滾珠之影響變小,故而可使流動於初始滾珠附近之氣流更加順利,藉此,可形成穩定之初始滾珠。
由以上所述,根據本實施形態2,於將銅或焊料等之易被氧化之金屬用作導線之打線接合步驟中,可抑制對焊墊之損害。即,根據本實施形態2可知,可充分地實現使形成於毛細管之前端部之初始滾珠處於如下之正常狀態:為真球,滾珠直徑為適當,並且無偏芯,表面未被氧化。其結果為,因初始滾珠之偏芯而對打線接合時之焊墊之損害等受到抑制,故而可使半導體裝置之可靠性提高。
圖40係表示本實施形態2中之抗氧化氣體之流動之模式圖,圖40(a)~圖40(c)之各自與圖39(a)~圖39(c)之各自對應,以箭頭表示抗氧化氣體之流動。本實施形態2之滾珠形成單元BFU中,與上述實施形態1同樣地,設置有排出抗氧化氣體之氣體排出部GOP。亦即,本實施形態2中,作為自氣體導入部GIP導入之抗氧化氣體之排出路徑,不僅存在於貫通滾珠形成單元BFU之厚度方向之滾珠形成部 BFP之上下方向,此外亦存在於氣體排出部GOP。因此,根據本實施形態2,於抗氧化氣體之排出路徑上追加有氣體排出部GOP,故而供給至滾珠形成部BFP之抗氧化氣體可順利地自氣體排出部GOP有效地排出。尤其於氣體排出部GOP之內部,未配置毛細管CAP本身,且未配置抗氧化氣體排出時成為障礙之構件,故而可使抗氧化氣體自氣體排出部GOP充分地排出。
進而,本實施形態2中,如圖40(a)及圖40(b)所示,由於設置有氣體積存部GCP,故而可降低自氣體導入部GIP供給之氣流、與經氣體積存部GCP彈回之氣流因碰撞而產生之亂流,並且即便產生亂流,亦可較上述實施形態1之情形更遠離該亂流之形成位置。該結果為,根據本實施形態2,上述亂流對形成於毛細管CAP之前端部之初始滾珠之影響變小,故而可使流動於初始滾珠附近之氣流更加順利,藉此,可形成穩定之初始滾珠。
以上,對由本發明者完成之發明根據其實施形態而進行了具體說明,但本發明並不限定於上述實施形態,當然於不脫離其要旨之範圍內可進行各種變更。
上述MOSFET並不限定於由氧化膜形成閘極絕緣膜之情形,假定亦包含由較寬之絕緣膜形成閘極絕緣膜之MISFET(Metal Insulator Semiconductor Field Effect Transistor,金氧絕緣半導體場效電晶體)。亦即,本說明書中,為方便起見而使用MOSFET之用語,該MOSFET係作為亦包含MISFET之意圖之用語而用於本說明書中。
本案發明之技術思想係關於使用易被氧化之金屬作為導線之打線接合步驟者,尤其於上述實施形態中,舉出使用銅導線之情形為例進行了說明,但本案發明之技術思想並不限於此,例如,亦可廣泛應用於使用有焊料等之易被氧化之金屬之打線接合步驟。
<變形例>
再者,上述實施形態中,舉出使用有銅導線之打線接合步驟為例進行了說明,但本案發明之技術思想亦可廣泛應用於形成包含銅之柱形凸塊電極之步驟。其原因在於,柱形凸塊電極亦以如下方式而形成:藉由毛細管而使形成於前端部之初始滾珠落至焊墊上之後,施加壓縮負載及超音波振動藉以使初始滾珠變形而形成壓接滾珠,於該壓接滾珠之前端部切斷銅導線,以此形成柱形凸塊電極。亦即,銅導線之打線接合步驟與柱形凸塊電極形成步驟之任一者均為施加壓縮負載及超音波振動而形成壓接滾珠,該點為共通,故而認為於形成包含銅之柱形凸塊電極之步驟中,對焊墊之損害之問題亦會顯著化。因此,於形成柱形凸塊電極之步驟中,亦可藉由應用本發明之技術思想而有效地防止對焊墊之損害。
以下,對柱形凸塊電極之構成例進行說明。圖41係表示形成於半導體晶片CHP上之複數個柱形凸塊電極SBMP之圖。圖41中雖未圖示,但於形成於半導體晶片CHP之表面上之焊墊上配置有柱形凸塊電極SBMP。如此形成有柱形凸塊電極SBMP之半導體晶片CHP例如係藉由面朝下焊接 而安裝於配線基板上。
圖42係表示將形成有柱形凸塊電極SBMP之半導體晶片CHP安裝於配線基板WB上之一例之圖。如圖42所示,於配線基板WB上形成有端子TE,且以使該端子TE、與搭載於半導體晶片CHP上之柱形凸塊電極SBMP相對之方式而配置。而且,搭載於半導體晶片CHP上之柱形凸塊電極SBMP、與形成於配線基板WB上之端子TE例如藉由焊料S而連接。以上述方式,可將形成有柱形凸塊電極SBMP之半導體晶片CHP安裝於配線基板WB上。
[產業上之可利用性]
本發明可廣泛利用於製造半導體裝置之製造業。
AD‧‧‧接著材料
BFP‧‧‧滾珠形成部
BFU‧‧‧滾珠形成單元
CAP‧‧‧毛細管
CHP‧‧‧半導體晶片
CMP‧‧‧夾持器
CN‧‧‧錐部
CN1‧‧‧錐部
CN2‧‧‧錐部
CN3‧‧‧錐部
GCP‧‧‧氣體積存部
GIP‧‧‧氣體導入部
GOP‧‧‧氣體排出部
GOP1‧‧‧氣體排出部
GOP2‧‧‧氣體排出部
GOP3‧‧‧氣體排出部
GOP4‧‧‧氣體排出部
GOP5‧‧‧氣體排出部
HI‧‧‧孔插入部
HI1‧‧‧孔插入部
HI2‧‧‧孔插入部
HI3‧‧‧孔插入部
HL‧‧‧噴出孔
HP‧‧‧加熱板
IBL‧‧‧初始滾珠
IBL1‧‧‧初始滾珠
IBL2‧‧‧初始滾珠
IBL3‧‧‧初始滾珠
IL‧‧‧內引腳
LD‧‧‧引線
LD1‧‧‧焊盤端子
LD2‧‧‧端子
MR‧‧‧樹脂
OL‧‧‧外引腳
PAS‧‧‧鈍化膜
PBL‧‧‧壓接滾珠
PBL1‧‧‧壓接滾珠
PBL2‧‧‧壓接滾珠
PBL3‧‧‧壓接滾珠
PD‧‧‧焊墊
PE‧‧‧基座部
PE1‧‧‧基座部
PE2‧‧‧基座部
PE3‧‧‧基座部
PF‧‧‧電鍍膜
RM‧‧‧樹脂
S‧‧‧焊料
SA1‧‧‧半導體裝置
SA2‧‧‧半導體裝置
SB‧‧‧焊錫球
SBMP‧‧‧柱形凸塊電極
STCH‧‧‧訂合部(新月形部)
TAB‧‧‧晶片搭載部
TCH‧‧‧焊炬電極
TE‧‧‧端子
W‧‧‧導線
WB‧‧‧配線基板
圖1係俯視觀察包含BGA封裝之半導體裝置之平面圖。
圖2係俯視觀察半導體裝置之圖,其係透視樹脂而表示之圖。
圖3係自背面觀察實施形態1之半導體裝置之圖。
圖4係沿圖1之A-A線切斷後之剖面圖。
圖5係表示製造包含BGA封裝之半導體裝置之步驟之流程的流程圖。
圖6係俯視觀察包含QFP封裝之半導體裝置之平面圖。
圖7係沿圖6之A-A線切斷後之剖面圖。
圖8係表示於半導體晶片上形成積體電路之後,製造包含QFP封裝之半導體裝置之步驟之流程的流程圖。
圖9(a)係表示於打線接合步驟中,使毛細管動作之情形 之部分剖面圖,(b)係表示使毛細管動作之情形之平面圖。
圖10係說明繼圖9之後之打線接合步驟之圖,(a)係表示使毛細管動作情形之部分剖面圖,(b)係表示使毛細管動作之情形之平面圖。
圖11係說明繼圖10之後之打線接合步驟之圖,(a)係表示使毛細管動作之情形之部分剖面圖,(b)係表示使毛細管動作之情形之平面圖。
圖12係說明繼圖11之後之打線接合步驟之圖,(a)係表示使毛細管動作之情形之部分剖面圖,(b)係表示使毛細管動作之情形之平面圖。
圖13係說明繼圖12之後之打線接合步驟之圖,(a)係表示使毛細管動作之情形之部分剖面圖,(b)係表示使毛細管動作之情形之平面圖。
圖14係說明繼圖13之後之打線接合步驟之圖,(a)係表示使毛細管動作之情形之部分剖面圖,(b)係表示使毛細管動作之情形之平面圖。
圖15係表示將毛細管之前端部配置於滾珠形成單元內之情形之圖。
圖16係表示於毛細管之前端部形成有初始滾珠之情形之圖。
圖17係表示將正常形狀之初始滾珠快速焊接至焊墊上之步驟之剖面圖。
圖18係表示將正常形狀之初始滾珠快速焊接至焊墊上之步驟之剖面圖。
圖19係表示將相對於導線而偏芯之初始滾珠快速焊接至焊墊上之步驟之剖面圖。
圖20係表示將相對於導線而偏芯之初始滾珠快速焊接至焊墊上之步驟之剖面圖。
圖21係表示將小直徑之初始滾珠快速焊接至焊墊上之步驟之剖面圖。
圖22係表示將小直徑之初始滾珠快速焊接至焊墊上之步驟之剖面圖。
圖23係表示將前端突起形狀之初始滾珠快速焊接至焊墊上之步驟之剖面圖。
圖24係表示將前端突起形狀之初始滾珠快速焊接至焊墊上之步驟之剖面圖。
圖25係表示本發明者研討之研討例1中之滾珠形成單元之構成之圖。特別是,(a)係表示研討例1中之滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖26係表示研討例1中之抗氧化氣體之流動之模式圖,(a)~(c)之各自係與圖25(a)~圖25(c)之各自對應之圖。
圖27係表示本發明者研討之研討例2中之滾珠形成單元之構成之圖。特別是,(a)係表示研討例2中之滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖28係表示研討例2中之抗氧化氣體之流動之模式圖,(a)~(c)之各自係與圖27(a)~圖27(c)之各自對應之圖。
圖29係表示實施形態1中之滾珠形成單元之構成之圖。特別是,(a)係表示實施形態1中之滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖30係表示實施形態1中之抗氧化氣體之流動之模式圖,(a)~(c)之各自係與圖29(a)~圖29(c)之各自對應之圖。
圖31係表示初始滾珠之滾珠直徑、與抗氧化氣體之氣體流量之關係之圖表。
圖32係表示變形例1中之滾珠形成單元之構成之圖。特別是,(a)係表示變形例1中之滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。(c)係沿(a)之B-B線切斷後之剖面圖。
圖33係表示變形例1中之其他滾珠形成單元之構成之圖。特別是,(a)係表示變形例1中之滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖34係表示變形例2中之滾珠形成單元之構成之圖。特別是,(a)係表示變形例2中之滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖35係表示變形例2中之其他滾珠形成單元之構成之圖。特別是,(a)係表示變形例2中之其他滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖36係表示變形例2中之其他滾珠形成單元之構成之圖。特別是,(a)係表示變形例2中之其他滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖37係表示變形例3中之滾珠形成單元之構成之圖。特別是,(a)係表示變形例3中之滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖38係表示變形例3中之其他滾珠形成單元之構成之圖。特別是,(a)係表示變形例3中之其他滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖39係表示實施形態2中之滾珠形成單元之構成之圖。特別是,(a)係表示實施形態2中之滾珠形成單元之一部分之平面圖,(b)係沿(a)之A-A線切斷後之剖面圖。又,(c)係沿(a)之B-B線切斷後之剖面圖。
圖40係表示實施形態2中之抗氧化氣體之流動之模式圖,(a)~(c)之各自係與圖39(a)~圖39(c)之各自對應之圖。
圖41係表示形成於半導體晶片上之複數個柱形凸塊電極之圖。
圖42係表示將形成有柱形凸塊電極之半導體晶片安裝於配線基板上之一例之圖。
BFP‧‧‧滾珠形成部
BFU‧‧‧滾珠形成單元
CAP‧‧‧毛細管
GIP‧‧‧氣體導入部
GOP‧‧‧氣體排出部
TCH‧‧‧焊炬電極
W‧‧‧導線

Claims (18)

  1. 一種半導體裝置之製造方法,其特徵在於包括以下步驟:(a)準備搭載有半導體晶片之配線板;(b)將毛細管之前端部配置於滾珠形成單元內之滾珠形成部;(c)將上述滾珠形成部之內部形成為抗氧化氣體環境,於上述滾珠形成部內使焊炬電極、與自上述毛細管之前端部引出之導電性導線之間放電,藉此於上述導電性導線之前端部形成初始滾珠;及(d)將上述初始滾珠焊接至上述半導體晶片上之焊墊上,藉此將上述導電性導線與上述半導體晶片電性連接;上述滾珠形成單元包含:上述滾珠形成部;將抗氧化氣體導入至上述滾珠形成部之氣體導入部;及自上述滾珠形成部排出上述抗氧化氣體之氣體排出部;上述氣體排出部係設置於與將上述抗氧化氣體導入至上述滾珠形成部之方向不同之方向上。
  2. 如請求項1之半導體裝置之製造方法,其中上述氣體排出部係設置於相對於上述抗氧化氣體之導入方向而為90°±45°之範圍內。
  3. 如請求項2之半導體裝置之製造方法,其中上述氣體排出部係設置於相對於上述抗氧化氣體之導入方向而為90°之位置上。
  4. 如請求項1之半導體裝置之製造方法,其中上述氣體排出部係貫通於上述滾珠形成單元之厚度方向。
  5. 如請求項4之半導體裝置之製造方法,其中上述氣體排 出部之寬度為上述毛細管之寬度以上。
  6. 如請求項5之半導體裝置之製造方法,其中上述氣體排出部之寬度為上述滾珠形成部之寬度以下。
  7. 如請求項1之半導體裝置之製造方法,其中於上述滾珠形成單元中,在相對於上述滾珠形成部而與上述氣體導入部對向之位置上設置有氣體積存部。
  8. 如請求項1之半導體裝置之製造方法,其中上述導電性導線係較金導線更易氧化之金屬導線。
  9. 如請求項8之半導體裝置之製造方法,其中上述導電性導線係銅導線。
  10. 如請求項1之半導體裝置之製造方法,其中上述抗氧化氣體係惰性氣體。
  11. 如請求項10之半導體裝置之製造方法,其中上述惰性氣體包含氮氣或氬氣。
  12. 如請求項1之半導體裝置之製造方法,其中上述抗氧化氣體係包含惰性氣體與還原性氣體之組成氣體。
  13. 如請求項12之半導體裝置之製造方法,其中上述組成氣體包含氮氣與氫氣。
  14. 如請求項1之半導體裝置之製造方法,其中上述滾珠形成單元包含絕緣樹脂。
  15. 如請求項14之半導體裝置之製造方法,其中上述絕緣樹脂係聚醯胺醯亞胺樹脂。
  16. 如請求項1之半導體裝置之製造方法,其中更包括以下步驟: 於上述(d)步驟之後,(e)將上述導電性導線焊接至上述配線板上之端子上,藉此將上述導電性導線與上述配線板電性連接;及(f)藉由密封體而密封上述半導體晶片、上述導電性導線、及上述配線板之一部分。
  17. 如請求項16之半導體裝置之製造方法,其中上述配線板係配線基板,上述配線板上之上述端子係焊盤端子。
  18. 如請求項16之半導體裝置之製造方法,其中上述配線板係引線框架,上述配線板上之上述端子係內引腳。
TW101116085A 2011-05-24 2012-05-04 半導體裝置之製造方法 TW201301417A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011115592A JP2012244093A (ja) 2011-05-24 2011-05-24 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW201301417A true TW201301417A (zh) 2013-01-01

Family

ID=47199672

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101116085A TW201301417A (zh) 2011-05-24 2012-05-04 半導體裝置之製造方法

Country Status (4)

Country Link
US (1) US8586416B2 (zh)
JP (1) JP2012244093A (zh)
CN (1) CN102800602A (zh)
TW (1) TW201301417A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI631673B (zh) * 2013-11-29 2018-08-01 青井電子股份有限公司 半導體裝置及半導體裝置之製造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627344B2 (en) * 2013-04-04 2017-04-18 Rohm Co., Ltd. Semiconductor device
JP5916814B2 (ja) 2014-08-06 2016-05-11 株式会社カイジョー ボンディング方法及びボンディング装置
TWI555104B (zh) * 2014-09-11 2016-10-21 矽品精密工業股份有限公司 打線裝置及排除不良銲線之方法
CN107297592A (zh) * 2016-04-15 2017-10-27 中芯国际集成电路制造(上海)有限公司 焊线机夹具系统
JP6699742B2 (ja) * 2016-09-20 2020-05-27 三菱電機株式会社 半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4390771A (en) * 1981-05-11 1983-06-28 Fairchild Camera & Instrument Corp. Bonding wire ball forming method and apparatus
JPS60244034A (ja) * 1984-05-18 1985-12-03 Mitsubishi Electric Corp ワイヤボンデイング用雰囲気形成装置
JPH0254947A (ja) * 1988-08-19 1990-02-23 Hitachi Ltd 半導体装置の組立方法およびそれに用いる装置
US5295619A (en) * 1992-05-22 1994-03-22 Rohm Co., Ltd. Method and apparatus for performing wire bonding by using solder wire
JP3286141B2 (ja) * 1995-12-27 2002-05-27 株式会社東芝 ワイヤボンディング装置
US5783866A (en) * 1996-05-17 1998-07-21 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
JP2000340599A (ja) * 1999-05-26 2000-12-08 Canon Inc ワイヤボンディング装置及び該ワイヤボンディング装置によるワイヤボンディング方法
US7628307B2 (en) * 2006-10-30 2009-12-08 Asm Technology Singapore Pte Ltd. Apparatus for delivering shielding gas during wire bonding
JP4392015B2 (ja) 2006-11-21 2009-12-24 株式会社カイジョー ワイヤボンディング装置
JP2009105114A (ja) 2007-10-22 2009-05-14 Shinkawa Ltd ワイヤボンディング装置及びボール形成方法
JP4369507B2 (ja) * 2007-12-07 2009-11-25 株式会社新川 ボンディング装置及びボンディング方法
CN101971314B (zh) * 2008-06-10 2013-10-09 库力索法工业公司 用于在引线接合操作中降低氧化的输气系统
JP4817341B2 (ja) * 2009-08-13 2011-11-16 株式会社カイジョー ワイヤボンディング装置
US8096461B2 (en) * 2009-09-03 2012-01-17 Advanced Semiconductor Engineering, Inc. Wire-bonding machine with cover-gas supply device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI631673B (zh) * 2013-11-29 2018-08-01 青井電子股份有限公司 半導體裝置及半導體裝置之製造方法

Also Published As

Publication number Publication date
CN102800602A (zh) 2012-11-28
US8586416B2 (en) 2013-11-19
US20120302009A1 (en) 2012-11-29
JP2012244093A (ja) 2012-12-10

Similar Documents

Publication Publication Date Title
US9991213B2 (en) Resin-encapsulated semiconductor device and its manufacturing method
TW201301417A (zh) 半導體裝置之製造方法
US20180005981A1 (en) Semiconductor device
US7017794B2 (en) Wire bonding method and wire bonding apparatus
JP3573133B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
US9230930B2 (en) Semiconductor device
JP5529992B1 (ja) ボンディング用ワイヤ
WO2013018238A1 (ja) ボールボンディングワイヤ
JP5671512B2 (ja) ボンディング用ワイヤ
TWI550740B (zh) 半導體裝置及其製造方法
JP2007504648A (ja) 絶縁ワイヤのワイヤボンディング及びワイヤボンディングに用いるキャピラリ
JP6407672B2 (ja) 半導体装置の製造方法
KR101334282B1 (ko) 반도체 패키지용 은-합금 와이어 및 이를 포함하는 반도체 패키지
US8247272B2 (en) Copper on organic solderability preservative (OSP) interconnect and enhanced wire bonding process
JP2013048169A (ja) ボールボンディング用ワイヤ
TWI508248B (zh) 有機保焊之互連上之銅及加強之打線接合製程
KR100853272B1 (ko) 구리 와이어 산화 방지용 불활성가스 분사장치
JP5339101B2 (ja) バンプ用ワイヤ
CN205319126U (zh) 一种打火杆烧球的氮气保护装置
KR20240122740A (ko) 본딩 와이어 및 반도체 장치
KR20130139406A (ko) 반도체 패키지용 은-합금 와이어 및 이를 포함하는 반도체 패키지
KR20130042310A (ko) 반도체 패키지
KR20090007533U (ko) 반도체 패키지 제조 장치