TWI508248B - 有機保焊之互連上之銅及加強之打線接合製程 - Google Patents
有機保焊之互連上之銅及加強之打線接合製程 Download PDFInfo
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- TWI508248B TWI508248B TW098120913A TW98120913A TWI508248B TW I508248 B TWI508248 B TW I508248B TW 098120913 A TW098120913 A TW 098120913A TW 98120913 A TW98120913 A TW 98120913A TW I508248 B TWI508248 B TW I508248B
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/2076—Diameter ranges equal to or larger than 100 microns
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- Condensed Matter Physics & Semiconductors (AREA)
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- Wire Bonding (AREA)
Description
相關申請案之交互參考
本申請案主張於2007年12月27日申請之美國專利申請案第11/965,252號及於2008年6月20日申請之美國臨時申請案第61/074,154號之權利,其揭示內容以引用方式併入本文中。
打線接合一般係一半導體晶片與一基板之間的一電連接之構件。該基板可(例如)係一印刷電路板(PCB)或一引線框架。打線接合通常涉及使用金(Au)打線、鋁(Al)打線、銅(Cu)打線、銀(Ag)打線或一合金打線組合以形成該電連接。例如,一種類型之打線接合製程係隔離式縫合球形接合(SSB)。SSB之優點係其提供較佳迴路控制並且可實現較低打線迴路輪廓。
Au打線通常係用作該半導體晶片與該基板之間的一電連接形式。通常,該Au打線係於一端接合至形成在該晶片上的一Al接合墊,且於另一端接合至該基板。在接合期間,該Au與Al交互擴散至彼此內,且可能導致高電阻及高熱產生。此接著可造成低接合可靠性及裝置性能。而且,金材料之劣性散熱特性可能在IC裝配件中引起過熱。
此外,Au材料具有低張力強度並且可能在封裝囊封期間引起劣性打線鬆弛、劣性打線偏移性能、劣性打線迴路輪廓及對長打線的不穩定性。而且,在Au打線接合中,需要在基板上塗布Ni及Au之一程序,以便實現在該Au打線與該基板之間的一可接受的電連接。
有鑑於金之前述缺點及昂貴成本,已對打線接合考慮其他材料,例如銅(Cu)。特定言之,銅與金材料相比具有較佳導電率,藉此增加裝置功率額定值並且改良封裝散熱。
在打線接合中使用銅之一挑戰係在該晶片上的接合墊表面或在該基板上的引線指狀物表面可能具有塗布於其上面的氧化材料,其可能降低接合可靠性。例如,當打線接合至一Cu接合墊時,該Cu接合墊容易氧化從而在該接合墊表面上形成一氧化物層。該氧化物層防止該打線與該Cu接合墊之間的有效接合。
從前述論述看,需要改良打線接合之性能,例如用於銅打線接合之SSB製程及透過OSP表面之銅打線接合。
依據本發明之一態樣,提供半導體封裝,其包括一第一基板;一第一半導體晶片,其係附著至該第一基板,其中該第一基板與該第一半導體晶片之至少一者具有塗布於一表面的至少一部分上之一OSP材料;以及一第一銅打線,其係透過該OSP材料打線接合至該第一基板與該第一半導體晶片之至少一者。
該第一基板可包括一引線指狀物,且該第一銅打線可係打線接合至該引線指狀物。
可採用該OSP材料塗布該引線指狀物。
該引線指狀物可包括銅、鋁及銀之至少一者。
該第一半導體晶片可包括一接合墊,且該第一銅打線可係打線接合至該接合墊。
可採用該OSP材料塗布該接合墊。
該接合墊可包括銅、鋁及銀之至少一者。
該半導體封裝可進一步包括:一第二半導體晶片,其係附著至該第一基板或至該第一半導體晶片,其中該第一基板與該第二半導體晶片的至少一者具有塗布於一表面的至少一部分上之OSP材料;以及一第二銅打線,其係透過該OSP材料打線接合至該第一基板與該第二半導體晶片的至少一者。
該第一半導體晶片與該第二導體晶片可係佈置於該第一基板之相對側上。
該半導體封裝可進一步包括:一第二基板,其具有塗布於一表面的至少一部分上之OSP材料;以及一第三銅打線,其係透過該第一基板之OSP材料打線接合至該第一基板之一引線指狀物以及透過該第二基板之OSP材料打線接合至該第二基板之一引線指狀物,其中該引線指狀物包含銅、鋁及銀之至少一者。
該第二導體晶片可係堆疊於該第一半導體晶片上。
該半導體封裝可進一步包括一第二基板,其具有塗布於一表面的至少一部分上之OSP材料;以及一第三銅打線,其係打線接合至該第二半導體晶片以及透過該第二基板之OSP材料打線接合至該第二基板之一引線指狀物,其中該第一半導體晶片係佈置於該第一基板上及該第二基板上,以及其中該引線指狀物包括銅、鋁及銀之至少一者。
該半導體封裝可進一步包括:一第三半導體晶片,其中該第一基板與該第三半導體晶片之至少一者具有塗布於一表面的至少一部分上之OSP材料;以及一第三銅打線,其係透過該OSP材料打線接合至該第一基板及該第三半導體晶片,其中該第三半導體晶片係堆疊於該第二半導體晶片上,且該第二半導體晶片係堆疊於該第一半導體晶片上。
相對於該半導體封裝之一斷面圖,該第三半導體晶片可比該第二半導體晶片更寬,且該第二半導體晶片可比該第一半導體晶片更寬。
相對於該半導體封裝之一斷面圖,該第一半導體晶片可比該第二半導體晶片更寬,且該第二半導體晶片可比該第三半導體晶片更寬。
在該銅打線係打線接合至該基板之情況下,該半導體封裝可進一步包括:一球形接合、縫合接合、帶接合、楔形接合及銅凸塊接合之一者。
在該銅打線係打線接合至該半導體晶片之情況下,該半導體封裝可進一步包括:一球形接合、縫合接合、帶接合、楔形接合及銅凸塊接合之一者。
依據一態樣,提供一種用於建構一半導體封裝之方法,該方法包括:(a)透過塗布於該基板上的一OSP材料將一銅打線之一端接合至一基板;以及(b)將該銅打線之一相對端打線接合至一半導體或晶片。
該基板可包括一引線指狀物;(a)可包括透過該OSP材料打線接合該銅打線以將該引線指狀物連接至該半導體晶片;以及該引線指狀物可包括銅、鋁及銀之至少一者。
可採用該OSP材料塗布該引線指狀物。
該第一半導體晶片可包括一接合墊;(b)可包括將該銅打線打線接合至該接合墊;以及該接合墊可包括銅、鋁及銀之至少一者。
可採用該OSP材料塗布該接合墊。
此外,(a)可包括在該基板上形成一球形接合、縫合接合、帶接合、楔形接合及銅凸塊接合之一者。
此外,(b)可包括在該半導體晶片上形成一球形接合、縫合接合、帶接合、楔形接合及銅凸塊接合之一者。
依據另一態樣,一種形成一裝置之方法包含提供該裝置之第一及第二接觸區域。將一球形焊塊形成於該第一接觸區域上。平滑化該球形焊塊以形成一平坦頂部表面。將一打線之一第一端接合至該第二接合區域,而將該打線之第二端接合至該球形焊塊之頂部表面。
透過參考以下說明及附圖將清楚本文所揭示之本發明的該等及其他目的以及優點及特徵。另外,應瞭解,本文所說明之各種具體實施例的特徵並非相互排斥,而是可存在於各種組合及置換內。
具體實施例一般係關於半導體封裝。例如,封裝具有藉由打線接合而接合之接觸區域。在一些具體實施例中,接觸區域之至少一者包含銅並且係用有機保焊(OSP)材料塗布。可採用銅打線接合接觸區域。此類半導體封裝廣泛用於電子裝置內。例如,電子裝置可係記憶體裝置、無線通信裝置或汽車控制裝置。該等裝置係併入至消費者產品內,例如消費者電子產品。將該等裝置併入其他類型之產品內亦有用。
圖1解說依據本發明之一範例性具體實施例之一半導體封裝。
如圖1中所示,依據一範例性具體實施例之半導體封裝包括接合墊1、銅打線2、引線指狀物3、黏性材料4、一半導體晶片5及一OSP基板6。
黏性材料4係用於提供半導體晶片5與OSP基板6之間的黏合。
用OSP材料塗布OSP基板6,並且透過OSP材料將銅打線2打線接合至OSP基板6之引線指狀物3。基板可係引線框架材料(例如Alloy 42、Cu7025、Olin 0194以及其他銅合金)、PCB、基板核心材料(例如BT832、Hitachi E679、Nanya NPG-150)、玻璃面板或陶瓷材料。基板6上之OSP塗層可係在整個表面之上、部分在表面上或在引線指狀物3上。引線指狀物3或接合墊1可包含銅、鋁、銀或其他導電材料。亦將銅打線2打線接合至半導體晶片5之接合墊1,且可用OSP材料塗布接合墊1。
圖2係圖1之半導體封裝之一等角視圖。如圖2中所示,銅打線接合能夠為半導體晶片5與位於晶粒之中心或周邊的接合墊1提供電連接。可相對於接合指狀物3在OSP基板6上的位置來相應地變更銅打線2之長度。
圖3係依據另一範例性具體實施例之一半導體封裝之一等角視圖。如圖3中所示,半導體封裝可包括與半導體晶片5垂直堆疊之第二半導體晶片7。第二半導體晶片7具有複數個接合墊1。銅打線接合在第二半導體晶片7之接合墊1與半導體晶片5之接合墊1間提供電連接。銅打線接合亦在第二半導體晶片7之接合墊1與OSP基板6之引線指狀物3間提供電連接。可用OSP材料塗布半導體晶片5及/或第二半導體晶片7之接合墊1。
圖4解說依據另一範例性具體實施例之一半導體封裝。如圖4中所示,半導體封裝可包括與第二半導體晶片7及第一半導體晶片5垂直堆疊之第三半導體晶片8。類似於半導體晶片5及第二半導體晶片7,第三半導體晶片8具有複數個接合墊1。銅打線接合在第三半導體晶片8之接合墊1與半導體晶片5及第二半導體晶片7的每一者之接合墊1間提供電連接。銅打線接合亦在第三半導體晶片8之接合墊1與OSP基板6之引線指狀物3間提供電連接。可用OSP材料塗布半導體晶片5、第二半導體晶片7及/或第三半導體晶片8之接合墊1。
圖5解說依據另一範例性具體實施例之一半導體封裝。如圖5中所示,可將第二半導體晶片7垂直堆疊於半導體晶片5上。而且,第二半導體晶片7及半導體晶片5相對於半導體封裝之斷面圖可具有近似相同之寬度。可用OSP材料塗布半導體晶片5及/或第二半導體晶片7之接合墊1。
圖6解說依據另一範例性具體實施例之一半導體封裝。如圖6中所示,可將第二半導體晶片7及半導體晶片5佈置於OSP基板6之相對側上。可用OSP材料塗布半導體晶片5及/或第二半導體晶片7之接合墊1。
圖7a解說依據另一範例性具體實施例之一半導體封裝。如圖7a所示,該半導體封裝可包括用OSP材料塗布之一第二OSP基板9。第二基板9上之OSP塗層可係在整個表面之上、部分在表面之上或在引線指狀物3上。半導體晶片5經配置使得其底部表面係佈置於OSP基板6及第二OSP基板9兩者上。因此,曝露半導體晶片5之底部表面的一部分。此曝露部分包括打線接合至OSP基板6及第二OSP基板9的引線指狀物3之複數個接合墊1,如圖7b中所示。第二半導體晶片7係配置於半導體晶片5上。可用OSP材料塗布半導體晶片5及/或第二半導體晶片7之接合墊1。第一OSP基板6與第二OSP基板9可係藉由一孔徑分離之一整合結構,該孔徑曝露半導體晶片5的底部表面之部分。
圖8解說依據另一範例性具體實施例之一半導體封裝。如圖8中所示,半導體晶片5、第二半導體晶片7及第三半導體晶片8可採用接近OSP基板6之遞減寬度垂直堆疊。可用OSP材料塗布半導體晶片5、第二半導體晶片7及/或第三半導體晶片8之接合墊1。
圖9解說依據另一範例性具體實施例之一半導體封裝。如圖9中所示,可將半導體晶片5及第二半導體晶片7佈置於OSP基板6之相對側上。而且,可將第三半導體晶片8佈置於第二OSP基板9上。銅打線接合可電性連接OSP基板6及第二OSP基板9之引線指狀物3。可用OSP材料塗布半導體晶片5、第二半導體晶片7及/或第三半導體晶片8之接合墊1。
圖10至16解說用於穿過OSP塗層的銅打線之各種接合組合。
圖10a及10b顯示OSP基板之經OSP塗布之引線指狀物上的銅凸塊焊塊及縫合凸塊焊塊之替代視圖。
圖11a及11b顯示一OSP基板之經OSP塗布之引線指狀物上的一銅縫合接合之替代視圖。
圖12a及12b顯示一半導體晶片之一經OSP塗布之接合墊上的一銅凸塊焊塊及縫合凸塊焊塊之替代視圖。
圖13a及13b顯示一OSP基板之經OSP塗布之引線指狀物上的一銅球形接合之替代視圖。
圖14a及14b顯示一半導體晶片之經OSP塗布之接合墊上的一銅球形接合之替代視圖。
圖15a及15b顯示在一半導體晶片之經OSP塗布的接合墊上之一銅單一凸塊及堆疊凸塊焊塊。
圖16及16b顯示經OSP塗布之接合墊上以及經OSP塗布之引線指狀物上的一銅球形接合。
圖17顯示依據一範例性具體實施例建構一半導體封裝之一方法。在操作S10中,透過塗布於OSP基板6上之OSP材料將銅打線2打線接合至OSP基板6之引線指狀物3。在操作S20中,將銅打線2打線接合至半導體晶片5之接合墊1。
再次參考圖1至9,本發明之一些具體實施例揭示將隔離式縫合球形接合(SSB)製程應用於(例如)半導體晶片與半導體封裝之基板間的銅打線接合。用於銅打線接合之此SSB製程亦可應用於其他半導體封裝內,如先前所介紹,例如包括第二半導體晶片、第三半導體晶片或更多半導體晶片之封裝,其中將銅打線打線接合至基板及半導體晶片。
圖18a至18d顯示用於將裝置330(例如晶粒)打線接合至封裝之載體或基板的製程300的一具體實施例。例如,將晶粒附著至基板。各種技術,例如膠帶或黏合劑,可用於將晶粒附著至基板。如所示,提供第一及第二接觸區域340及360。
該等區域之一者係提供於封裝基板上,而另一區域係提供於晶粒上。在一具體實施例中,將第一接觸區域340佈置於基板332上,並且將第二接觸區域360佈置於晶粒334上。例如,第一接觸區域係一基板引線指狀物,而第二接觸區域係一晶粒接合墊。其他類型之接觸區域亦有用。或者,將第一接觸區域佈置於晶粒上並且將第二接觸區域佈置於基板上。如所示,將第一接觸區域佈置於第二接觸區域下方。此可係由於將晶粒附著至基板之事實。其他配置亦有用,例如將基板上之接觸區域佈置於晶粒上之接觸區域下方或者使該等接觸區域共面。
接觸區域係藉由打線接合耦合。在一具體實施例中,接觸區域包含銅。在一具體實施例中,接觸區域之至少一者包含用OSP塗布之銅。例如,基板上之接觸區域包含用OSP塗布之銅,而晶粒上之第二接觸區域包含無OSP塗層之鋁。提供包含用OSP塗布之銅的接觸區域兩者亦可有用。在一具體實施例中,接觸區域係藉由銅打線接合耦合。接觸區域材料、塗層及導電打線之其他組態或組合亦可有用。
打線接合係藉由打線接合工具實行。打線接合工具包括毛細管370,透過該毛細管交織導電打線325。較佳的係,打線包含銅。其他類型之導電打線亦有用。一夾具(未顯示)定位或移動打線。為促進接合,可沿裝置之平面沿x-y軸以及垂直於裝置之平面的z軸平移毛細管。提供在x-y-z方向上平移裝置的平台或可平移毛細管及裝置之組合亦有用。
參考圖18a,在步驟302將導電球326a形成於導電打線之尖端處。在一具體實施例中,將銅球形形成於銅打線之尖端處。例如,可藉由電子點火(EFO)單元形成導電球。在將銅球形形成於銅打線之尖端上期間提供形成氣體至EFO單元。在一具體實施例中,形成氣體包含大約95%之氮及5%之氫。用於形成導電球之其他技術亦有用。
在步驟304毛細管將具有導電球之導電打線定位於第一接觸區域上以在第一接觸區域上形成球形焊塊。毛細管形成所需尺寸之球形焊塊。球形焊塊之所需尺寸可取決於(例如)接觸區域之大小及間距以及導電打線之厚度。可採用適當毛細管設計實現所需尺寸,如稍後將說明。在一具體實施例中,在步驟304毛細管藉由將接合壓力(BP)及超音波能量(USG)應用於處理時間(T)形成球形焊塊,以在第一接觸區域上形成球形焊塊326b。製程參數應形成球形焊塊,其係充分接合至銅接觸區域。在一具體實施例中,製程參數應形成穿透銅接觸區域之OSP塗層以及充分接合至銅的球形焊塊。例如,該等參數可取決於晶粒接合墊及基板引線指狀物之尺寸及組態,並且可對所需應用加以修改。
如圖18b中所示,在步驟306將毛細管遠離第一接觸區域重新定位。此致使打線與球形焊塊分離,從而使球形焊塊保留在第一接觸區域上。在一具體實施例中,採用平坦或平面表面形成球形焊塊。在一具體實施例中,平坦表面無尾部。在一具體實施例中,採用與第一接觸區域之平面大約共面之平坦表面形成球形焊塊。在其他具體實施例中,與第一接觸區域之平面成一角度地形成平坦表面。平面表面增加表面接合面積,頃發現其改良接合至該表面之打線的拉力強度。
在圖18c中,在已將毛細管與球形焊塊分離後,在步驟308將另一導電球327a形成於打線之尖端處。在步驟310,毛細管將導電球定位於第二接觸區域上以形成球形接合327b。
在步驟310將毛細管重新定位至第一接觸區域而無需將打線與第二接觸區域處之球形接合分離,如圖18d中所示。在一具體實施例中,從第二接觸區域至第一接觸區域之毛細管路徑在打線內形成迴路。例如,此製程可稱為「迴路化」。毛細管路徑經選擇以產生所需迴路形狀及高度。在第一接觸區域處,毛細管在球形焊塊327a上形成縫合接合。在形成縫合接合後,毛細管將銅打線與縫合接合分離,從而完成第一與第二接觸區域間之打線接合。
在一裝置內,一般存在藉由打線接合耦合的複數個第一及第二接觸區域。如上所說明,製程重複直至耦合所有第一及第二接觸區域。
球形焊塊之形狀及尺寸至少部分取決於毛細管設計。圖19顯示毛細管370之尖端471的一具體實施例。例如,毛細管可由陶瓷材料形成。用於形成可維持EFO製程的毛細管之另一類型之材料亦有用。毛細管之本體471可係直立(藉由虛線指示)且尖端以一角度逐漸變細。毛細管之中心包含電洞421,導電打線透過該電洞交織。電洞可至少在尖端處變窄,例如,以有利於引導其中之導電。電洞之其他組態亦可有用。電洞應足以容納導電打線。在一具體實施例中,電洞容納導電打線,例如直徑大約0.8mm之銅打線。容納其他大小之導電打線亦有用。
在尖端之底部,將電洞斜切。將電洞之底部斜切建立一內部有角度表面423。角度表面之底部對應於斜切直徑424,而表面角度對應於毛細管之圓錐角425。斜切直徑及圓錐角係毛細管之內部尺寸,其經設計以產生具有所需形狀之球形焊塊或球形接合。
另一方面,毛細管之外部尺寸影響縫合接合之形狀。例如,尖端431之外部半徑、面角432及尖端直徑409經選擇以產生所需縫合形狀。
圖20a至20c顯示製程2000,其用於平滑球形焊塊326b以在球形焊塊上形成平坦頂部或平臺表面327。藉由如圖20a至20c描述之製程發生於圖18a之步驟304後。參考圖20a,將毛細管370降低至接觸區域2030上。在較佳具體實施例中,以垂直於接觸區域之方向a降低毛細管。毛細管之降低壓低位於導電打線325之尖端處的導電球。壓低導電球之製程使導電球變形以形成耦合至導電打線的所需形狀之球形焊塊326a。
在圖20b中,在形成具有所需形狀之球形焊塊後,升高毛細管。在一具體實施例中,沿垂直於接觸區域之平面的方向b升高毛細管。在一具體實施例中,升高毛細管使得毛細管之底部與球形焊塊之平臺表面大致對準。在平臺表面有角度之情形中,將毛細管升高至大約等於平臺表面之最高點的位置。
在將毛細管升高至所需位置後,橫跨球形焊塊加以平移以將導電打線與球形焊塊分離。在一具體實施例中,在遠離球形焊塊之一側的第一及第二方向上平移毛細管。在一具體實施例中,第一及第二方向係橫跨球形焊塊之相對方向,如箭頭c及d所指示。在一具體實施例中,從c至d之平移方向係橫跨或沿接觸區域之平臺表面。例如,首先在c方向上平移毛細管,並且在d方向上橫跨接觸區域之平臺表面反轉。在一具體實施例中,在c方向上並且在橫跨接觸區域之平臺表面的相對或第二方向上各平移一次毛細管。在一或兩個方向上平移毛細管一次以上亦有用。在其他具體實施例中,可在不同或非相對方向上平移毛細管。平移製程將球形焊塊326b與導電打線分離並且形成平面表面327,如圖20c中所示。對於平坦表面係有角度之應用,沿與平坦表面相同之角度平移毛細管。
圖21顯示一EFO單元2100之一具體實施例。EFO單元包含形成室2160,該室具有開口2162以致能毛細管在其中定位以及從其中通過。形成室包括形成氣體入口2165及EFO源2175。
在操作中,將形成氣體注入至形成室內。在一具體實施例中,形成氣體包含還原大氣,其用於防止將在形成室內形成於毛細管之尖端處的導電球之氧化。在一具體實施例中,形成氣體包含氫及氮。在一具體實施例中,形成氣體包含大約5%之氫及大約95%之氮。為形成氣體提供其他百分比之氫及氮或成分之其他組成亦有用。
將毛細管定位於形成室內,且導電打線延伸超過尖端。一旦就位,EFO源在延伸超過毛細管之導電打線之末端釋放火花。火花熔化導電打線之曝露部分以在毛細管之尖端處形成導電球。一旦形成導電球,例如,毛細管通過形成室並且定位於接觸區域上以形成球形焊塊。
根據一具體實施例,EFO單元不包括形成氣體分配單元。即,導電球係形成並且接合至接觸區域而無需形成氣體分配單元。在習知接合製程中,接合接觸區域上之導電球需要形成氣體分配單元。例如,形成氣體分配單元包含近垂直管(NVT),其係佈置於接觸區域附近以在形成之導電球焊塊之上提供形成氣體,從而防止氧化。氧化可減小接合性能及可靠性。例如,球形焊塊之氧化可在SSB製程中影響縫合接合與球形焊塊之接合強度。然而,根據一具體實施例,可實現良好接合性能及可靠性而不需要形成氣體分配單元。避免具有形成氣體分配單元之需要可導致形成氣體之使用的節省,且因此導致與其相關聯之成本的節省。
實驗1
已對具有藉由打線接合耦合之第一及第二接觸區域的測試樣本進行實驗。第一接觸區域係包含鋁之基板引線指狀物。第二接觸區域係包含鋁之晶粒接合墊。ICU銅打線用於打線接合製程。ICU銅打線係來自Kulicke & Soffa之0.8mm ICU銅打線。銅打線之末端係採用球形接合耦合至第二接觸區域,而另一端係採用球形焊塊上之縫合接合(例如隔離式縫合接合)耦合至第一接觸區域。使用來自Kulicke & Soffa的具有Copper Kit及CU-FC-1049-P37 Cupra+之Maxum Ultra打線接合機實行打線接合。用於測試樣本上之打線接合製程類似於圖18a至18d中所說明者。
採用平坦表面形成第一接觸區域上之球形焊塊。為形成具有平坦表面之球形,在球形焊塊之上移動毛細管。平滑動作涉及橫跨球形焊塊將毛細管朝方向c並接著朝方向d移動,如對圖20b所顯示及說明。在第一組測試樣本中,使用NVT將形成氣體供應至球形焊塊。NVT將形成氣體分配於球形焊塊上。形成氣體包含95% N2
及5% H2
。在第二組測試樣本中,未藉由NVT將形成氣體供應至球形焊塊。
對形成於第一及第二組測試樣本之接觸區域上的球形接合及隔離式縫合接合實行縫合拉力及接合剪力測試。使用來自Dage Holdings Limited之Dage 4000接合測試器實行測試。
圖22a顯示採用形成氣體及無形成氣體之隔離式縫合接合的焊塊拉力強度。從圖22a可看出,採用形成氣體的隔離式縫合接合之平均拉力強度範圍從5.63至7.12克力,且具有6.32克力之平均值及2.94之CPK。無形成氣體的隔離式縫合接合之平均拉力強度範圍從5.12至6.82克力,且具有6.82克力之平均值及2.52之CPK。因此,可推斷球形焊塊之上之形成氣體未顯著改良位於第一接觸區域處之隔離式縫合接合的接合強度。
圖22b顯示採用形成氣體及無形成氣體之隔離式縫合接合的球形剪力強度。從圖22b可看出,採用形成氣體的隔離式縫合接合之平均球形剪力強度範圍從24.86至27.79克力,且平均值為26.26克力。無形成氣體的隔離式縫合接合之平均拉力強度範圍從23.97至27.87克力,且平均值為25.55克力。因此,與焊塊拉力測試之結果一致,球形焊塊之上之形成氣體未顯著改良位於第一接觸區域處之球形焊塊及隔離式縫合接合的接合剪力強度。
本發明之具體實施例亦係關於使用銅打線將第一接觸區域耦合至第二接觸區域,其中採用OSP材料塗布第一及/或第二接觸區域。使用銅打線耦合兩個接觸區域之製程類似於以上對圖18a至18d所顯示及說明者。該等區域之一者係提供於封裝基板上,而另一區域係提供於晶粒上。如所示,將第一接觸區域340佈置於基板332上,並且將第二接觸區域360佈置於晶粒334上。第一接觸區域可係用OSP(未顯示)塗布之銅引線指狀物,而第二接觸區域可係鋁晶粒接合墊。其他類型之接觸區域亦有用,例如採用或無OSP之鋁、銀或其他導電材料。基板可具有塗布於第二接觸區域上或於包括第二接觸區域的整個基板表面上之OSP。
參考圖18a,在步驟302將導電球326a形成於導電打線之尖端處。在一具體實施例中,將銅球形形成於銅打線之尖端處。例如,可藉由電子點火(EFO)單元形成導電球。在步驟304毛細管將具有導電球之導電打線定位於塗布OSP之第一接觸區域上以在第一接觸區域上形成球形焊塊。透過OSP層形成銅球形焊塊並且形成至第一接觸區域上。在繼續圖18(b)中所示之步驟前,毛細管在形成銅球形焊塊後沿對如圖20a至20c所顯示及說明的方向c及d移動,以在銅球形焊塊上形成平坦表面。
如圖18b中所示,在步驟306將毛細管遠離第一接觸區域重新定位。此致使打線與銅球形焊塊分離,從而使銅球形焊塊保留在第一接觸區域上。銅球形焊塊之平坦表面可係水平或與水平成一角度。
在圖18c中,在已將毛細管與銅球形焊塊分離後,在步驟308將另一導電球327a形成於打線之尖端處。在步驟310毛細管將導電球定位於第二接觸區域上以形成球形接合327b。
在步驟310將毛細管重新定位至第一接觸區域而無需將打線與第二接觸區域處之球形接合分離,如圖18d中所示。在第一接觸區域處,毛細管在球形焊塊327a上形成縫合接合。在形成縫合接合後,毛細管將銅打線與縫合接合分離,從而完成在第一與第二接觸區域間之打線接合。
實驗2
對兩個測試樣本單元1及單元2進行另一實驗。測試樣本包含具有晶粒大小10×10.5mm半導體封裝之精細間距球形格柵陣列(FBGA)。第一接觸區域係提供於基板上並且採用OSP塗布之銅引線指狀物。第二接觸區域係提供於晶粒上而無需OSP塗層之鋁接合墊。銅打線用於打線接合製程。銅打線係來自Kulicke & Soffa之24.um AFW-ICU銅打線。使用來自Kulicke & Soffa的具有Copper Kit及CU-FB-1031-P37毛細管之Maxum Ultra打線接合機實行打線接合。
毛細管將銅打線引導至填滿形成氣體之形成室內,其中EFO電極在毛細管之尖端處點燃銅打線之曝露部分,以形成銅球形。形成氣體包含95% N2
及5% H2
。毛細管接著退出形成室並且降低銅球形以接觸塗布OSP之第一接觸區域,從而形成球形焊塊。在形成球形焊塊時,在球形焊塊之上移動毛細管以建立平坦表面。平滑動作涉及將毛細管朝方向c並接著朝方向d移動,如對圖20b所顯示及說明(即,雙重平滑)。毛細管接著將銅打線朝第二接觸區域移動。依相同方式,將導電球形成於形成室內並且降低以在第二接觸區域上形成球形接合。其後將銅打線從位於第二接觸區域處之球形接合朝第一接觸區域迴路化,以在球形焊塊上形成縫合接合。使用相同製程形成測試樣本單元1及單元2兩者。
測試樣本單元1及單元2經測試以使用從Dage Holdings Limited獲得之Dage 4000接合測試器測量其接合性能。圖23顯示測試結果。特定言之,焊塊拉力測試係在第一及第二接觸區域上進行。例如,第一接觸區域上之焊塊拉力測試測量焊球形之剪力強度(焊塊上之球形剪力測試);第二接觸區域上之焊塊拉力測試測量球形接合之剪力強度(球形上之球形剪力測試)。此外,對第一接觸區域內之球形焊塊上的縫合接合進行縫合拉力測試。
如圖23中所示,用於單元1之球形接合的平均剪力強度範圍從25.40至28.70克力,且平均值為26.68克力。用於單元2之球形接合的平均剪力強度範圍從24.40至27.50克力,且平均值為25.98克力。用於單元1之隔離式縫合接合的平均剪力強度範圍從21.50至45.80克力,且平均值為41.35克力。用於單元2之隔離式縫合接合的平均剪力強度範圍從35.70至46.70克力,且平均值為44.04克力。用於單元1之隔離式縫合接合的平均縫合拉力強度範圍從18.40至19.70克力,且平均值為18.93克力。用於單元2之隔離式縫合接合的平均拉力強度範圍從17.50至19.60克力,且平均值為18.62克力。
圖23中顯示決定良好接合強度之典型規格(SPEC)。如圖所清楚顯示,獲得之球形剪力強度高於17克力之規格。獲得之縫合拉力強度高於7克力之規格。從圖23可看出,獲得之球形大小亦在指定範圍內。
圖24顯示單元1及單元2上之各種類型之測試的結果。潮濕敏感度位準測試涉及在30℃、60%房間濕度下經歷192小時之MSL 3測試,然後在260℃下回焊3次之封裝。在150批半導體封裝中,僅2批未通過測試。溫度循環測試涉及使封裝經歷-55℃至125℃之溫度循環達500及1000個循環。所有批次均通過溫度循環測試。高溫儲存測試涉及將封裝儲存於150℃之溫度下達500小時及1000小時。所有批次均通過高溫儲存測試。
使用OSP上的Cu打線接合允許消除在進行Au打線接合以實現半導體晶片與PCB之間的可接受電連接時所需要之Ni及Au塗布製程。透過OSP之Cu打線接合不限於在基板上塗布OSP。OSP亦可用於塗布位於半導體晶片上的接合墊,藉此允許透過Cu打線來連接接合墊與PCB。而且,可在引線指狀物上或者在基板的部分或整個表面之上形成基板上的OSP塗層。
與Au打線接合相比,較慢金屬間生長發生於Cu打線接合中。此導致較低電阻及較低熱產生。此亦增強接合可靠性及裝置性能。
銅材料與金材料相比具有較佳導電率,藉此增加裝置功率額定值並且改良封裝散熱。此極佳的散熱特性可防止IC在電性測試及應力環境測試期間過熱。
銅打線呈現極佳的可製造性特性,例如與金打線相比較高的張力強度及伸長率,從而在封裝囊封期間導致改良的頸部強度、改良的打線鬆弛及打線偏移性能、極佳的打線迴路輪廓及對長打線的穩定性。其為精細間距封裝應用提供一極佳替代方案。精細間距表示當位於半導體晶片上的2個接合墊彼此十分接近(例如,2個相鄰接合墊之間的10μm間隔)時,在2個相鄰打線之間的緊密近接。
SSB製程傳統上需要在將近垂直管形成於接觸區域上後使用其在球形焊塊之上傳遞形成氣體,以防止焊塊氧化,該焊塊被認為影響待接合至球形焊塊的縫合接合之接合強度。本發明者令人訝異地發現球形焊塊上之形成氣體未顯著改良接合強度。有利的係,此可造成與來自近垂直管的形成氣體相關聯之成本的節省。
OSP塗層用作在晶片接合墊(由銅、鋁、銀等形成)或基板之上之一抗氧化層。此外,在銅(Cu)打線係接合至Cu接合墊之情況下,由於其單金屬系統,因而與諸如接合至Al接合墊的金打線之金屬間系統相比提供更佳的可靠性。然而,將銅打線直接接合至OSP表面之習知方法具有其問題,即打線接合可能無法透過OSP有效接合至接合墊或引線指狀物。本發明因此藉由使用SSB及/或平滑特徵將銅打線接合至OSP表面改善此問題。應明白,此亦可應用於未塗布OSP之表面以導致銅打線與表面之有效接合。
本發明可以其他特定形式體現而不背離其精神或本質特性。因此,前述具體實施例在各方面係視為解說性而非限制本文所說明的發明。本發明之範疇因此係由隨附申請專利範圍而非由前述說明定義定義,且在申請專利範圍之等效意義和範圍之內的所有變化均係包含於本發明中。
1...接合墊
2...銅打線
3...引線指狀物
4...黏性材料
5...半導體晶片
6...OSP基板
7...第二半導體晶片
8...第三半導體晶片
9...第二OSP基板
325...導電打線
326a...導電球
326b...球形焊塊
327...平臺表面
327a...導電球/球形焊塊
327b...球形接合
330...裝置
332...基板
334...晶粒
340...第一接觸區域
360...第二接觸區域
370...毛細管
409...尖端直徑
421...電洞
423...內部有角度表面
424...斜切直徑
425...圓錐角
431...尖端
432...面角
471...尖端/本體
2030...接觸區域
2100...EFO單元
2160...形成室
2162...開口
2165...形成氣體入口
2175...EFO源
在圖式中,相似參考字元一般指所有不同視圖中的相同零件。而且,該等圖式並不一定按比例繪製,而一般強調解說本發明之原理。在以下說明中,參考以下圖式說明本發明之各種具體實施例,其中:
圖1解說依據本發明之一範例性具體實施例之一半導體封裝;
圖2係圖1之半導體封裝之一等角視圖;
圖3係依據本發明之另一範例性具體實施例之一半導體封裝之一等角視圖;
圖4解說依據本發明之另一範例性具體實施例之一半導體封裝;
圖5解說依據本發明之另一範例性具體實施例之一半導體封裝;
圖6解說依據本發明之另一範例性具體實施例之一半導體封裝;
圖7a解說依據本發明之另一範例性具體實施例之一半導體封裝,且圖7b解說打線接合至圖7a之半導體封裝的基板之引線指狀物的銅打線;
圖8解說依據本發明之另一範例性具體實施例之一半導體封裝;
圖9解說依據本發明之另一範例性具體實施例之一半導體封裝;
圖10a及10b顯示一OSP基板之經OSP塗布之引線指狀物上的一銅凸塊焊塊及縫合凸塊焊塊之替代視圖;
圖11a及11b顯示一OSP基板之經OSP塗布之引線指狀物上的一銅縫合接合之替代視圖;
圖12a及12b顯示一半導體晶片之經OSP塗布之墊上的一銅凸塊焊塊及縫合凸塊焊塊之替代視圖;
圖13a及13b顯示一OSP基板之經OSP塗布之引線指狀物上的一銅球形接合之替代視圖;
圖14a及14b顯示一半導體晶片之經OSP塗布之墊上的一銅球形接合之替代視圖;
圖15a及15b顯示一半導體晶片之經OSP塗布之接合墊上的一銅單一凸塊及堆疊凸塊焊塊;
圖16及16b顯示經OSP塗布之接合墊上以及經OSP塗布之引線指狀物上的一銅球形接合;
圖17顯示依據本發明之一範例性具體實施例建構一半導體封裝之一方法;
圖18a至18d顯示用於接合第一及第二接觸區域之一製程的一具體實施例;
圖19顯示用於接合之一毛細管的一具體實施例;
圖20a至20c解說一焊塊形成製程之一具體實施例;
圖21顯示一EFO子系統之一具體實施例;
圖22a顯示用於採用形成氣體及無需形成氣體沖洗形成於鋁接觸區域上之隔離式縫合接合的焊塊拉力比較資料;
圖22b顯示用於採用形成氣體及無需形成氣體沖洗形成於鋁接觸區域上之隔離式縫合接合的球形剪力比較資料;
圖23顯示用於形成於經OSP塗布之接觸區域上之隔離式縫合接合的球形剪力及縫合拉力比較資料;以及
圖24顯示在測試樣本上實行之各種類型之可靠性測試的結果。
325...導電打線
326b...球形焊塊
327b...球形接合
330...裝置
332...基板
334...晶粒
340...第一接觸區域
Claims (18)
- 一種形成一裝置之方法,其包含:提供該裝置之第一及第二接觸區域,其中該第一接觸區域包含用一有機保焊材料塗佈之銅;在該第一接觸區域上形成一球形焊塊,其中形成該球形焊塊包含:透過一接合工具之一毛細管穿過一打線,其中該打線之一尖端被設置為超過該毛細管之一尖端;將該毛細管佈置於具有一形成氣體之一形成室內;及在該室內形成一火花以在該打線之該尖端上形成該球形焊塊;平滑化該球形焊塊以在該球形焊塊上形成無一尾部之一平坦頂部表面,其中平滑化該球形焊塊包含:將該毛細管與該球形焊塊一起定位於該第一接觸區域上;處理以形成該球形焊塊,其穿透該有機保焊材料並且充分接合至該第一接觸區域;在一第一方向上轉移該毛細管以遠離該球形焊塊;及在一第二方向上向後轉移該毛細管橫跨該球形焊塊以形成該球形焊塊之該平坦頂部表面,該平坦頂部表面無一尾部(devoid of a tail),其中該等轉移係沿著與該平坦頂部表面相同之角度;將該打線之一第一端接合至該第二接觸區域;以及將該打線之一第二端接合至該球形焊塊之該平坦頂部 表面。
- 如請求項1之方法,其中該裝置包含一半導體封裝,其包含:一基板;一晶粒,其係附著至該基板;以及其中該第一接觸區域包含佈置於該基板上之一引線指狀物並且該第二接觸區域包含該晶粒上之一晶粒接合墊。
- 如請求項2之方法,其中避免將形成氣體分配於該第一接觸區域上之該球形焊塊上。
- 如請求項2之方法,其中該打線包含銅。
- 如請求項3之方法,其中該打線包含銅。
- 如請求項4之方法,其中避免將形成氣體分配於該第一接觸區域上之該球形焊塊上。
- 如請求項1之方法,其中該打線包含銅。
- 如請求項7之方法,其中避免將形成氣體分配於該第一接觸區域上之該球形焊塊上。
- 如請求項1之方法,其中避免將形成氣體分配於該第一接觸區域上之該球形焊塊上。
- 如請求項9之方法,其中:將該打線之該第一端接合至該第二接觸區域包括:將該毛細管佈置於該第二接觸區域上方;以及在該第二接觸區域上形成一導電球,以形成一球形接合,該球形接合具有延伸自該導電球之該打線之該第一端;及 將該打線之一第二端接合至該球形焊塊之該平坦頂部表面包括:將該毛細管重新定位至該第一接觸區域,以在該球形焊塊之該平坦頂部表面上形成一縫合接合(stitch bond)而無需將該打線與該第二接觸區域處之該球形接合分離。
- 一種形成一裝置之方法,其包含:提供該裝置之第一及第二接觸區域,其中該第一接觸區域包含用一有機保焊材料塗佈之銅;在該第一接觸區域上形成一球形焊塊;平滑化該球形焊塊以在該球形焊塊上形成無一尾部之一平坦頂部表面,其中平滑化該球形焊塊包含:處理以形成具有該平坦頂部表面之該球形焊塊,該平坦頂部表面無一尾部,且穿透該有機保焊材料並且充分接合至該第一接觸區域;將一打線之一第一端接合至該第二接觸區域;將該打線之一第二端接合至該球形焊塊之該平坦頂部表面;以及其中在該等第一及第二接觸區域之接合期間避免將形成氣體分配於該第一接觸區域上之該球形焊塊上。
- 如請求項11之方法,其中該打線包含銅。
- 如請求項11之方法,其中形成該球形焊塊包含:透過一接合工具之一毛細管穿過一打線,其中該打線之一尖端被設置為超過該毛細管之一尖端;將該毛細管佈置於具有一形成氣體之一形成室內;及 在該室內形成一火花以在該打線之該尖端上形成該球形焊塊。
- 如請求項11之方法,其中平滑化該球形焊塊更包含:將一毛細管與該球形焊塊一起定位於該第一接觸區域上;在一第一橫向方向上轉移該毛細管以遠離該球形焊塊;及在一第二橫向方向上向後轉移該毛細管橫跨該球形焊塊以形成該平坦頂部表面,該平坦頂部表面無尾部。
- 一種裝置,其包含:該裝置之第一及第二接觸區域,其中該第一接觸區域包含用一有機保焊材料塗佈之銅;一球形焊塊,其係佈置於該第一接觸區域上,其中該球形焊塊包含無一尾部之一平坦頂部表面,及該球形焊塊穿透該有機保焊材料並且充分接合至該第一接觸區域;將一打線之一第一端接合至該第二接觸區域;以及將該打線之一第二端接合至該球形焊塊之該平坦頂部表面,該平坦頂部表面無一尾部,其中該平坦頂部表面增強該打線之該第二端的接合強度。
- 如請求項15之裝置,其中該打線包含銅。
- 如請求項15之裝置,其進一步包含一半導體封裝,該半導體封裝包含:一基板; 一晶粒,其係附著至該基板;以及其中該第一接觸區域包含佈置於該基板上之一引線指狀物並且該第二接觸區域包含該晶粒上之一晶粒接合墊。
- 如請求項15之裝置,其中該第二接觸區域包括一導電球,該導電球具有延伸自該導電球之該打線之該第一端,以在該第二接觸區域上形成一球形接合,且該打線之該第二端形成一縫合接合,該縫合接合被接合至該第一接觸區域上之該球形焊塊之該平坦頂部表面。
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US10121742B2 (en) * | 2017-03-15 | 2018-11-06 | Amkor Technology, Inc. | Method of forming a packaged semiconductor device using ganged conductive connective assembly and structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US6610601B2 (en) * | 1999-03-31 | 2003-08-26 | Lam Research Corporation | Bond pad and wire bond |
US20040152292A1 (en) * | 2002-09-19 | 2004-08-05 | Stephen Babinetz | Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine |
TW200741925A (en) * | 2006-04-26 | 2007-11-01 | Kulicke & Soffa Ind Inc | Wire bonding machine and method for processing a semiconductor device |
-
2009
- 2009-06-22 SG SG200904295-3A patent/SG158048A1/en unknown
- 2009-06-22 TW TW098120913A patent/TWI508248B/zh not_active IP Right Cessation
- 2009-06-22 DE DE102009029844A patent/DE102009029844A1/de not_active Withdrawn
- 2009-06-22 SG SG2011092343A patent/SG177212A1/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6610601B2 (en) * | 1999-03-31 | 2003-08-26 | Lam Research Corporation | Bond pad and wire bond |
US20040152292A1 (en) * | 2002-09-19 | 2004-08-05 | Stephen Babinetz | Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine |
TW200741925A (en) * | 2006-04-26 | 2007-11-01 | Kulicke & Soffa Ind Inc | Wire bonding machine and method for processing a semiconductor device |
Also Published As
Publication number | Publication date |
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DE102009029844A1 (de) | 2010-02-18 |
TW201007911A (en) | 2010-02-16 |
SG158048A1 (en) | 2010-01-29 |
SG177212A1 (en) | 2012-01-30 |
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