TW201301257A - 訊號處理電路、訊號處理方法及顯示設備 - Google Patents

訊號處理電路、訊號處理方法及顯示設備 Download PDF

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Publication number
TW201301257A
TW201301257A TW101109666A TW101109666A TW201301257A TW 201301257 A TW201301257 A TW 201301257A TW 101109666 A TW101109666 A TW 101109666A TW 101109666 A TW101109666 A TW 101109666A TW 201301257 A TW201301257 A TW 201301257A
Authority
TW
Taiwan
Prior art keywords
signal
read
signal processing
image
processing circuit
Prior art date
Application number
TW101109666A
Other languages
English (en)
Chinese (zh)
Inventor
Mikio Ishii
Masahiro Take
Shoji Kosuge
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of TW201301257A publication Critical patent/TW201301257A/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Picture Signal Circuits (AREA)
TW101109666A 2011-03-30 2012-03-21 訊號處理電路、訊號處理方法及顯示設備 TW201301257A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011074348A JP2012208342A (ja) 2011-03-30 2011-03-30 信号処理回路と信号処理方法および表示装置

Publications (1)

Publication Number Publication Date
TW201301257A true TW201301257A (zh) 2013-01-01

Family

ID=46926598

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101109666A TW201301257A (zh) 2011-03-30 2012-03-21 訊號處理電路、訊號處理方法及顯示設備

Country Status (5)

Country Link
US (1) US20120249565A1 (enExample)
JP (1) JP2012208342A (enExample)
KR (1) KR20120112059A (enExample)
CN (1) CN102737618A (enExample)
TW (1) TW201301257A (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI463432B (zh) * 2012-10-05 2014-12-01 創惟科技股份有限公司 圖像資料處理方法
KR101695007B1 (ko) * 2012-12-14 2017-01-10 한국전자통신연구원 대용량 비디오 데이터의 병렬 처리 장치 및 방법
JP6034703B2 (ja) * 2013-01-21 2016-11-30 サターン ライセンシング エルエルシーＳａｔｕｒｎ Ｌｉｃｅｎｓｉｎｇ ＬＬＣ 変換回路、画像処理装置および変換方法
KR20140112892A (ko) * 2013-03-14 2014-09-24 삼성디스플레이 주식회사 터치 스크린 패널 및 그 제조 방법
JP2015001549A (ja) * 2013-06-13 2015-01-05 ソニー株式会社 信号出力装置、信号出力方法、及び映像表示装置
WO2015136571A1 (ja) 2014-03-11 2015-09-17 パナソニック液晶ディスプレイ株式会社 表示装置及びその駆動方法
KR102631190B1 (ko) * 2016-10-31 2024-01-29 엘지디스플레이 주식회사 유기 발광 표시 장치 및 이의 구동 방법
KR102783269B1 (ko) * 2019-10-21 2025-03-20 삼성디스플레이 주식회사 구동 컨트롤러 및 그것을 포함하는 표시 장치
WO2021124729A1 (ja) * 2019-12-17 2021-06-24 パナソニックＩｐマネジメント株式会社 表示制御システム、移動体、表示制御方法、表示装置、表示方法及びプログラム
CN119603419B (zh) * 2024-12-19 2025-11-25 深圳曦华科技有限公司 芯片以及显示设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2907988B2 (ja) * 1990-10-05 1999-06-21 株式会社日立製作所 ワイドテレビジョン受信機
US5841430A (en) * 1992-01-30 1998-11-24 Icl Personal Systems Oy Digital video display having analog interface with clock and video signals synchronized to reduce image flicker
WO1998007272A1 (en) * 1996-08-13 1998-02-19 Fujitsu General Limited Pll circuit for digital display device
JPH1055161A (ja) * 1996-08-13 1998-02-24 Fujitsu General Ltd デジタル映像処理装置用のｐｌｌ回路
US6333750B1 (en) * 1997-03-12 2001-12-25 Cybex Computer Products Corporation Multi-sourced video distribution hub
US5914757A (en) * 1997-04-21 1999-06-22 Philips Electronics North America Corporation Synchronization of multiple video and graphic sources with a display using a slow PLL approach
JP3582382B2 (ja) * 1998-11-13 2004-10-27 株式会社日立製作所 マルチディスプレイ装置の表示制御装置、表示装置及びマルチディスプレイ装置
JP2000232649A (ja) * 1998-12-10 2000-08-22 Fujitsu Ltd Ｍｐｅｇビデオ復号器及びｍｐｅｇビデオ復号方法
JP2006148765A (ja) * 2004-11-24 2006-06-08 Seiko Epson Corp テレビ受像機
JP5099406B2 (ja) * 2006-11-14 2012-12-19 ソニー株式会社 信号処理回路および方法
JP5106893B2 (ja) * 2007-03-20 2012-12-26 三菱電機株式会社 表示装置
JP5335273B2 (ja) * 2008-04-17 2013-11-06 キヤノン株式会社 メモリ制御装置及びメモリの制御方法
JP2011061323A (ja) * 2009-09-07 2011-03-24 Toshiba Corp 同期信号制御回路及び表示装置

Also Published As

Publication number Publication date
CN102737618A (zh) 2012-10-17
JP2012208342A (ja) 2012-10-25
US20120249565A1 (en) 2012-10-04
KR20120112059A (ko) 2012-10-11

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