KR20120112059A - 신호 처리 회로, 신호 처리 방법 및 표시 장치 - Google Patents

신호 처리 회로, 신호 처리 방법 및 표시 장치 Download PDF

Info

Publication number
KR20120112059A
KR20120112059A KR1020120029400A KR20120029400A KR20120112059A KR 20120112059 A KR20120112059 A KR 20120112059A KR 1020120029400 A KR1020120029400 A KR 1020120029400A KR 20120029400 A KR20120029400 A KR 20120029400A KR 20120112059 A KR20120112059 A KR 20120112059A
Authority
KR
South Korea
Prior art keywords
signal
read
signal processing
frame
processing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020120029400A
Other languages
English (en)
Korean (ko)
Inventor
미끼오 이시이
마사히로 다께
쇼지 고스게
Original Assignee
소니 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소니 주식회사 filed Critical 소니 주식회사
Publication of KR20120112059A publication Critical patent/KR20120112059A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Picture Signal Circuits (AREA)
KR1020120029400A 2011-03-30 2012-03-22 신호 처리 회로, 신호 처리 방법 및 표시 장치 Withdrawn KR20120112059A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011074348A JP2012208342A (ja) 2011-03-30 2011-03-30 信号処理回路と信号処理方法および表示装置
JPJP-P-2011-074348 2011-03-30

Publications (1)

Publication Number Publication Date
KR20120112059A true KR20120112059A (ko) 2012-10-11

Family

ID=46926598

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120029400A Withdrawn KR20120112059A (ko) 2011-03-30 2012-03-22 신호 처리 회로, 신호 처리 방법 및 표시 장치

Country Status (5)

Country Link
US (1) US20120249565A1 (enExample)
JP (1) JP2012208342A (enExample)
KR (1) KR20120112059A (enExample)
CN (1) CN102737618A (enExample)
TW (1) TW201301257A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140077754A (ko) * 2012-12-14 2014-06-24 한국전자통신연구원 대용량 비디오 데이터의 병렬 처리 장치 및 방법

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI463432B (zh) * 2012-10-05 2014-12-01 Genesys Logic Inc 圖像資料處理方法
JP6034703B2 (ja) * 2013-01-21 2016-11-30 サターン ライセンシング エルエルシーＳａｔｕｒｎ Ｌｉｃｅｎｓｉｎｇ ＬＬＣ 変換回路、画像処理装置および変換方法
KR20140112892A (ko) * 2013-03-14 2014-09-24 삼성디스플레이 주식회사 터치 스크린 패널 및 그 제조 방법
JP2015001549A (ja) * 2013-06-13 2015-01-05 ソニー株式会社 信号出力装置、信号出力方法、及び映像表示装置
WO2015136571A1 (ja) * 2014-03-11 2015-09-17 パナソニック液晶ディスプレイ株式会社 表示装置及びその駆動方法
KR102631190B1 (ko) * 2016-10-31 2024-01-29 엘지디스플레이 주식회사 유기 발광 표시 장치 및 이의 구동 방법
KR102783269B1 (ko) * 2019-10-21 2025-03-20 삼성디스플레이 주식회사 구동 컨트롤러 및 그것을 포함하는 표시 장치
CN113348436B (zh) * 2019-12-17 2023-07-25 松下知识产权经营株式会社 显示控制系统及方法、显示装置及方法、移动体、记录介质
CN119603419B (zh) * 2024-12-19 2025-11-25 深圳曦华科技有限公司 芯片以及显示设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2907988B2 (ja) * 1990-10-05 1999-06-21 株式会社日立製作所 ワイドテレビジョン受信機
US5841430A (en) * 1992-01-30 1998-11-24 Icl Personal Systems Oy Digital video display having analog interface with clock and video signals synchronized to reduce image flicker
CA2263221C (en) * 1996-08-13 2002-05-28 Masanori Kurita Pll circuit for digital display apparatus
JPH1055161A (ja) * 1996-08-13 1998-02-24 Fujitsu General Ltd デジタル映像処理装置用のｐｌｌ回路
US6333750B1 (en) * 1997-03-12 2001-12-25 Cybex Computer Products Corporation Multi-sourced video distribution hub
US5914757A (en) * 1997-04-21 1999-06-22 Philips Electronics North America Corporation Synchronization of multiple video and graphic sources with a display using a slow PLL approach
JP3582382B2 (ja) * 1998-11-13 2004-10-27 株式会社日立製作所 マルチディスプレイ装置の表示制御装置、表示装置及びマルチディスプレイ装置
JP2000232649A (ja) * 1998-12-10 2000-08-22 Fujitsu Ltd Ｍｐｅｇビデオ復号器及びｍｐｅｇビデオ復号方法
JP2006148765A (ja) * 2004-11-24 2006-06-08 Seiko Epson Corp テレビ受像機
JP5099406B2 (ja) * 2006-11-14 2012-12-19 ソニー株式会社 信号処理回路および方法
JP5106893B2 (ja) * 2007-03-20 2012-12-26 三菱電機株式会社 表示装置
JP5335273B2 (ja) * 2008-04-17 2013-11-06 キヤノン株式会社 メモリ制御装置及びメモリの制御方法
JP2011061323A (ja) * 2009-09-07 2011-03-24 Toshiba Corp 同期信号制御回路及び表示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140077754A (ko) * 2012-12-14 2014-06-24 한국전자통신연구원 대용량 비디오 데이터의 병렬 처리 장치 및 방법

Also Published As

Publication number Publication date
JP2012208342A (ja) 2012-10-25
CN102737618A (zh) 2012-10-17
US20120249565A1 (en) 2012-10-04
TW201301257A (zh) 2013-01-01

Similar Documents

Publication Publication Date Title
KR20120112059A (ko) 신호 처리 회로, 신호 처리 방법 및 표시 장치
US8823721B2 (en) Techniques for aligning frame data
US10049642B2 (en) Sending frames using adjustable vertical blanking intervals
CN103220478B (zh) 一种显示装置和电视机
TWI579819B (zh) 顯示驅動器積體電路及其顯示資料處理方法
KR101861723B1 (ko) 티어링과 플리커를 방지하기 위한 동기 신호를 조절하는 장치들과 그 방법
TWI488172B (zh) 多螢幕顯示
KR101885331B1 (ko) 디스플레이 드라이버의 동작 방법과 상기 디스플레이 드라이버를 포함하는 시스템
US20110157202A1 (en) Techniques for aligning frame data
US8026919B2 (en) Display controller, graphics processor, rendering processing apparatus, and rendering control method
CN107924666A (zh) 显示控制装置、显示装置、显示控制装置的控制方法以及控制程序
CN103597818A (zh) 用于动态配置显示设备中的串行数据链路的系统和方法
CN101000755A (zh) 多屏显示拼接控制器
CN110460784A (zh) 显示通道的切换方法及模块、显示驱动装置、显示设备
TWI520568B (zh) 三維顯示控制裝置及方法
JP2015096920A (ja) 画像処理装置および画像処理システムの制御方法
CN119788835A (zh) 基于fpga的立体图像显示系统及方法
JP2015125411A (ja) 映像処理装置
US20070195111A1 (en) Device and method for overlapping multi-channel digital display signals
JP4708528B2 (ja) 映像信号変換装置
TWI633789B (zh) 資料讀取方法、資料傳送方法及相關行動裝置
CN101901591B (zh) 具有多个控制器的显示装置以及视频数据处理方法
JP6027739B2 (ja) 映像処理装置、映像処理方法、映像処理システムおよびプログラム
JP4781688B2 (ja) 映像信号伝送方法及び映像信号伝送装置
CN112785980B (zh) 显示驱动装置、方法及oled显示装置

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20120322

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid