WO2020156284A1 - 显示驱动装置、其控制方法及显示装置 - Google Patents

显示驱动装置、其控制方法及显示装置 Download PDF

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Publication number
WO2020156284A1
WO2020156284A1 PCT/CN2020/073025 CN2020073025W WO2020156284A1 WO 2020156284 A1 WO2020156284 A1 WO 2020156284A1 CN 2020073025 W CN2020073025 W CN 2020073025W WO 2020156284 A1 WO2020156284 A1 WO 2020156284A1
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Prior art keywords
frame
displayed
display data
processing chip
memory
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PCT/CN2020/073025
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English (en)
French (fr)
Inventor
马希通
耿立华
李彦孚
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京东方科技集团股份有限公司
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Priority to JP2020573176A priority Critical patent/JP2022518084A/ja
Priority to EP20749432.9A priority patent/EP3920168A4/en
Priority to US17/256,094 priority patent/US11798450B2/en
Publication of WO2020156284A1 publication Critical patent/WO2020156284A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Definitions

  • the embodiment of the present disclosure relates to a display driving device, a control method thereof, and a display device.
  • the display data of the frame to be displayed is processed by the processing chip, and then output to the display panel, and the display panel is driven to display the image.
  • the requirements for storage bandwidth and transmission interfaces are getting higher and higher.
  • At least one embodiment of the present disclosure provides a control method of a display driving device, the display driving device comprising: at least two processing chips, and memories connected to the at least two processing chips in a one-to-one correspondence signal; each of the memories It includes a plurality of frame addresses set in sequence; each frame to be displayed includes at least two image areas, and the at least two image areas correspond to the at least two processing chips one-to-one; in the at least two processing chips One of the processing chips is the master processing chip, and the remaining processing chips are slave processing chips;
  • control method includes:
  • the main processing chip receives the display data of the corresponding image area in the current frame to be displayed; each of the slave processing chips receives the display data of the corresponding image area in the current frame to be displayed;
  • the master processing chip generates a read and write synchronization signal when buffering the received display data, and each of the slave processing chips receives the read and write synchronization signal;
  • the main processing chip buffers the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and caches the data in the electrically connected memory
  • the display data of the last frame to be displayed is read and processed before being transmitted to the display panel;
  • each of the slave processing chips buffers the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory in synchronization with the master processing chip And the display data of the last frame to be displayed buffered in the connected memory is read and processed in synchronization with the main processing chip and then transmitted to the display panel.
  • the master processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the currently to be displayed frame; the slave processing chip is receiving the current to be displayed Receiving the frame start signal when displaying data corresponding to the image area in the frame picture;
  • control method Before the master processing chip generates a read-write synchronization signal when buffering the received display data, before each of the slave processing chips receives the read-write synchronization signal, the control method further includes:
  • the main processing chip generates a frame start synchronization signal according to the frame start signal, and the slave processing chip receives the frame start synchronization signal;
  • the master processing chip In response to the frame start synchronization signal and the frame start signal, the master processing chip generates a drive timing corresponding to the display data received by the master processing chip; each of the slave processing chips responds to the frame start The synchronization signal and the frame start signal are synchronized with the main processing chip to generate drive timing corresponding to the display data received from the processing chip.
  • the control method when the master processing chip buffers the received display data, the read and write synchronization signal is generated, and after each slave processing chip receives the read and write synchronization signal, the control method also includes:
  • the main processing chip buffers the received display data of the currently to-be-displayed frame picture and the corresponding drive timing into the frame address of the corresponding electrically connected memory, and compares The display data of the last frame to be displayed and the corresponding driving sequence buffered in the memory that are electrically connected are read and processed, and then transmitted to the display panel; and
  • each of the slave processing chips buffers the received display data of the currently to-be-displayed frame picture and the corresponding drive timing to the corresponding electrical connection in synchronization with the master processing chip
  • the display data of the last frame to be displayed and the corresponding drive sequence buffered in the memory that are electrically connected are read and processed in synchronization with the main processing chip and then transmitted to the The display panel.
  • the image area in each frame to be displayed extends along the column direction of the pixel units of the display panel, and is arranged along the row direction of the pixel units of the display panel.
  • the frame start signal is a field synchronization signal.
  • the sequence of buffering the frame addresses of the display data of the last frame to be displayed in the memory is before the sequence of buffering the frame addresses of the display data of the frame to be displayed currently.
  • the memory electrically connected to the master processing chip caches the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip caches the frame to be displayed currently
  • the frame address of the display data of the screen is the same.
  • the memory electrically connected to the master processing chip caches the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip caches the frame to be displayed currently The frame address of the display data of the screen is different.
  • the size of each image area is the same.
  • the multiple frame addresses of the memory corresponding to the processing chip and electrically connected are used to store the display data of each display frame in order and cyclically.
  • an embodiment of the present disclosure also provides a display driving device, including: at least two processing chips, and memories connected with the at least two processing chips in a one-to-one correspondence signal; each of the memories includes a plurality of memories arranged in order.
  • a frame address; each frame to be displayed includes at least two image areas, the at least two image areas correspond to the at least two processing chips one-to-one; one of the at least two processing chips is the main processing chip Processing chip, other processing chips are slave processing chips;
  • the main processing chip is configured to receive the display data of the corresponding image area in the current frame to be displayed and generate a read-write synchronization signal when buffering, and respond to the read-write synchronization signal to respond to the received frame to be displayed currently
  • the display data of is buffered into the frame address of the corresponding electrically connected memory, and the display data of the last frame to be displayed buffered in the electrically connected memory is read and processed and then transmitted to the display panel;
  • Each of the slave processing chips is configured to receive the display data of the corresponding image area in the currently to-be-displayed frame picture and the read-write synchronization signal, and in response to the read-write synchronization signal, send the received current to-be-displayed
  • the display data of the displayed frame picture is buffered in the frame address of the corresponding electrically connected memory in synchronization with the main processing chip, and the display data of the last frame picture to be displayed is buffered in the connected memory and all
  • the main processing chip performs reading and processing synchronously and transmits it to the display panel.
  • the main processing chip is further configured to receive the frame start signal when receiving the display data of the corresponding image area in the frame picture currently to be displayed, and generate a frame according to the frame start signal.
  • Start synchronization signal in response to the frame start synchronization signal and the frame start signal, generate a drive timing corresponding to the display data received by the main processing chip; respond to the read and write synchronization signal to receive the
  • the display data of the current frame to be displayed and the corresponding driving timing are cached in the frame address of the corresponding electrically connected memory, and the display data of the last frame to be displayed and the corresponding driving timing are cached in the electrically connected memory After reading and processing, it is transmitted to the display panel;
  • the slave processing chip is further configured to receive the frame start synchronization signal, and receive the frame start signal when receiving the display data of the corresponding image area in the frame to be displayed currently; in response to the frame start
  • the start synchronization signal and the frame start signal are synchronized with the main processing chip to generate a drive timing corresponding to the display data received from the processing chip; in response to the read and write synchronization signal, the received current to-be-displayed
  • the display data of the frame picture and the corresponding drive timing are cached in the frame address of the corresponding electrically connected memory in synchronization with the main processing chip, and the display data of the last frame picture to be displayed cached in the electrically connected memory
  • the corresponding driving timing is read and processed in synchronization with the main processing chip and then transmitted to the display panel.
  • each of the processing chips is further configured to receive display data of corresponding image areas in at least two to-be-displayed frame pictures; and cyclically use the multiple frame addresses of the memory in order, Buffer the received display data of the at least two frames to be displayed in an electrically connected memory, and for the plurality of frame addresses of the memory, sequentially and cyclically buffer the corresponding to be stored in the electrically connected memory.
  • the display data of the display frame is read, converted, and transmitted to the display panel.
  • the processing chip includes: a field programmable logic gate array chip.
  • the memory includes: a double-rate synchronous dynamic random access memory.
  • At least one embodiment of the present disclosure also provides a display device, including: a display panel and any of the above display driving devices,
  • the display panel is configured to receive the display data transmitted by the display driving device.
  • FIG. 1 is a schematic structural diagram of a display driving device in at least one embodiment of the present disclosure
  • Fig. 2 is a flowchart of a control method in at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a VS signal in at least one embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a specific structure of a display driving device in at least one embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a display device in at least one embodiment of the disclosure.
  • the general processing chip can be set as a field programmable logic gate array (Field Programmable Gate Array, FPGA) chip.
  • FPGA Field Programmable Gate Array
  • the display data of the frame to be displayed can be processed by the FPGA chip and then output to the display panel, so as to drive the display panel and realize the image display.
  • a common practice is to buffer the display data of several frames to be displayed into the memory electrically connected to the FPGA chip through the FPGA chip, and then the FPGA chip reads and processes the display data buffered in the memory and outputs it to the display panel.
  • the frame address of the memory is shared between each FPGA chip. That is, when an FPGA chip stores the display data of a certain frame to be displayed in the frame address of the corresponding memory, the frame addresses of the memory corresponding to the remaining FPGA chips also change synchronously, so that the display data of the frame to be displayed Synchronously store to the frame address of the corresponding memory.
  • the memory initialization fails or the transmission interface cannot be locked, etc., it may cause a sudden change in the frame address of the memory of a certain FPGA chip, such as a reset.
  • the frame address of the memory is shared between FPGA chips, if the frame address of the memory of a certain FPGA chip changes, the frame addresses of the memory of the other FPGA chips will also change. This may cause the display data stored and read by each FPGA chip from the memory to not belong to the same frame of picture, resulting in abnormal display of the picture.
  • Each memory 200_m includes a plurality of frame addresses set in order.
  • the memory 200_m may have K frame addresses set in order, that is, frame addresses 0, 1, 2...K-1; where K is an integer greater than 1. .
  • each frame to be displayed may include at least two image areas AA_m.
  • each image area AA_m corresponds to one processing chip 100_m.
  • the image area AA_1 corresponds to the processing chip 100_1
  • the image area AA_2 corresponds to the processing chip 100_2, and the rest is the same, which will not be repeated here.
  • One of the M processing chips is defined as the master processing chip, and the remaining processing chips are defined as slave processing chips.
  • the processing chip 100_1 is defined as the master processing chip
  • the processing chips 100_2 to 100_M are defined as the slave processing chips.
  • control method of the display driving device may include the following steps:
  • the main processing chip receives the display data of the corresponding image area in the frame picture currently to be displayed; each slave processing chip receives the display data of the corresponding image area in the frame picture currently to be displayed;
  • the main processing chip generates a read and write synchronization signal when buffering the received display data, and each slave processing chip receives the read and write synchronization signal;
  • the main processing chip buffers the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and buffers the last to-be-displayed frame in the electrically connected memory. After reading and processing the display data, it is transmitted to the display panel; each slave processing chip synchronously buffers the received display data of the current frame to be displayed in the frame address of the corresponding electrically connected memory in response to the read and write synchronization signal , And synchronously read and process the display data of the last frame to be displayed buffered in the connected memory and transmit it to the display panel.
  • the master processing chip and each slave processing chip in response to the read-write synchronization signal, synchronously buffer the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and synchronize The display data of the last frame to be displayed buffered in the connected memory is read and processed before being transmitted to the display panel.
  • one master processing chip and multiple slave processing chips are provided, which can facilitate the design of a high-resolution display panel. Moreover, when the main processing chip buffers the received display data of the corresponding image area in the current frame to be displayed, it can generate a read-write synchronization signal and send the generated read-write synchronization signal to each slave processing chip.
  • the main processing chip and each slave processing chip are controlled by the read-write synchronization signal to buffer the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and the data buffered in the electrically connected memory
  • the display data of a frame to be displayed is read and processed and then transmitted to the display panel to drive the display panel to display the picture.
  • the main processing chip and each slave processing chip control the storage and reading operations of the memory through the read and write synchronization signal, it is possible to avoid sharing the frame address of the memory between the processing chips, so that the frame of the memory corresponding to a certain processing chip When the address changes, it will not affect the frame address of the memory corresponding to the other processing chips, thus ensuring that the display data output by each processing chip belongs to the same frame of screen, thereby eliminating the problem of abnormal screen display caused by asynchronization of multiple processing chips .
  • different application environments have different requirements for the value of M, so the value of M can be designed and determined according to the actual application environment, which is not limited here.
  • each processing chip 100_m is connected to the same signal receiving interface 400 to receive the display data of the frame to be displayed through the signal receiving interface 400.
  • the frame address of the memory that is electrically connected to the main processing chip to buffer the display data of the frame to be displayed currently is the same as the frame address of the memory that is electrically connected to each slave processing chip to buffer the display data of the frame to be displayed. .
  • the frame address for reading the stored display data from the memory is also the same. For example, if a certain video has 300 consecutive pictures, the memory 200_m can store 3 frame addresses: frame address 0, frame address 1, and frame address 2 as an example.
  • the master processing chip 100_1 stores the display data corresponding to the image area AA_m in the first frame to be displayed in the frame address 0 of the corresponding memory 200_1, and the slave processing chips 100_2 ⁇ 100_M are also in the frame address 0 of the corresponding memory 200_2 ⁇ 100_M Store the display data corresponding to the image area AA_m in the first frame to be displayed.
  • the master processing chip 100_1 stores the display data corresponding to the image area AA_m in the second frame to be displayed in the frame address 1 of the corresponding memory 200_1, and the slave processing chips 100_2 ⁇ 100_M are also in the frame address 1 of the corresponding memory 200_2 ⁇ 100_M Store the display data of the corresponding image area AA_m in the second frame to be displayed.
  • the memory electrically connected to the main processing chip can also buffer the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip buffer the frame address of the display data of the frame to be displayed currently They are not the same, and are not limited here.
  • the order of the frame addresses of the display data of the last frame to be displayed in the memory can be buffered before the order of the frame addresses of the display data of the frame to be displayed currently. This can ensure that the read frame address is before the stored frame address, thereby avoiding display abnormalities.
  • the processing chip 100_m stores the display data corresponding to the image area AA_m in the first frame to be displayed in the frame address 0 of the corresponding memory 200_m, and the processing chip 100_m responds to the read and write synchronization signal in the frame of the corresponding memory 200_m
  • the display data of the corresponding image area AA_m in the second frame to be displayed is stored in address 1, and the display data of the first frame to be displayed stored in the frame address 0 of the corresponding memory 200_m is read and converted before transmission To the display panel.
  • the display data corresponding to the image area AA_m in the third frame to be displayed is stored in the frame address 2 of the corresponding memory 200_m, and the second stored in the frame address 1 of the corresponding memory 200_m
  • the display data of each frame to be displayed is read and converted and transmitted to the display panel. The rest is the same, so I won't repeat it here.
  • each processing chip 100_m may be configured to receive the display data corresponding to the image area AA_m in the at least two to-be-displayed frame pictures, and display the received at least two to-be-displayed frame pictures in response to the read-write synchronization signal
  • the data is circularly buffered to the frame address of the electrically connected memory 200_m in order, and the display data of the frame to be displayed buffered in the corresponding memory 200_m is sequentially read and converted to the display panel.
  • each processing chip 100_m may be configured to receive the display data corresponding to the image area AA_m in the at least two frames to be displayed, and in response to the read and write synchronization signal, the plurality of electrically connected memories 200_m are used in sequence and cyclically.
  • the frame address buffers the received display data of at least two frames to be displayed in the electrically connected memory 200_m (for example, according to the aforementioned frame address 1, frame address 2, frame address 0, frame address 1, frame address 2...
  • the display data of the frame to be displayed buffered in the corresponding memory 200_m is read and converted to the display panel (for example, according to The above-mentioned frame address 0, frame address 1, frame address 2, frame address 0, frame address 1... are read cyclically in order). This can avoid storing and reading the frame address in the same memory, thereby avoiding display abnormalities.
  • the number of frame addresses stored in the memory 200_m may be N.
  • the memory 200_m can store 3 frame addresses: frame address 0, frame address 1, and frame address 2.
  • a certain new video has 300 continuous pictures, and the processing chip 100_m cyclically receives the display data corresponding to the image area AA_m in the 3 frames to be displayed.
  • the processing chip 100_m buffers the received display data of the 3 frames to be displayed (that is, the display data of 3 consecutive frames to be displayed) to the frame address of the electrically connected memory 200_m in order, and stores the corresponding memory
  • the display data of the 3 to-be-displayed frames buffered in 200_m are read and converted in sequence and transferred to the display panel, which means: in response to the read and write synchronization signal, they are first stored in the frame address 0 of the corresponding memory 200_m
  • the display data of the first frame to be displayed of the new video, and the display data of the frame to be displayed of the previous video stored in the frame address 0 are read, converted, and transmitted to the display panel.
  • the display data of the second frame to be displayed is stored in the frame address 1 of the corresponding memory 200_m, and the display data of the first frame to be displayed stored in the frame address 0 is read After taking and converting, it is transmitted to the display panel so that the display panel displays the first frame to be displayed.
  • the display data of the third frame to be displayed is stored in the frame address 2 of the corresponding memory 200_m, and the display data of the second frame to be displayed stored in the frame address 1 is read After fetching and converting, it is transmitted to the display panel so that the display panel displays the second frame to be displayed.
  • the display data of the fourth frame to be displayed is stored in the frame address 0 of the corresponding memory 200_m, and the display data of the third frame to be displayed stored in the frame address 2 is read After fetching and converting, it is transmitted to the display panel so that the display panel displays the third frame to be displayed.
  • the display data of the fifth frame to be displayed is stored in the frame address 1 of the corresponding memory 200_m, and the display data of the fourth frame to be displayed stored in the frame address 0 is read After taking and converting, it is transmitted to the display panel, so that the display panel displays the fourth frame to be displayed.
  • the display data of the sixth frame to be displayed is stored in the frame address 2 of the corresponding memory 200_m, and the display data of the fifth frame to be displayed stored in the frame address 1 is read After taking and converting, it is transmitted to the display panel so that the display panel displays the fifth frame to be displayed. After that, cyclic storage is performed in the order of frame address 0, frame address 1, and frame address 2, and cyclic reading is performed in the order of frame address 2, frame address 0, and frame address 1 to drive the display panel to display, which will not be repeated here.
  • the main processing chip also receives the display data of the corresponding image area in the frame to be displayed currently The frame start signal
  • the slave processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed. That is, each processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed.
  • control method when the master processing chip generates a read and write synchronization signal when buffering the received display data, before each slave processing chip receives the read and write synchronization signal, the control method according to at least one embodiment of the present disclosure may further include:
  • the main processing chip generates a frame start synchronization signal according to the frame start signal, and receives the frame start synchronization signal from the processing chip;
  • the master processing chip In response to the frame start synchronization signal and the frame start signal, the master processing chip generates a drive timing corresponding to the display data received by the master processing chip; each slave processing chip generates corresponding slave processing in response to the frame start synchronization signal and the frame start signal. The drive timing of the display data received by the chip.
  • control method may include:
  • the main processing chip buffers the received display data of the currently to-be-displayed frame picture and the corresponding drive timing into the frame address of the corresponding electrically connected memory, and then caches the last to-be-displayed data in the electrically connected memory.
  • the display data of the display frame picture and the corresponding drive timing are read and processed and then transmitted to the display panel; each slave processing chip will receive the display data of the current frame to be displayed and the corresponding drive timing in response to the read and write synchronization signal Synchronously buffer into the frame address of the corresponding electrically connected memory, and synchronously read and process the display data of the last frame to be displayed and the corresponding driving sequence buffered in the electrically connected memory, and then transmit to the display panel.
  • the master processing chip and each slave processing chip in response to the read-write synchronization signal, synchronously buffer the received display data of the currently to-be-displayed frame and the corresponding drive timing to the frame of the corresponding electrically connected memory In the address, the display data of the last frame to be displayed and the corresponding drive sequence buffered in the electrically connected memory are read and processed synchronously, and then transmitted to the display panel.
  • the main processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed, and generates the frame start synchronization signal according to the frame start signal; then, responds to the frame start synchronization signal and the frame start signal.
  • the start signal is generated corresponding to the driving timing of the display data received by the main processing chip.
  • the main processing chip After that, the main processing chip generates a read and write synchronization signal when buffering the received display data, so as to respond to the read and write synchronization signal to buffer the received display data of the currently to-be-displayed frame and the corresponding drive timing to the corresponding electrical connection
  • the display data of the last frame to be displayed and the corresponding driving sequence buffered in the electrically connected memory are read and processed, and then transmitted to the display panel.
  • the slave processing chip also receives the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed; and, the slave processing chip also receives the frame start synchronization signal sent by the master processing chip, and responds to the frame start signal.
  • the synchronization signal and the frame start signal are synchronized with the main processing chip to generate drive timing corresponding to the display data received from the processing chip.
  • each slave processing chip receives the read and write synchronization signal, and in response to the read and write synchronization signal, buffers the received display data of the current frame to be displayed and the corresponding drive timing to the corresponding electrical connection in synchronization with the main processing chip.
  • the display data of the last frame to be displayed and the corresponding drive sequence buffered in the electrically connected memory are read and processed in synchronization with the main processing chip and then transmitted to the display panel.
  • the main processing chip can determine the start of a frame through the frame start signal, thereby generating a frame start synchronization signal to simultaneously control the driving of the main processing chip and the slave processing chip corresponding to the respective received display data through the frame start synchronization signal. Timing, so that the timing of driving the display data can be aligned, so that the screen is refreshed synchronously.
  • the field synchronization signal (VS) is set in the display panel.
  • the function of the VS signal is to select the effective field signal interval in the display panel. For example, when the falling edge of the VS signal, it can indicate a new display
  • the display data of the frame picture is transmitted sequentially according to the pixel units of the first row to the last row in the display panel.
  • the frame start signal may be set as a field synchronization signal. In this way, it can be ensured that the memory stores the display data of the corresponding image area in the frame address according to the order of the pixel units of the first row to the last row.
  • the display panel will also be provided with a line synchronization signal (HS), effective display data strobe signal (DE) and other signals.
  • HS line synchronization signal
  • DE effective display data strobe signal
  • each processing chip is receiving the current frame to be displayed.
  • At least one of the HS signal and the DE signal can also be received when the display data of the corresponding image area is displayed, which is not limited here.
  • the functions of the HS signal and the DE signal are basically the same as the existing functions, which should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be used as a limitation to the present disclosure.
  • each image area AA_m may be the same. In this way, the data stored, read, and processed by each processing chip can be more uniform, so that the power consumption of each processing chip is more uniform, so that the life of each processing chip is more uniform.
  • the main processing chip 100_1 is configured to receive the display data corresponding to the image area AA_1 in the current frame to be displayed and generate a read-write synchronization signal.
  • the main processing chip 100_1 responds to the read-write synchronization signal and will receive the current standby
  • the display data of the display frame is buffered into the frame address of the corresponding electrically connected memory 200_1, and the display data of the last frame to be displayed buffered in the electrically connected memory 200_1 is read and processed, and then transmitted to the display panel 300.
  • Each slave processing chip 100_2 ⁇ 100_M (M is an integer greater than 1) is configured to receive the display data AA_2 ⁇ AA_M of the corresponding image area in the current frame to be displayed and the read-write synchronization signal, and will receive the read-write synchronization signal in response to the read-write synchronization signal.
  • the received display data of the current frame to be displayed is synchronously buffered to the frame address of the corresponding electrically connected memory 200_2 ⁇ 200_M, and the display data of the last frame to be displayed buffered in the connected memory 200_2 ⁇ 200_M is synchronously read After the processing and processing, it is transmitted to the display panel 300.
  • the master processing chip 100_1 and each of the slave processing chips 100_2 to 100_M synchronously buffer the received display data of the current frame to be displayed to the corresponding electrically connected memory 200_1 to In the frame address of 200_M, the display data of the last frame to be displayed buffered in the connected memories 200_1 to 200_M is read and processed, and then transmitted to the display panel 300.
  • the main processing chip buffers the received display data of the corresponding image area in the current frame to be displayed, it can generate a read-write synchronization signal and send the generated read-write synchronization signal to each slave processing chip.
  • the main processing chip and each slave processing chip are controlled by the read-write synchronization signal to buffer the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and the data buffered in the electrically connected memory
  • the display data of a frame to be displayed is read and processed and then transmitted to the display panel to drive the display panel to display the picture.
  • the main processing chip and each slave processing chip control the storage and reading operations of the memory through the read and write synchronization signal, it is possible to avoid sharing the frame address of the memory between the processing chips, so that the frame of the memory corresponding to a certain processing chip When the address changes, it will not affect the frame address of the memory corresponding to the other processing chips, thus ensuring that the display data output by each processing chip belongs to the same frame of screen, thereby eliminating the problem of abnormal screen display caused by asynchronization of multiple processing chips .
  • the display driving device may be applicable to a 4K (3840*2160) display panel, an 8K (7680*4320) display panel, etc., which is not limited by the embodiment of the present disclosure.
  • each processing chip is configured to receive the display data of the corresponding image area in the at least two frames to be displayed; the multiple frame addresses of the electrically connected memory are cyclically used in order to receive The received display data of the at least two frames to be displayed are cached in the electrically connected memory, and the multiple frame addresses of the electrically connected memory are sequentially and cyclically displayed corresponding to the frame to be displayed cached in the electrically connected memory
  • the data is read and converted and transmitted to the display panel; among them, for each frame to be displayed, in response to the read and write synchronization signal, the received display data of the frame to be displayed is buffered into the frame address of the electrically connected memory , And synchronously read and process the display data of the last frame to be displayed buffered in the connected memory in response to the read-write synchronization signal, and then transmit it to the display panel.
  • the main processing chip is also configured to receive the frame start signal when receiving the display data of the corresponding image area in the frame picture currently to be displayed, and generate the frame start synchronization signal according to the frame start signal. Signal; In response to the frame start synchronization signal and the frame start signal, generate the drive timing corresponding to the display data received by the main processing chip; In response to the read and write synchronization signal, it will receive the display data and corresponding drive timing of the current frame to be displayed Buffer to the frame address of the corresponding electrically connected memory, and read and process the display data of the last frame to be displayed and the corresponding drive sequence buffered in the electrically connected memory, and then transmit to the display panel;
  • the slave processing chip is also configured to receive the frame start synchronization signal, and receive the frame start signal when receiving the display data of the corresponding image area in the current frame to be displayed; in response to the frame start synchronization signal and the frame start signal are generated synchronously Corresponding to the drive timing of the display data received from the processing chip; in response to the read-write synchronization signal, the received display data of the frame to be displayed and the corresponding drive timing are cached to the corresponding electrically connected memory in synchronization with the main processing chip In the frame address, the display data of the last frame to be displayed and the corresponding drive sequence buffered in the electrically connected memory are read and processed in synchronization with the main processing chip and then transmitted to the display panel.
  • the memory may include: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • the memory can also be other types of memory, which is not limited here.
  • the processing chip 100_m may include: a field programmable logic gate array chip (FPGA chip).
  • the FPGA chip in the processing chip 100_m may include: input interfaces RX1_m and RX2_m, a first input first output (FIFO) storage module 110_m, a timing generation module 120_m, a write memory controller 130_m, Read memory controller 140_m and output port 170_m.
  • the processing chip can also be other chips, which are not limited here.
  • the aforementioned FIFO storage module 110, timing generation module 120_m, write memory controller 130_m, and read memory controller 140_m may be implemented by software, hardware, firmware, or a combination thereof.
  • the input interfaces RX1_m and RX2_m are electrically connected to the signal receiving interface 400.
  • the input interfaces RX1_m and RX2_m may include: High Definition Multimedia Interface (HDMI).
  • HDMI 2.0 interface For example, HDMI 2.0 interface.
  • the input interfaces RX1_m and RX2_m can also be other interfaces that can realize the effects of the present disclosure, which are not limited here.
  • the FIFO storage module may be a FIFO memory, which may be a random access memory (RAM) inside the FPGA chip, which is used to store the display signals received by the input interfaces RX1_m and RX2_m.
  • the FIFO memory in the master processing chip is also used to generate a frame start synchronization signal according to the frame start signal, and provide it to the timing generation module 120_1 in each slave processing chip.
  • the structure of the FIFO memory can be basically the same as the existing structure and its variants, and will not be repeated here.
  • the timing generating module 120_m may include a timing generator for responding to the frame start synchronization signal and the corresponding frame start signal to synchronously generate the driving timing corresponding to the display data received by each processing chip 100_m.
  • the write memory controller 130_m may include a write direct memory access (WDMA) engine.
  • WDMA write direct memory access
  • the structure of the WDMA engine can be basically the same as the existing structure and its variants, and will not be repeated here.
  • the read memory controller 140_m may include a read direct memory access (RDMA) engine.
  • RDMA read direct memory access
  • the structure of the RDMA engine can be basically the same as the existing structure and its variants, which will not be repeated here.
  • the output port 170_m may include a V-By-One interface.
  • the structure of the V-By-One interface can be basically the same as the existing structure and its variants, and will not be repeated here.
  • the FPGA chip in the processing chip 100_m generally may also include: an AXI (Advanced eXtensible Interface) bus module 150_m and a data interaction module 160_m; wherein, the write memory controller 130_m can pass through the AXI bus module 150_m and The data interaction module 160_m performs data interaction with the memory 200_m. Further, the data interaction module 160_m can also be used to initialize the bottom storage in the memory 200_m. Among them, the structure of the AXI bus module 150_m and the data interaction module 160_m may be basically the same as the existing structure and its variants, and will not be repeated here.
  • AXI Advanced eXtensible Interface
  • the frame addresses stored in the memory 200_m are: frame address 0, frame address 1, and frame address 3 as an example for description.
  • the main processing chip 100_1 receives the display data and the frame start signal corresponding to the image area AA_1 in the first frame to be displayed through the input interfaces RX1_1 and RX2_1, and receives the display data corresponding to the image area AA_1 in the current frame to be displayed
  • the frame start signal is first stored in the FIFO storage module 110_1.
  • the processing chip 100_2 receives the display data and the frame start signal corresponding to the image area AA_2 in the first frame to be displayed through the input interfaces RX1_2 and RX2_2, and receives the display data corresponding to the image area AA_2 in the current frame to be displayed
  • the frame start signal is first stored in the FIFO storage module 110_2.
  • the FIFO storage module 110_1 generates a frame start synchronization signal FS_1 according to the frame start signal, and sends it to the timing generation module 120_1 of the master processing chip 100_1 and the timing generation module 120_2 of the slave processing chip 100_2.
  • the timing generating module 120_1 in the main processing chip 100_1 generates a driving timing corresponding to the display data received by the main processing chip 100_1 in response to the frame start synchronization signal FS_1 and the corresponding frame start signal.
  • the timing generation module 120_2 in the slave processing chip 100_2 synchronously generates the driving timing corresponding to the display data received from the processing chip 100_2 in response to the frame start synchronization signal FS_1 and the corresponding frame start signal.
  • the main processing chip 100_1 and the display data received from the processing chip 100_2 are processed synchronously, so that the display data in the two chips are aligned.
  • the write memory controller 130_1 in the main processing chip 100_1 receives the display data stored in the FIFO storage module 110_1 and the drive timing corresponding to the display data, generates a read and write synchronization signal DX_1, and sends the read and write synchronization signal DX_1 to the main processor
  • the write memory controller 130_1 in the main processing chip 100_1 buffers the received display data of the first frame to be displayed and the corresponding drive timing into the frame address 0 of the electrically connected memory 200_1 in response to the read and write synchronization signal DX_1, In response to the read and write synchronization signal DX_1, the display data of the last frame to be displayed and the corresponding driving sequence buffered in the memory 200_1 are read and processed, and then transmitted to the display panel 200 through the port 170_1. In addition, in response to the read and write synchronization signal DX_1, the slave memory write controller 130_2 in the processing chip 100_2 buffers the received display data of the first frame to be displayed and the corresponding drive timing to the frame address 0 of the electrically connected memory 200_2.
  • the display data of the last frame to be displayed and the corresponding driving sequence buffered in the memory 200_2 are read and processed, and then transmitted to the display panel 200 through the port 170_2. In this way, the display panel 200 can display the picture of the previous frame.
  • the main processing chip 100_1 receives the display data and the frame start signal corresponding to the image area AA_1 in the second frame to be displayed through the input interfaces RX1_1 and RX2_1, and combines the received frame image corresponding to the image area AA_1 in the current frame to be displayed
  • the display data and the frame start signal are first stored in the FIFO storage module 110_1.
  • the processing chip 100_2 receives the display data and the frame start signal corresponding to the image area AA_2 in the second frame to be displayed through the input interfaces RX1_2 and RX2_2, and receives the display data corresponding to the image area AA_2 in the current frame to be displayed
  • the frame start signal is first stored in the FIFO storage module 110_2.
  • the FIFO storage module 110_1 generates a frame start synchronization signal FS_2 according to the frame start signal, and sends it to the timing generation module 120_1 of the master processing chip 100_1 and the timing generation module 120_2 of the slave processing chip 100_2.
  • the timing generating module 120_1 in the main processing chip 100_1 generates a driving timing corresponding to the display data received by the main processing chip 100_1 in response to the frame start synchronization signal FS_2 and the corresponding frame start signal.
  • the timing generation module 120_2 in the slave processing chip 100_2 synchronously generates a driving timing corresponding to the display data received from the processing chip 100_2 in response to the frame start synchronization signal FS_2 and the corresponding frame start signal.
  • the main processing chip 100_1 and the display data received from the processing chip 100_2 are processed synchronously, so that the display data in the two chips are aligned.
  • the write memory controller 130_1 in the main processing chip 100_1 receives the display data stored in the FIFO storage module 110_1 and the drive timing corresponding to the display data, generates a read and write synchronization signal DX_2, and sends the read and write synchronization signal DX_2 to the main processor
  • the write memory controller 130_1 in the main processing chip 100_1 buffers the received display data of the second frame to be displayed and the corresponding drive timing into the frame address 1 of the electrically connected memory 200_1 in response to the read and write synchronization signal DX_2, In response to the read and write synchronization signal DX_2, the display data of the first frame to be displayed and the corresponding driving sequence buffered in the memory 200_1 are read and processed, and then transmitted to the display panel 200 through the port 170_1.
  • the slave write memory controller 130_2 in the processing chip 100_2 buffers the received display data of the second frame to be displayed and the corresponding drive timing to the frame address 1 of the electrically connected memory 200_2
  • the display data of the first frame to be displayed and the corresponding driving sequence buffered in the memory 200_2 are read and processed, and then transmitted to the display panel 200 through the port 170_2. In this way, the display panel 200 can display the first frame to be displayed.
  • the main processing chip 100_1 receives the display data and the frame start signal corresponding to the image area AA_1 in the third frame to be displayed through the input interfaces RX1_1 and RX2_1, and combines the received frame image corresponding to the image area AA_1 in the current frame to be displayed
  • the display data and the frame start signal are first stored in the FIFO storage module 110_1.
  • the processing chip 100_2 receives the display data and frame start signal corresponding to the image area AA_2 in the third frame to be displayed through the input interfaces RX1_2 and RX2_2, and receives the display data corresponding to the image area AA_2 in the current frame to be displayed
  • the frame start signal is first stored in the FIFO storage module 110_2.
  • the FIFO storage module 110_1 generates a frame start synchronization signal FS_3 according to the frame start signal, and sends it to the timing generation module 120_1 of the master processing chip 100_1 and the timing generation module 120_2 of the slave processing chip 100_2.
  • the timing generating module 120_1 in the main processing chip 100_1 generates a driving timing corresponding to the display data received by the main processing chip 100_1 in response to the frame start synchronization signal FS_3 and the corresponding frame start signal.
  • the timing generation module 120_2 in the slave processing chip 100_2 synchronously generates the driving timing corresponding to the display data received from the processing chip 100_2 in response to the frame start synchronization signal FS_3 and the corresponding frame start signal.
  • the main processing chip 100_1 and the display data received from the processing chip 100_2 are processed synchronously, so that the display data in the two chips are aligned.
  • the write memory controller 130_1 in the main processing chip 100_1 receives the display data stored in the FIFO storage module 110_1 and the drive timing corresponding to the display data, generates a read and write synchronization signal DX_3, and sends the read and write synchronization signal DX_3 to the main processor
  • the write memory controller 130_1 in the main processing chip 100_1 buffers the received display data of the third frame to be displayed and the corresponding drive timing into the frame address 2 of the electrically connected memory 200_1 in response to the read and write synchronization signal DX_3, In response to the read and write synchronization signal DX_2, the display data of the second frame to be displayed and the corresponding driving sequence buffered in the memory 200_1 are read and processed, and then transmitted to the display panel 200 through the port 170_1.
  • the slave write memory controller 130_2 in the processing chip 100_2 buffers the received display data of the third frame to be displayed and the corresponding drive timing to the frame address 2 of the electrically connected memory 200_2
  • the display data of the second frame to be displayed and the corresponding driving sequence buffered in the memory 200_2 are read and processed, and then transmitted to the display panel 200 through the port 170_1. In this way, the display panel 200 can display the second frame to be displayed. The same applies afterwards, and so on, so I won’t repeat them here.
  • the memory electrically connected to the main processing chip can buffer the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip can buffer the frame address of the display data of the frame to be displayed currently the same. In this way, the frame address for reading the stored display data from the memory is also the same.
  • the memory electrically connected to the main processing chip can also buffer the frame address of the display data of the frame to be displayed currently and the memory electrically connected to each slave processing chip can buffer the display data of the frame to be displayed currently.
  • the frame addresses are not the same, which is not limited in the embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a display device.
  • the display device 500 includes a display panel 510 and a display driving device 520 provided by the embodiment of the present disclosure.
  • the display panel 510 is configured to receive the display data transmitted by the display driving device 520.
  • the display panel 510 includes, but is not limited to, a 4K (3840*2160) display panel, an 8K (7680*4320) display panel, and so on.
  • 4K 3840*2160
  • 8K 7680*4320
  • the display panel may be, for example, a liquid crystal display panel or an electroluminescence display panel, which is not limited herein.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display panel, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a display panel, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the main processing chip buffers the received display data of the corresponding image area in the current frame to be displayed, it can generate a read-write synchronization signal and send the generated read-write synchronization signal to each slave processing chip.
  • the main processing chip and each slave processing chip are controlled by the read-write synchronization signal to buffer the received display data of the currently to-be-displayed frame into the frame address of the corresponding electrically connected memory, and compare the data buffered in the electrically connected memory.
  • the display data of a frame to be displayed is read and processed, and then transmitted to the display panel to drive the display panel to display the picture.
  • the main processing chip and each slave processing chip control the storage and reading operations of the memory through the read and write synchronization signal, it is possible to avoid sharing the frame address of the memory between the processing chips, so that the frame of the memory corresponding to a certain processing chip When the address changes, it will not affect the frame address of the memory corresponding to the other processing chips, so that the display data output by each processing chip can be guaranteed to belong to the same frame of screen, and the problem of abnormal screen display caused by asynchronization of multiple processing chips can be eliminated .

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Abstract

一种显示驱动装置、其控制方法及显示装置。该控制方法包括：主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一从处理芯片接收读写同步信号（S202）；主处理芯片响应于读写同步信号将接收到的当前待显示帧画面的显示数据缓存至对应存储器的帧地址中，并对缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板；以及每一从处理芯片响应于读写同步信号，将接收到的当前待显示帧画面的显示数据同步地缓存至对应存储器的帧地址中，并对缓存的上一个待显示帧画面的显示数据同步地进行读取与处理后传输至显示面板（S203）。通过读写同步信号控制主处理芯片和各从处理芯片控制存储器的存储和读取操作，可以避免各处理芯片之间共享存储器的帧地址，进而可以消除多个处理芯片不同步导致的画面显示异常的问题。

Description

显示驱动装置、其控制方法及显示装置
相关申请的交叉引用
本申请要求于2019年1月28日递交的第201910080264.5号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示驱动装置、其控制方法及显示装置。
背景技术
目前，通过处理芯片对待显示帧画面的显示数据进行处理后，再输出至显示面板中，对显示面板进行驱动以显示画面。随着高分辨率显示面板的出现，对存储带宽及传输接口的要求越来越高。
发明内容
本公开至少一个实施例提供了一种显示驱动装置的控制方法，所述显示驱动装置包括：至少两个处理芯片，与所述至少两个处理芯片一一对应信号连接的存储器；各所述存储器包括按次序设置的多个帧地址；每一待显示帧画面包括至少两个图像区域，所述至少两个图像区域与所述至少两个处理芯片一一对应；所述至少两个处理芯片中的一个处理芯片为主处理芯片，其余处理芯片为从处理芯片；
其中，所述控制方法包括：
所述主处理芯片接收当前待显示帧画面中对应图像区域的显示数据；每一所述从处理芯片接收所述当前待显示帧画面中对应图像区域的显示数据；
所述主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一所述从处理芯片接收所述读写同步信号；
所述主处理芯片响应于所述读写同步信号将接收到的所述当前待显 示帧画面的显示数据缓存至对应电连接的存储器的帧地址中，并对电连接的所述存储器中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板；以及
每一所述从处理芯片响应于所述读写同步信号，将接收到的所述当前待显示帧画面的显示数据与所述主处理芯片相同步地缓存至对应电连接的存储器的帧地址中，并对连接的所述存储器中缓存的所述上一个待显示帧画面的显示数据与所述主处理芯片相同步地进行读取与处理后传输至所述显示面板。
例如，在本公开实施例中，所述主处理芯片在接收所述当前待显示帧画面中对应图像区域的显示数据时还接收帧起始信号；所述从处理芯片在接收所述当前待显示帧画面中对应图像区域的显示数据时还接收所述帧起始信号；
在所述主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一所述从处理芯片接收所述读写同步信号之前，所述控制方法还包括：
所述主处理芯片根据所述帧起始信号生成帧起始同步信号，所述从处理芯片接收所述帧起始同步信号；以及
所述主处理芯片响应于所述帧起始同步信号和所述帧起始信号生成对应所述主处理芯片接收的显示数据的驱动时序；每一所述从处理芯片响应于所述帧起始同步信号和所述帧起始信号与所述主处理芯片同步地生成对应所述从处理芯片接收的显示数据的驱动时序。
例如，在本公开的实施例中，在所述主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一所述从处理芯片接收所述读写同步信号之后，所述控制方法还包括：
所述主处理芯片响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据和对应的所述驱动时序缓存至对应电连接的所述存储器的帧地址中，并对电连接的所述存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后传输至所述显示面板；以及
每一所述从处理芯片响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据和对应的所述驱动时序与所述主处理芯片相同步地缓存至对应电连接的存储器的帧地址中，并对电连接的所述存储器中缓存的上一 个待显示帧画面的显示数据和对应的驱动时序与所述主处理芯片相同步地进行读取与处理后传输至所述显示面板。
例如，在本公开实施例中，每一所述待显示帧画面中的图像区域沿所述显示面板的像素单元的列方向延伸，且沿所述显示面板的像素单元的行方向排列。
例如，在本公开实施例中，所述帧起始信号为场同步信号。
例如，在本公开实施例中，所述存储器中缓存所述上一个待显示帧画面的显示数据的帧地址的次序在缓存所述当前待显示帧画面的显示数据的帧地址的次序之前。
例如，在本公开实施例中，所述主处理芯片电连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址与各所述从处理芯片电连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址相同。
例如，在本公开实施例中，所述主处理芯片电连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址与各所述从处理芯片电连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址不相同。
例如，在本公开实施例中，各所述图像区域的尺寸相同。
例如，在本公开实施例中，与所述处理芯片对应电连接的所述存储器的所述多个帧地址被按次序循环地用于存储各显示帧画面的显示数据。
相应地，本公开实施例还提供了一种显示驱动装置，包括：至少两个处理芯片，与所述至少两个处理芯片一一对应信号连接的存储器；各所述存储器包括按次序设置的多个帧地址；每一待显示帧画面包括至少两个图像区域，所述至少两个图像区域与所述至少两个处理芯片一一对应；所述至少两个处理芯片中的一个处理芯片为主处理芯片，其余处理芯片为从处理芯片；
所述主处理芯片被配置为接收当前待显示帧画面中对应图像区域的显示数据并在缓存时生成读写同步信号，响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据缓存至对应电连接的存储器的帧地址中，并对电连接的所述存储器中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板；
每一所述从处理芯片被配置为接收所述当前待显示帧画面中对应图像区域的显示数据与所述读写同步信号，响应于所述读写同步信号，将接收到的 所述当前待显示帧画面的显示数据与所述主处理芯片相同步地缓存至对应电连接的存储器的帧地址中，并对连接的所述存储器中缓存的所述上一个待显示帧画面的显示数据与所述主处理芯片相同步地进行读取与处理后传输至所述显示面板。
例如，在本公开实施例中，所述主处理芯片还被配置为在接收所述当前待显示帧画面中对应图像区域的显示数据时接收帧起始信号，根据所述帧起始信号生成帧起始同步信号；响应于所述帧起始同步信号和所述帧起始信号生成对应所述主处理芯片接收的显示数据的驱动时序；响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据和对应的驱动时序缓存至对应电连接的存储器的帧地址中，并对电连接的所述存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后传输至所述显示面板；
所述从处理芯片还被配置为接收所述帧起始同步信号，并在接收所述当前待显示帧画面中对应图像区域的显示数据时接收所述帧起始信号；响应于所述帧起始同步信号和所述帧起始信号与所述主处理芯片同步地生成对应所述从处理芯片接收的显示数据的驱动时序；响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据和对应的驱动时序与所述主处理芯片同步地缓存至对应电连接的存储器的帧地址中，并对电连接的所述存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序与所述主处理芯片同步地进行读取与处理后传输至所述显示面板。
例如，在本公开实施例中，每一所述处理芯片还被配置为接收至少两个待显示帧画面中对应图像区域的显示数据；按次序循环使用所述存储器的所述多个帧地址，将接收到的所述至少两个待显示帧画面的显示数据缓存至电连接的存储器中，以及对于所述存储器的所述多个帧地址按次序循环地将对应电连接的存储器中缓存的待显示帧画面的显示数据进行读取并转换后传输至所述显示面板。
例如，在本公开实施例中，所述处理芯片包括：现场可编程逻辑门阵列芯片。
例如，在本公开实施例中，所述存储器包括：双倍速率同步动态随机存储器。
本公开至少一个实施例还提供了一种显示装置，包括：显示面板以及任一上述显示驱动装置，
其中，所述显示面板配置为接收所述显示驱动装置传输的所述显示数据。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一个实施例中显示驱动装置的结构示意图；
图2为本公开至少一个实施例中控制方法的流程图；
图3为本公开至少一个实施例中VS信号的示意图；
图4为本公开至少一个实施例中显示驱动装置的具体结构示意图；
图5为本公开至少一个实施例中显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
在实际设计中，一个处理芯片的存储带宽及传输接口的数量是有限的，这就导致仅设置一个处理芯片无法满足高分辨率显示面板的要求，因此需要设置两个或更多的处理芯片。这种设计能够适应高分辨率显示面板的设计，然而，这样设计并不能保证多个处理芯片各自输出的显示数据均属于同一帧画面，从而导致画面的显示异常。
一般处理芯片可以设置为现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)芯片。这样待显示帧画面的显示数据可以经过FPGA芯片进行相关的图像处理后再输出至显示面板中，以对显示面板进行驱动，实现画面显示。通常的做法是通过FPGA芯片将几个待显示帧画面的显示数据缓存至与该FPGA芯片电连接的存储器内，而后FPGA芯片对存储器内缓存 的显示数据进行读取并处理后输出给显示面板。
随着高分辨率显示面板的出现，对存储带宽和高速传输接口的要求越来越高。在实际设计中，一个FPGA芯片的存储带宽及传输接口的数量是有限的，这就导致仅设置一个FPGA芯片无法满足高分辨率显示面板的要求，从而需要设置两个或更多的FPGA芯片。由于设置多个FPGA芯片，通常会将一个待显示帧画面分割为多个区域，其中，一个区域对应一个FPGA芯片，一个FPGA芯片对应设置一个存储器。每一FPGA芯片均将多帧待显示帧画面对应区域的显示数据在对应的存储器中按次序进行存储，而后读取对应存储器中的显示数据并进行处理后输出给显示面板。这种设计能够适应高分辨率显示面板的要求。
为了保证多个FPGA芯片各自输出的显示数据可以均属于同一帧画面，一般通过使各FPGA芯片之间共享存储器的帧地址。即在一个FPGA芯片将某一帧待显示帧画面的显示数据存储至对应的存储器的帧地址中时，其余FPGA芯片对应的存储器的帧地址也同步变化，以将该待显示帧画面的显示数据同步存储至对应的存储器的帧地址中。然而，在存储器初始化失败或传输接口不能锁定等问题出现时，可能会导致某个FPGA芯片的存储器的帧地址突变，例如复位。由于各FPGA芯片之间共享存储器的帧地址，若某个FPGA芯片的存储器的帧地址突变，其余FPGA芯片的存储器的帧地址也会突变。这样可能导致各FPGA芯片从存储器中存储和读取的显示数据不能属于同一帧画面，从而导致画面的显示异常。
基于此，如图1所示，本公开实施例提供了一种显示驱动装置，可以包括：至少两个处理芯片100_m(m为大于或等于1且小于或等于M的整数，M为处理芯片的总数，且M为大于1的整数，图1以M＝2为例)，与各处理芯片100_m一一对应电连接的存储器200_m。各存储器200_m包括按次序设置的多个帧地址，例如，存储器200_m可以具有按次序设置的K个帧地址，即帧地址0、1、2……K-1；其中，K为大于1的整数。
并且，每一待显示帧画面可以包括至少两个图像区域AA_m，同一待显示帧画面中，每一图像区域AA_m对应一个处理芯片100_m。例如，图像区域AA_1对应处理芯片100_1，图像区域AA_2对应处理芯片100_2，其余同理，在此不作赘述。将这M个处理芯片中的一个处理芯片定义为主处理芯片， 其余处理芯片定义为从处理芯片，例如将处理芯片100_1定义为主处理芯片，处理芯片100_2～100_M定义为从处理芯片。
如图2所示，本公开实施例提供的显示驱动装置的控制方法，可以包括如下步骤：
S201、主处理芯片接收当前待显示帧画面中对应图像区域的显示数据；每一从处理芯片接收当前待显示帧画面中对应图像区域的显示数据；
S202、主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一从处理芯片接收读写同步信号；
S203、主处理芯片响应于读写同步信号将接收到的当前待显示帧画面的显示数据缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板；每一从处理芯片响应于读写同步信号，将接收到的当前待显示帧画面的显示数据同步缓存至对应电连接的存储器的帧地址中，并对连接的存储器中缓存的上一个待显示帧画面的显示数据进行同步读取与处理后传输至显示面板。在一个实施例中，响应于读写同步信号，主处理芯片和每一从处理芯片同步地将接收到的当前待显示帧画面的显示数据缓存至对应电连接的存储器的帧地址中，并同步地对连接的存储器中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板。
本公开实施例提供的显示驱动装置的控制方法，通过设置一个主处理芯片及多个从处理芯片，这样可以有利于实现高分辨率显示面板的设计。并且，在主处理芯片对接收的当前待显示帧画面中对应图像区域的显示数据进行缓存时，可以生成读写同步信号并将生成的读写同步信号发送给每一个从处理芯片。以通过读写同步信号控制主处理芯片和每一从处理芯片将接收到的当前待显示帧画面的显示数据缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板，以驱动显示面板进行画面显示。并且，由于通过读写同步信号控制主处理芯片和各从处理芯片控制存储器的存储和读取操作，可以避免各处理芯片之间共享存储器的帧地址，这样在某一个处理芯片对应的存储器的帧地址突变时，并不会影响其余处理芯片对应的存储器的帧地址，从而可以保证各个处理芯片输出的显示数据均属于同一帧画面，进而可以消除多个 处理芯片不同步导致的画面显示异常的问题。
在具体实施时，如图1所示，可以使M＝2，这样可以设置2个处理芯片100_1～100_2，2个存储器200_1～200_2。或者，也可以使M＝3，这样可以设置3个处理芯片100_1～100_3，3个存储器200_1～200_3。或者，也可以使M＝4，这样可以设置4个处理芯片100_1～100_4，4个存储器200_1～200_4。当然，不同应用环境对M的取值的需求不同，因此M的取值可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，如图1所示，各处理芯片100_m均连接同一个信号接收接口400，以通过信号接收接口400接收待显示帧画面的显示数据。在本公开实施例中，可以使主处理芯片电连接的存储器缓存当前待显示帧画面的显示数据的帧地址与各从处理芯片电连接的存储器缓存当前待显示帧画面的显示数据的帧地址相同。这样使得从存储器中读取存储的显示数据的帧地址也相同。例如，以某个视频具有300个连续的画面，存储器200_m可以存储3个帧地址：帧地址0、帧地址1以及帧地址2为例。主处理芯片100_1在对应的存储器200_1的帧地址0中存储第1个待显示帧画面中对应图像区域AA_m的显示数据，从处理芯片100_2～100_M也在对应的存储器200_2～100_M的帧地址0中存储第1个待显示帧画面中对应图像区域AA_m的显示数据。主处理芯片100_1在对应的存储器200_1的帧地址1中存储第2个待显示帧画面中对应图像区域AA_m的显示数据，从处理芯片100_2～100_M也在对应的存储器200_2～100_M的帧地址1中存储第2个待显示帧画面中对应图像区域AA_m的显示数据。其余同理，在此不作赘述。当然，在实际应用中，也可以使主处理芯片电连接的存储器缓存当前待显示帧画面的显示数据的帧地址与各从处理芯片电连接的存储器缓存当前待显示帧画面的显示数据的帧地址不相同，在此不作限定。
进一步地，在具体实施时，可以使存储器中缓存上一个待显示帧画面的显示数据的帧地址的次序在缓存当前待显示帧画面的显示数据的帧地址的次序之前。这样可以确保读取的帧地址位于存储的帧地址之前，从而避免显示异常的问题。例如，处理芯片100_m在对应的存储器200_m的帧地址0中存储有第1个待显示帧画面中对应图像区域AA_m的显示数据，则处理芯片100_m响应于读写同步信号在对应的存储器200_m的帧地址1中存储第2个 待显示帧画面中对应图像区域AA_m的显示数据，并将对应的存储器200_m的帧地址0中存储的第1个待显示帧画面的显示数据进行读取并转换后传输至显示面板。之后，响应于读写同步信号在对应的存储器200_m的帧地址2中存储第3个待显示帧画面中对应图像区域AA_m的显示数据，并将对应的存储器200_m的帧地址1中存储的第2个待显示帧画面的显示数据进行读取并转换后传输至显示面板。其余同理，在此不作赘述。
在具体实施时，每一处理芯片100_m可以被配置为接收至少两个待显示帧画面中对应图像区域AA_m的显示数据，响应于读写同步信号将接收到的至少两个待显示帧画面的显示数据按次序循环缓存至电连接的存储器200_m的帧地址中，以及将对应的存储器200_m中缓存的待显示帧画面的显示数据按次序循环进行读取并转换后传输至显示面板。在一个实施例中，每一处理芯片100_m可以被配置为接收至少两个待显示帧画面中对应图像区域AA_m的显示数据，响应于读写同步信号按次序循环使用电连接的存储器200_m的多个帧地址将接收到的至少两个待显示帧画面的显示数据缓存至电连接的存储器200_m中(例如，按照上述的帧地址1，帧地址2，帧地址0，帧地址1，帧地址2……的顺序循环地缓存)，以及对于存储器200_m的多个帧地址按次序循环地将对应的存储器200_m中缓存的待显示帧画面的显示数据进行读取并转换后传输至显示面板(例如，按照上述的帧地址0，帧地址1，帧地址2，帧地址0，帧地址1……的顺序循环地读取)。这样可以避免存储和读取同一存储器中的帧地址，从而避免显示异常的问题。
具体地，存储器200_m存储的帧地址可以为N个。例如，以N＝3为例，存储器200_m可以存储3个帧地址：帧地址0、帧地址1以及帧地址2。例如某个新视频具有300个连续的画面，则处理芯片100_m循环接收3个待显示帧画面中对应图像区域AA_m的显示数据。处理芯片100_m将接收到的3个待显示帧画面的显示数据(即连续的3个待显示帧画面的显示数据)按次序循环缓存至电连接的存储器200_m的帧地址中，并将对应的存储器200_m中缓存的3个待显示帧画面的显示数据按次序循环进行读取并转换后传输至显示面板，指的可以是：响应于读写同步信号先在对应的存储器200_m的帧地址0中存储该新视频的第1个待显示帧画面的显示数据，并将帧地址0中存储的上一个视频的待显示帧画面的显示数据进行读取并转换后传输至显示 面板。之后，响应于读写同步信号在对应的存储器200_m的帧地址1中存储第2个待显示帧画面的显示数据，并将帧地址0中存储的第1个待显示帧画面的显示数据进行读取并转换后传输至显示面板，以使显示面板显示第1个待显示帧画面。之后，响应于读写同步信号在对应的存储器200_m的帧地址2中存储第3个待显示帧画面的显示数据，并将帧地址1中存储的第2个待显示帧画面的显示数据进行读取并转换后传输至显示面板，以使显示面板显示第2个待显示帧画面。之后，响应于读写同步信号在对应的存储器200_m的帧地址0中存储第4个待显示帧画面的显示数据，并将帧地址2中存储的第3个待显示帧画面的显示数据进行读取并转换后传输至显示面板，以使显示面板显示第3个待显示帧画面。之后，响应于读写同步信号在对应的存储器200_m的帧地址1中存储第5个待显示帧画面的显示数据，并将帧地址0中存储的第4个待显示帧画面的显示数据进行读取并转换后传输至显示面板，以使显示面板显示第4个待显示帧画面。之后，响应于读写同步信号在对应的存储器200_m的帧地址2中存储第6个待显示帧画面的显示数据，并将帧地址1中存储的第5个待显示帧画面的显示数据进行读取并转换后传输至显示面板，以使显示面板显示第5个待显示帧画面。之后按照帧地址0、帧地址1、帧地址2的次序进行循环存储，以及按照帧地址2、帧地址0、帧地址1的次序进行循环读取，以驱动显示面板显示，在此不作赘述。
进一步地，为了使各处理芯片接收得到的显示数据的驱动时序同步，在具体实施时，在本公开实施例中，主处理芯片在接收当前待显示帧画面中对应图像区域的显示数据时还接收帧起始信号，并且从处理芯片在接收当前待显示帧画面中对应图像区域的显示数据时还接收帧起始信号。即各处理芯片在接收当前待显示帧画面中对应图像区域的显示数据时还接收帧起始信号。
例如，在主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一从处理芯片接收读写同步信号之前，根据本公开至少一个实施例的控制方法还可以包括：
主处理芯片根据帧起始信号生成帧起始同步信号，从处理芯片接收帧起始同步信号；
主处理芯片响应于帧起始同步信号和帧起始信号生成对应主处理芯片接收的显示数据的驱动时序；每一从处理芯片响应于帧起始同步信号和帧起始 信号同步生成对应从处理芯片接收的显示数据的驱动时序。
例如，在主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一从处理芯片接收读写同步信号之后，根据本公开至少一个实施例的控制方法可以包括：
主处理芯片响应于读写同步信号将接收到的当前待显示帧画面的显示数据和对应的驱动时序缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后传输至显示面板；每一从处理芯片响应于读写同步信号将接收到的当前待显示帧画面的显示数据和对应的驱动时序同步缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行同步读取与处理后传输至显示面板。在一个实施例中，响应于读写同步信号，主处理芯片和每一从处理芯片同步地将接收到的当前待显示帧画面的显示数据和对应的驱动时序缓存至对应电连接的存储器的帧地址中，并同步地对电连接的存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后传输至显示面板。
这样使得主处理芯片在接收当前待显示帧画面中对应图像区域的显示数据时还接收帧起始信号，根据帧起始信号生成帧起始同步信号；之后，响应于帧起始同步信号和帧起始信号生成对应主处理芯片接收的显示数据的驱动时序。之后，在主处理芯片在缓存接收到的显示数据时生成读写同步信号，以响应于读写同步信号将接收到的当前待显示帧画面的显示数据和对应的驱动时序缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后传输至显示面板。并且，从处理芯片在接收当前待显示帧画面中对应图像区域的显示数据时还接收帧起始信号；并且，从处理芯片还接收主处理芯片发送的帧起始同步信号，响应于帧起始同步信号和帧起始信号与主处理芯片同步地生成对应从处理芯片接收的显示数据的驱动时序。之后，每一从处理芯片接收读写同步信号，以响应于读写同步信号将接收到的当前待显示帧画面的显示数据和对应的驱动时序与主处理芯片相同步地缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序与主处理芯片相同步地进行读取与处理后传输至显示面 板。这样主处理芯片通过帧起始信号可以确定一帧画面的开始，从而生成帧起始同步信号，以通过帧起始同步信号同时控制主处理芯片和从处理芯片分别对应各自接收的显示数据的驱动时序，从而可以使驱动显示数据显示的时序可以打齐，以使画面同步刷新。
在具体实施时，在本公开实施例中，可以使每一待显示帧画面中的图像区域沿显示面板的像素单元的列方向延伸，且沿显示面板的像素单元的行方向排列。即可以使每一待显示帧画面包括沿显示面板的像素单元的行方向依次排列的M个图像区域。以M＝2为例，结合图1所示，每一待显示帧画面可以包括沿显示面板300的像素单元的行方向F1依次排列的2个图像区域AA_1和AA_2。
一般显示面板中会设置场同步信号(VS)，如图3所示，VS信号的作用是选择出显示面板中有效场信号区间，例如VS信号中的下降沿时，可以说明一个新的待显示帧画面的显示数据开始根据显示面板中的第一行至最后一行像素单元依次传输了。在具体实施时，在本公开实施例中，帧起始信号可以设置为场同步信号。这样可以保证存储器根据第一行至最后一行像素单元的顺序将对应图像区域的显示数据存储到帧地址中。
进一步地，显示面板中还会设置行同步信号(HS)，有效显示数据选通信号(DE)等信号，在具体实施时，在本公开实施例中，各处理芯片在接收当前待显示帧画面中对应图像区域的显示数据时还可以接收HS信号和DE信号中的至少一个，在此不作限定。当然，HS信号和DE信号的功能与现有的功能基本相同，为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
在具体实施时，在本公开实施例中，可以使各图像区域AA_m的尺寸相同。这样可以使各处理芯片存储、读取以及处理的数据较均匀，从而使各处理芯片的功耗较均匀，以使各处理芯片的寿命较均匀。
基于同一发明构思，本公开至少一个实施例还提供了一种显示驱动装置，该显示驱动装置适于实施上述的根据本公开至少一个实施例的控制方法。如图1所示，主处理芯片100_1被配置为接收当前待显示帧画面中对应图像区域AA_1的显示数据并生成读写同步信号，主处理芯片100_1响应于读写同步信号将接收到的当前待显示帧画面的显示数据缓存至对应电连接的存储器 200_1的帧地址中，并对电连接的存储器200_1中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板300。
每一从处理芯片100_2～100_M(M为大于1的整数)被配置为接收当前待显示帧画面中对应图像区域的显示数据AA_2～AA_M与读写同步信号，响应于读写同步信号，将接收到的当前待显示帧画面的显示数据同步缓存至对应电连接的存储器200_2～200_M的帧地址中，并对连接的存储器200_2～200_M中缓存的上一个待显示帧画面的显示数据进行同步读取与处理后传输至显示面板300。
在一个实施例中，响应于读写同步信号，主处理芯片100_1和每个从处理芯片100_2～100_M同步地将接收到的当前待显示帧画面的显示数据同步缓存至对应电连接的存储器200_1～200_M的帧地址中，并同步地对连接的存储器200_1～200_M中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板300。
本公开实施例提供的显示驱动装置，通过设置一个主处理芯片及至少一个从处理芯片，这样可以有利于实现高分辨率显示面板的设计。并且，在主处理芯片将接收的当前待显示帧画面中对应图像区域的显示数据进行缓存时，可以生成读写同步信号并将生成的读写同步信号发送给每一个从处理芯片。以通过读写同步信号控制主处理芯片和每一从处理芯片将接收到的当前待显示帧画面的显示数据缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板，以驱动显示面板进行画面显示。并且，由于通过读写同步信号控制主处理芯片和各从处理芯片控制存储器的存储和读取操作，可以避免各处理芯片之间共享存储器的帧地址，这样在某一个处理芯片对应的存储器的帧地址突变时，并不会影响其余处理芯片对应的存储器的帧地址，从而可以保证各个处理芯片输出的显示数据均属于同一帧画面，进而可以消除多个处理芯片不同步导致的画面显示异常的问题。
例如，根据本公开实施例的显示驱动装置可适用于4K(3840*2160)显示面板、8K(7680*4320)显示面板等，本公开的实施例对此不做限制。
在具体实施时，在本公开实施例中，每一处理芯片被配置为接收至少两个待显示帧画面中对应图像区域的显示数据；按次序循环使用电连接的存储 器的多个帧地址将接收到的至少两个待显示帧画面的显示数据缓存至电连接的存储器中，以及对于电连接的存储器的多个帧地址按次序循环地将对应电连接的存储器中缓存的待显示帧画面的显示数据进行读取并转换后传输至显示面板；其中，针对每一个待显示帧画面，响应于读写同步信号将接收到的当前待显示帧画面的显示数据缓存至电连接的存储器的帧地址中，以及响应于读写同步信号对连接的存储器中缓存的上一个待显示帧画面的显示数据进行同步读取与处理后传输至显示面板。
在具体实施时，在本公开实施例中，主处理芯片还被配置为在接收当前待显示帧画面中对应图像区域的显示数据时接收帧起始信号，根据帧起始信号生成帧起始同步信号；响应于帧起始同步信号和帧起始信号生成对应主处理芯片接收的显示数据的驱动时序；响应于读写同步信号将接收到的当前待显示帧画面的显示数据和对应的驱动时序缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后传输至显示面板；
从处理芯片还被配置为接收帧起始同步信号，并在接收当前待显示帧画面中对应图像区域的显示数据时接收帧起始信号；响应于帧起始同步信号和帧起始信号同步生成对应从处理芯片接收的显示数据的驱动时序；响应于读写同步信号将接收到的当前待显示帧画面的显示数据和对应的驱动时序与主处理芯片相同步地缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序与主处理芯片相同步地进行读取与处理后传输至显示面板。
在具体实施时，在本公开实施例中，可以使存储器包括：双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，DDR SDRAM)。当然，在实际应用中，存储器还可以为其他类型的存储器，在此不作限定。
在具体实施时，在本公开实施例中，可以使处理芯片100_m可以包括：现场可编程逻辑门阵列芯片(FPGA芯片)。其中，如图4所示，处理芯片100_m中的FPGA芯片可以包括：输入接口RX1_m和RX2_m，先进先出(First Input First Output，FIFO)存储模块110_m、时序产生模块120_m、写存储器控制器130_m、读存储器控制器140_m以及输出端口170_m。当然，在实际 应用中，处理芯片还可以为其他芯片，在此不作限定。例如，上述的FIFO存储模块110、时序产生模块120_m、写存储器控制器130_m、读存储器控制器140_m可通过软件、硬件、固件或其组合来实施。
在具体实施时，输入接口RX1_m和RX2_m与信号接收接口400电连接。其中，输入接口RX1_m和RX2_m可以包括：高清多媒体接口(High Definition Multimedia Interface，HDMI)。例如，HDMI 2.0接口。当然，输入接口RX1_m和RX2_m还可以为其他可实现本公开效果的接口，在此不作限定。
在具体实施时，FIFO存储模块可以为FIFO存储器，其可以是FPGA芯片内部的随机存取存储器(random access memory，RAM)，其用于存储输入接口RX1_m和RX2_m接收到的显示信号。并且，主处理芯片中的FIFO存储器还用于根据帧起始信号生成帧起始同步信号，并提供给各从处理芯片中的时序产生模块120_1。并且，FIFO存储器的结构可以与现有的结构及其变型基本相同，在此不作赘述。
在具体实施时，时序产生模块120_m可以包括时序产生器，用于响应于帧起始同步信号和对应的帧起始信号，以同步生成对应各处理芯片100_m接收的显示数据的驱动时序。
在具体实施时，写存储器控制器130_m可以包括写入式直接记忆体存取(WDMA)引擎。并且，WDMA引擎的结构可以与现有的结构及其变型基本相同，在此不作赘述。
在具体实施时，读存储器控制器140_m可以包括读取式直接记忆体存取(RDMA)引擎。并且，RDMA引擎的结构可以与现有的结构及其变型基本相同，在此不作赘述。
在具体实施时，输出端口170_m可以包括V-By-One接口。并且，V-By-One接口的结构可以与现有的结构及其变型基本相同，在此不作赘述。
进一步地，如图4所示，处理芯片100_m中的FPGA芯片一般还可以包括：AXI(Advanced eXtensible Interface)总线模块150_m和数据交互模块160_m；其中，写存储器控制器130_m可以通过AXI总线模块150_m和数据交互模块160_m与存储器200_m进行数据交互。进一步地，数据交互模块160_m还可以用于对存储器200_m中的底层存储进行初始化。其中，AXI总线模块150_m和数据交互模块160_m的结构可以与现有的结构及其变型 基本相同，在此不作赘述。
具体地，以图4所示的驱动装置的结构为例，对本公开实施例提供的驱动装置的工作过程进行说明。其中，以存储器200_m存储的帧地址为：帧地址0、帧地址1以及帧地址3为例进行说明。
主处理芯片100_1通过输入接口RX1_1和RX2_1接收第1个待显示帧画面中对应图像区域AA_1的显示数据与帧起始信号，并将接收到的当前待显示帧画面中对应图像区域AA_1的显示数据与帧起始信号先存储在FIFO存储模块110_1中。从处理芯片100_2通过输入接口RX1_2和RX2_2接收第1个待显示帧画面中对应图像区域AA_2的显示数据与帧起始信号，并将接收到的当前待显示帧画面中对应图像区域AA_2的显示数据与帧起始信号先存储在FIFO存储模块110_2中。
FIFO存储模块110_1根据帧起始信号生成帧起始同步信号FS_1，并发送给主处理芯片100_1的时序产生模块120_1与从处理芯片100_2的时序产生模块120_2。
主处理芯片100_1中的时序产生模块120_1响应于帧起始同步信号FS_1和对应的帧起始信号生成对应主处理芯片100_1接收的显示数据的驱动时序。并且，从处理芯片100_2中的时序产生模块120_2响应于帧起始同步信号FS_1和对应的帧起始信号同步生成对应从处理芯片100_2接收的显示数据的驱动时序。以对主处理芯片100_1和从处理芯片100_2接收到的显示数据进行同步处理，使这两个芯片中的显示数据打齐。
主处理芯片100_1中的写存储器控制器130_1接收FIFO存储模块110_1中存储的显示数据以及接收该显示数据对应的驱动时序，并生成读写同步信号DX_1，以及将读写同步信号DX_1发送给主处理芯片100_1中的读存储器控制器140_1、从处理芯片100_2中的写存储器控制器130_2和读存储器控制器140_2。
主处理芯片100_1中的写存储器控制器130_1响应于读写同步信号DX_1将接收到的第1个待显示帧画面的显示数据和对应的驱动时序缓存至电连接的存储器200_1的帧地址0中，并响应于该读写同步信号DX_1对存储器200_1中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后通过端口170_1传输至显示面板200。并且，从处理芯片100_2 中的写存储器控制器130_2响应于读写同步信号DX_1将接收到的第一个待显示帧画面的显示数据和对应的驱动时序缓存至电连接的存储器200_2的帧地址0中，并响应于该读写同步信号DX_1对存储器200_2中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后通过端口170_2传输至显示面板200。这样可以使显示面板200显示上一帧的画面。
之后，主处理芯片100_1通过输入接口RX1_1和RX2_1接收第2个待显示帧画面中对应图像区域AA_1的显示数据与帧起始信号，并将接收到的当前待显示帧画面中对应图像区域AA_1的显示数据与帧起始信号先存储在FIFO存储模块110_1中。从处理芯片100_2通过输入接口RX1_2和RX2_2接收第2个待显示帧画面中对应图像区域AA_2的显示数据与帧起始信号，并将接收到的当前待显示帧画面中对应图像区域AA_2的显示数据与帧起始信号先存储在FIFO存储模块110_2中。
FIFO存储模块110_1根据帧起始信号生成帧起始同步信号FS_2，并发送给主处理芯片100_1的时序产生模块120_1与从处理芯片100_2的时序产生模块120_2。
主处理芯片100_1中的时序产生模块120_1响应于帧起始同步信号FS_2和对应的帧起始信号生成对应主处理芯片100_1接收的显示数据的驱动时序。并且，从处理芯片100_2中的时序产生模块120_2响应于帧起始同步信号FS_2和对应的帧起始信号同步生成对应从处理芯片100_2接收的显示数据的驱动时序。以对主处理芯片100_1和从处理芯片100_2接收到的显示数据进行同步处理，使这两个芯片中的显示数据打齐。
主处理芯片100_1中的写存储器控制器130_1接收FIFO存储模块110_1中存储的显示数据以及接收该显示数据对应的驱动时序，并生成读写同步信号DX_2，以及将读写同步信号DX_2发送给主处理芯片100_1中的读存储器控制器140_1、从处理芯片100_2中的写存储器控制器130_2和读存储器控制器140_2。
主处理芯片100_1中的写存储器控制器130_1响应于读写同步信号DX_2将接收到的第2个待显示帧画面的显示数据和对应的驱动时序缓存至电连接的存储器200_1的帧地址1中，并响应于该读写同步信号DX_2对存储器200_1中缓存的第1个待显示帧画面的显示数据和对应的驱动时序进行 读取与处理后通过端口170_1传输至显示面板200。并且，从处理芯片100_2中的写存储器控制器130_2响应于读写同步信号DX_2将接收到的第2个待显示帧画面的显示数据和对应的驱动时序缓存至电连接的存储器200_2的帧地址1中，并响应于该读写同步信号DX_2对存储器200_2中缓存的第1个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后通过端口170_2传输至显示面板200。这样可以使显示面板200显示第1个待显示帧画面。
之后，主处理芯片100_1通过输入接口RX1_1和RX2_1接收第3个待显示帧画面中对应图像区域AA_1的显示数据与帧起始信号，并将接收到的当前待显示帧画面中对应图像区域AA_1的显示数据与帧起始信号先存储在FIFO存储模块110_1中。从处理芯片100_2通过输入接口RX1_2和RX2_2接收第3个待显示帧画面中对应图像区域AA_2的显示数据与帧起始信号，并将接收到的当前待显示帧画面中对应图像区域AA_2的显示数据与帧起始信号先存储在FIFO存储模块110_2中。
FIFO存储模块110_1根据帧起始信号生成帧起始同步信号FS_3，并发送给主处理芯片100_1的时序产生模块120_1与从处理芯片100_2的时序产生模块120_2。
主处理芯片100_1中的时序产生模块120_1响应于帧起始同步信号FS_3和对应的帧起始信号生成对应主处理芯片100_1接收的显示数据的驱动时序。并且，从处理芯片100_2中的时序产生模块120_2响应于帧起始同步信号FS_3和对应的帧起始信号同步生成对应从处理芯片100_2接收的显示数据的驱动时序。以对主处理芯片100_1和从处理芯片100_2接收到的显示数据进行同步处理，使这两个芯片中的显示数据打齐。
主处理芯片100_1中的写存储器控制器130_1接收FIFO存储模块110_1中存储的显示数据以及接收该显示数据对应的驱动时序，并生成读写同步信号DX_3，以及将读写同步信号DX_3发送给主处理芯片100_1中的读存储器控制器140_1、从处理芯片100_2中的写存储器控制器130_2和读存储器控制器140_2。
主处理芯片100_1中的写存储器控制器130_1响应于读写同步信号DX_3将接收到的第3个待显示帧画面的显示数据和对应的驱动时序缓存至 电连接的存储器200_1的帧地址2中，并响应于该读写同步信号DX_2对存储器200_1中缓存的第2个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后通过端口170_1传输至显示面板200。并且，从处理芯片100_2中的写存储器控制器130_2响应于读写同步信号DX_3将接收到的第3个待显示帧画面的显示数据和对应的驱动时序缓存至电连接的存储器200_2的帧地址2中，并响应于该读写同步信号DX_3对存储器200_2中缓存的第2个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后通过端口170_1传输至显示面板200。这样可以使显示面板200显示第2个待显示帧画面。之后同理，以此类推，在此不作赘述。
在本公开一些实施例中，可以使主处理芯片电连接的存储器缓存当前待显示帧画面的显示数据的帧地址与各从处理芯片电连接的存储器缓存当前待显示帧画面的显示数据的帧地址相同。这样使得从存储器中读取存储的显示数据的帧地址也相同。当然，在另一些实施例中，也可以使主处理芯片电连接的存储器缓存当前待显示帧画面的显示数据的帧地址与各从处理芯片电连接的存储器缓存当前待显示帧画面的显示数据的帧地址不相同，本公开的实施例对此不作限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，如图5所示，显示装置500包括显示面板510和本公开实施例提供的显示驱动装置520。显示面板510配置为接收该显示驱动装置520传输的显示数据。显示面板510例如包括但不限于4K(3840*2160)显示面板、8K(7680*4320)显示面板等。该显示装置的实施可以参见上述显示驱动装置的实施例，重复之处不再赘述。
在具体实施时，在本公开实施例中，显示面板例如可以为液晶显示面板或电致发光显示面板，在此不作限定。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示面板、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的显示驱动装置、其控制方法及显示装置，通过设置一个主处理芯片及至少一个从处理芯片，这样可以有利于实现高分辨率显示 面板的设计。并且，在主处理芯片对接收的当前待显示帧画面中对应图像区域的显示数据进行缓存时，可以生成读写同步信号并将生成的读写同步信号发送给每一个从处理芯片。以通过读写同步信号控制主处理芯片和每一从处理芯片将接收到的当前待显示帧画面的显示数据缓存至对应电连接的存储器的帧地址中，并对电连接的存储器中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板，以驱动显示面板进行画面显示。并且，由于通过读写同步信号控制主处理芯片和各从处理芯片控制存储器的存储和读取操作，可以避免各处理芯片之间共享存储器的帧地址，这样在某一个处理芯片对应的存储器的帧地址突变时，并不会影响其余处理芯片对应的存储器的帧地址，从而可以保证各个处理芯片输出的显示数据均属于同一帧画面，进而可以消除多个处理芯片不同步导致的画面显示异常的问题。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种显示驱动装置的控制方法，所述显示驱动装置包括：至少两个处理芯片，与所述至少两个处理芯片一一对应信号连接的存储器；各所述存储器包括按次序设置的多个帧地址；每一待显示帧画面包括至少两个图像区域，所述至少两个图像区域与所述至少两个处理芯片一一对应；所述至少两个处理芯片中的一个处理芯片为主处理芯片，其余处理芯片为从处理芯片；
    其中，所述控制方法包括：
    所述主处理芯片接收当前待显示帧画面中对应图像区域的显示数据；每一所述从处理芯片接收所述当前待显示帧画面中对应图像区域的显示数据；
    所述主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一所述从处理芯片接收所述读写同步信号；
    所述主处理芯片响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据缓存至对应信号连接的存储器的帧地址中，并对信号连接的所述存储器中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板；以及
    每一所述从处理芯片响应于所述读写同步信号，将接收到的所述当前待显示帧画面的显示数据与所述主处理芯片相同步地缓存至对应信号连接的存储器的帧地址中，并对连接的所述存储器中缓存的所述上一个待显示帧画面的显示数据与所述主处理芯片相同步地进行读取与处理后传输至所述显示面板。
  2. 如权利要求1所述的控制方法，还包括：所述主处理芯片在接收所述当前待显示帧画面中对应图像区域的显示数据时还接收帧起始信号；所述从处理芯片在接收所述当前待显示帧画面中对应图像区域的显示数据时还接收所述帧起始信号；
    在所述主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一所述从处理芯片接收所述读写同步信号之前，所述控制方法还包括：
    所述主处理芯片根据所述帧起始信号生成帧起始同步信号，所述从处理芯片接收所述帧起始同步信号；以及
    所述主处理芯片响应于所述帧起始同步信号和所述帧起始信号生成对应所述主处理芯片接收的显示数据的驱动时序；每一所述从处理芯片响应于所述帧起始同步信号和所述帧起始信号与所述主处理芯片同步地生成对应所述从处理芯片接收的显示数据的驱动时序。
  3. 如权利要求2所述的控制方法，其中，
    在所述主处理芯片在缓存接收到的显示数据时生成读写同步信号，每一所述从处理芯片接收所述读写同步信号之后，所述控制方法还包括：
    所述主处理芯片响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据和对应的所述驱动时序缓存至对应信号连接的所述存储器的帧地址中，并对信号连接的所述存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后传输至所述显示面板；以及
    每一所述从处理芯片响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据和对应的所述驱动时序与所述主处理芯片相同步地缓存至对应信号连接的存储器的帧地址中，并对信号连接的所述存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序与所述主处理芯片相同步地进行读取与处理后传输至所述显示面板。
  4. 如权利要求2或3所述的控制方法，其中，每一所述待显示帧画面中的图像区域沿所述显示面板的像素单元的列方向延伸，且沿所述显示面板的像素单元的行方向排列。
  5. 如权利要求2-4任一项所述的控制方法，其中，所述帧起始信号为场同步信号。
  6. 如权利要求1-5任一项所述的控制方法，其中，所述存储器中缓存所述上一个待显示帧画面的显示数据的帧地址的次序在缓存所述当前待显示帧画面的显示数据的帧地址的次序之前。
  7. 如权利要求1-6任一项所述的控制方法，其中，所述主处理芯片信号连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址与各所述从处理芯片信号连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址相同。
  8. 如权利要求1-6任一项所述的控制方法，其中，所述主处理芯片信号连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址与各所述从处 理芯片信号连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址不相同。
  9. 如权利要求1-8任一项所述的控制方法，其中，各所述图像区域的尺寸相同。
  10. 如权利要求1-9任一项所述的控制方法，其中，与所述处理芯片对应信号连接的所述存储器的所述多个帧地址被按次序循环地用于存储各显示帧画面的显示数据。
  11. 一种显示驱动装置，包括：
    至少两个处理芯片，
    与所述至少两个处理芯片一一对应信号连接的存储器，
    其中，各所述存储器包括按次序设置的多个帧地址；每一待显示帧画面包括至少两个图像区域，所述至少两个图像区域与所述至少两个处理芯片一一对应；所述至少两个处理芯片中的一个处理芯片为主处理芯片，其余处理芯片为从处理芯片；
    所述主处理芯片被配置为接收当前待显示帧画面中对应图像区域的显示数据并在缓存时生成读写同步信号，响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据缓存至对应信号连接的存储器的帧地址中，并对信号连接的所述存储器中缓存的上一个待显示帧画面的显示数据进行读取与处理后传输至显示面板；
    每一所述从处理芯片被配置为接收所述当前待显示帧画面中对应图像区域的显示数据与所述读写同步信号，响应于所述读写同步信号，将接收到的所述当前待显示帧画面的显示数据与所述主处理芯片相同步地缓存至对应信号连接的存储器的帧地址中，并对连接的所述存储器中缓存的所述上一个待显示帧画面的显示数据与所述主处理芯片相同步地进行读取与处理后传输至所述显示面板。
  12. 如权利要求11所述的显示驱动装置，其中，所述主处理芯片还被配置为在接收所述当前待显示帧画面中对应图像区域的显示数据时接收帧起始信号，根据所述帧起始信号生成帧起始同步信号；响应于所述帧起始同步信号和所述帧起始信号生成对应所述主处理芯片接收的显示数据的驱动时序；响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据和对 应的驱动时序缓存至对应信号连接的存储器的帧地址中，并对信号连接的所述存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序进行读取与处理后传输至所述显示面板；
    所述从处理芯片还被配置为接收所述帧起始同步信号，并在接收所述当前待显示帧画面中对应图像区域的显示数据时接收所述帧起始信号；响应于所述帧起始同步信号和所述帧起始信号与所述主处理芯片同步地生成对应所述从处理芯片接收的显示数据的驱动时序；响应于所述读写同步信号将接收到的所述当前待显示帧画面的显示数据和对应的驱动时序与所述主处理芯片同步地缓存至对应信号连接的存储器的帧地址中，并对信号连接的所述存储器中缓存的上一个待显示帧画面的显示数据和对应的驱动时序与所述主处理芯片同步地进行读取与处理后传输至所述显示面板。
  13. 如权利要求12所述的显示驱动装置，其中，每一所述处理芯片还被配置为接收至少两个待显示帧画面中对应图像区域的显示数据；按次序循环使用所述存储器的所述多个帧地址，将接收到的所述至少两个待显示帧画面的显示数据缓存至信号连接的存储器中，以及对于所述存储器的所述多个帧地址按次序循环地将对应信号连接的存储器中缓存的待显示帧画面的显示数据进行读取并转换后传输至所述显示面板。
  14. 如权利要求12或13所述的显示驱动装置，其中，所述帧起始信号为场同步信号。
  15. 如权利要求11-14任一项所述的显示驱动装置，其中，所述存储器中缓存所述上一个待显示帧画面的显示数据的帧地址的次序在缓存所述当前待显示帧画面的显示数据的帧地址的次序之前。
  16. 如权利要求11-15任一项所述的显示驱动装置，其中，所述主处理芯片信号连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址与各所述从处理芯片信号连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址相同。
  17. 如权利要求11-15任一项所述的显示驱动装置，其中，所述主处理芯片信号连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址与各所述从处理芯片信号连接的存储器缓存所述当前待显示帧画面的显示数据的帧地址不相同。
  18. 如权利要求11-17任一项所述的显示驱动装置，其中，所述处理芯片包括：现场可编程逻辑门阵列芯片。
  19. 如权利要求11-18任一项所述的显示驱动装置，其中，
    所述存储器包括：双倍速率同步动态随机存储器。
  20. 一种显示装置，包括：显示面板以及如权利要求11-19任一项所述的显示驱动装置，
    其中，所述显示面板配置为接收所述显示驱动装置传输的所述显示数据。
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