WO2014082231A1 - 一种液晶面板驱动电路、液晶显示装置及一种驱动方法 - Google Patents

一种液晶面板驱动电路、液晶显示装置及一种驱动方法 Download PDF

Info

Publication number
WO2014082231A1
WO2014082231A1 PCT/CN2012/085478 CN2012085478W WO2014082231A1 WO 2014082231 A1 WO2014082231 A1 WO 2014082231A1 CN 2012085478 W CN2012085478 W CN 2012085478W WO 2014082231 A1 WO2014082231 A1 WO 2014082231A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
timing control
liquid crystal
module
storage
Prior art date
Application number
PCT/CN2012/085478
Other languages
English (en)
French (fr)
Inventor
谭小平
秦杰辉
张勇
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/807,734 priority Critical patent/US20150279312A1/en
Publication of WO2014082231A1 publication Critical patent/WO2014082231A1/zh

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006Details of the interface to the display terminal
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096Details of the interface to the display terminal specific for a flat panel
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005Adapting incoming signals to the display format of the display terminal
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00Aspects of display data processing
    • G09G2340/04Changes in size, position or resolution of an image
    • G09G2340/0407Resolution change, inclusive of the use of different resolutions for different screen areas
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00Solving problems of bandwidth in display systems
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00Parallel handling of streams of display data
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/18Use of a frame buffer in a display terminal, inclusive of the display panel
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00Aspects of data communication
    • G09G2370/12Use of DVI or HDMI protocol in interfaces along the display data pipeline
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00Aspects of data communication
    • G09G2370/20Details of the management of multiple sources of image data

Definitions

  • Liquid crystal panel driving circuit liquid crystal display device and driving method
  • the present invention relates to the field of liquid crystal display, and more particularly to a liquid crystal panel driving circuit, a liquid crystal display device, and a driving method.
  • the interface of conventional LCD TVs in the market includes HDMI, DVL Display Port, etc., but for ultra-high resolution LCD panels with resolutions of 3840X2160 and above, single-channel input can support such high resolution due to bandwidth limitation.
  • the interface has only a 30Hz HDMI input signal, but the human eye can easily observe flicker. Therefore, the common architecture is dual signal input. As shown in Fig. 1, taking the DVI input as an example, the image signal is divided into 1/2, and then input from the DVI interface to the programmable logic array (FPGA) through two input signals respectively.
  • FPGA programmable logic array
  • the FPGA then combines the signals of the two interfaces, combines the two 1/2 image signals, and then performs arithmetic processing such as error processing and inter-row shift compensation, and then splits into 1/2 display signals and outputs them to each TCON.
  • arithmetic processing such as error processing and inter-row shift compensation
  • the technical problem to be solved by the present invention is to provide a liquid crystal panel driving circuit, a liquid crystal display device and a driving method for improving the picture synchronization performance of a liquid crystal panel.
  • a driving circuit for a liquid crystal panel includes at least two signal input interfaces and a timing control module, and the driving circuit further includes a storage module and a data processing module;
  • the data processing module reads the screen data from the storage module and sends the image data to the timing control module, and the timing control module drives the liquid crystal panel.
  • the timing control module has at least two, and the data processing module reads from the storage module. After the screen data is processed, it is sent to all timing control modules at the same time.
  • the screen data of different interfaces is stored through different storage spaces, and the data of each interface does not affect each other, so that it is determined whether the picture data of the corresponding interface is written by detecting whether the data of each storage space is empty, and the method is reliable. It is conducive to the design of the tube and reduces the design cost.
  • the data processing module includes a conversion unit that converts the picture data into a data format readable by the timing control module. Since the input video signal format is various, the conversion unit can be added for data processing without changing the timing control module, which can alleviate the burden of the timing control module and enhance the versatility of the timing control module.
  • the storage module includes at least two storage spaces, where each storage space stores screen data of a signal input interface, and when all storage spaces have screen data stored therein, the data processing module simultaneously reads The picture data of each storage space is then sent to the timing control module.
  • the screen data of different interfaces is stored through different storage spaces, and the data of each interface does not affect each other, so that it is determined whether the picture data of the corresponding interface is written by detecting whether the data of each storage space is empty, and the method is reliable. It is conducive to the design of the tube and reduces the design cost.
  • the timing control module has at least two, the data processing module includes a conversion unit that converts the screen data into a data format readable by the timing control module, and the storage module includes at least two storage spaces, each of the The storage space stores the screen data of a signal input interface.
  • the data processing module simultaneously reads the screen data of each storage space, and converts the screen data into the timing through the conversion unit. After controlling the data format readable by the module, it is sent to all timing control modules at the same time. This is a specific liquid crystal panel driving circuit.
  • the storage module can receive the screen data from the interface module and send the screen data to the data processing module.
  • the operation efficiency is high, and the data processing capability of the driving circuit can be improved.
  • the signal input interface is any one of a digital video interface (DVI: Digital Visual Interface), a high definition multimedia interface (HDMI: High Definition Multimedia Interface), or a high definition digital display interface (DisplayPort);
  • the processing module is a Field-Programmable Gate Array (FPGA).
  • FPGA Field-Programmable Gate Array
  • a liquid crystal display device comprising the driving circuit of any one of the liquid crystal panels described above.
  • a driving method of a liquid crystal panel with multiple signal inputs comprising the steps of:
  • step B When all the input signal interfaces have the same picture data storage in the storage module, go to step C; otherwise, return to step A;
  • the timing control module has at least two, and the step A includes: establishing two storage spaces with the same number of input interfaces in the storage module, and respectively writing the screen data of the two input interfaces into the corresponding storage.
  • the step B detects the content of each storage space. If the contents of the two storage spaces are not empty, go to step C, otherwise return to step A.
  • the step C includes: using a data processing module to read picture data from the storage module, and converting the picture data into a data format readable by the timing control module, and then transmitting to all the timing control modules simultaneously.
  • the screen data of different interfaces is stored through different storage spaces, and the data of each interface does not affect each other, so that it is determined whether the picture data of the corresponding interface is written by detecting whether the data of each storage space is empty, and the method is reliable. It is conducive to the design of the tube and reduces the design cost.
  • the step C includes: using a data processing module to read picture data line by line from the storage module, and converting the picture data into a data format readable by the timing control module, and then sending it to all at the same time.
  • Timing control module This is a progressive transmission mode.
  • the storage module can receive the screen data from the interface module and send the screen data to the data processing module. The operation efficiency is high, and the data processing capability of the driving circuit can be improved.
  • the inventor's research found that the phenomenon that the left and right pictures are not synchronized is mainly due to the fact that the display card or other display device may receive individual data delay due to channel speed.
  • the picture data has a certain time difference, and the time difference is not fixed.
  • the data or more) the FPGA will treat the data of different frames as the same frame of data at the same time, causing the left and right pictures to be not accurately synchronized, thus affecting the normal display of the picture.
  • the picture data of each input signal interface is first stored first, and each picture interface has the same display picture data stored, and then sent to all the timing control modules at the same time, so that each The timing control module can receive the screen data of the same display screen at the same time, and synchronously drive the existing data lines for display, so that the corresponding display area of each timing control module displays the corresponding picture at the same time, forming a complete
  • the picture solves the problem that the prior art picture is out of sync and improves the display quality.
  • 1 is a schematic view showing the driving of a conventional liquid crystal panel
  • Figure 2 is a schematic view of the principle of the present invention
  • FIG. 3 is a schematic diagram of a principle of using two-way signal input according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing the data structure of two storage spaces when the DDR memory module first starts storing data according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of data structures of two storage spaces after the DDR memory module has just stored data according to an embodiment of the present invention
  • Figure 6 is a schematic illustration of a method in accordance with an embodiment of the present invention.
  • the invention discloses a liquid crystal display device, which comprises a driving of a liquid crystal panel Circuit.
  • the driving circuit of the liquid crystal panel includes at least two signal input interfaces and a timing control module, and the driving circuit further includes a storage module and a data processing module;
  • the data processing module reads the screen data from the storage module and sends it to the timing control module, and the timing control module drives the liquid crystal panel.
  • the inventor has found that since the display card or other display device has a certain time difference in accepting the multi-input picture data, the time difference is not fixed (one line of data or more), causing the left and right sides of the picture to be out of sync, thereby affecting the normal display of the picture.
  • the invention adopts the storage module, first stores the screen data of each input signal interface first, and after each interface has the same display screen image data, and then sends it to all the timing control modules at the same time, so that each The timing control module can receive the screen data of the same display screen at the same time, and synchronously drive the existing data lines for display, so that the corresponding display area of each timing control module displays the corresponding picture at the same time, forming a complete image.
  • the screen solves the problem that the prior art pictures are out of sync and improves the display quality.
  • the data processing module can also include a conversion unit that converts the picture data into a data format readable by the timing control module. Since the input video signal format is various, the conversion unit can be added for data processing without changing the timing control module, which can reduce the burden of the timing control module and enhance the versatility of the timing control module.
  • FIG. 3 shows a driving circuit of a 3840*2160 ultra high definition resolution liquid crystal panel, which includes two DVI signal input interfaces, and each DVI receives a data stream of 1920*2160, that is, 1/2 screen data of the same display screen.
  • the corresponding picture data is input into the DDR memory module.
  • the DDR memory module includes two storage spaces (address 1 and address 2), and each storage space stores picture data of a DVI signal input interface.
  • the data processing module can use a programmable logic array (FPGA: Field - Programmable Gate Array).
  • FPGA Field - Programmable Gate Array
  • the programmable logic array Reads the picture data of each memory space at the same time and converts it into a data format readable by the timing control module, and then sends it to all timing control modules.
  • the screen data of different interfaces is stored through different storage spaces, and the data of each interface does not affect each other, so that it is determined whether the picture data of the corresponding interface is written by detecting whether the data of each storage space is empty, and the method is reliable. It is conducive to the design of the tube and reduces the design cost.
  • the DDR memory module can receive picture data from the interface module and send the picture data to the data processing module, which has high operation efficiency and can improve the data processing capability of the driving circuit.
  • This embodiment is a dual-interface technical solution, which can use mainstream dual-channel storage modules (such as DDR) to store picture data.
  • DDR digital video interface
  • the present invention is also applicable only to a digital video interface (DVI: Digital Visual Interface), and can also be applied to other high definition data interfaces such as a high definition multimedia interface (HDMI) and a high definition digital display interface (DisplayPort).
  • HDMI High Definition multimedia interface
  • DisplayPort high definition digital display interface
  • the data processing module can also use other circuits that can perform data format conversion and synchronous output.
  • the data processing module can also have no function of the conversion unit.
  • the DDR receives and throws data in a FIFO (First In First Out).
  • the DDR two different storage spaces store two DVI data (ie, left and right picture data).
  • data 1 and data 2 represent RX two output signals respectively. Due to the data transmission time difference, there is also a time difference between data 1 and data 2 to DDR.
  • the FPGA is used to detect two storage spaces to store picture data. Whether it is empty, it starts to transfer DDR data to the FPGA when it detects that both sets of data are stored. For example, if data 1 is transferred to DDR first than data 2, then DDR—stores data of data 1 directly. When it reaches the Nth row, FPGA detects data 2 and transmits data 1 and data 2 row by row. Transfer to the FPGA, then processed by the FPGA to the timing control module (TCON), and then transmitted to the LCD panel by TCON. At the same time, data 1 and data 2 are still transferred to the DDR, that is, subsequent data. DDR storage data 1 stores more than data 2 (N-1) rows Data, you can achieve normal display and synchronization of the picture.
  • the invention also discloses a driving method for an ultra high definition resolution liquid crystal panel, comprising the steps of:
  • the screen data input by each input signal interface is first stored in the storage module
  • step B When all the input signal interfaces have the same picture data storage in the storage module, go to step C; otherwise, return to step A;
  • the step A includes: establishing two storage spaces in the DDR memory module, and writing the screen data of the two input interfaces into the two storage spaces respectively; The contents of the two storage spaces, if the contents of the two storage spaces are not empty, the FPGA converts the picture data into a data format readable by the timing control module, and then sends them to all the timing control modules through the differential picture data line (LVDSTX). (TCON). If it is determined that any of the storage spaces is empty, then return to step A to continue storing the data.
  • LDDSTX differential picture data line
  • the screen data of different interfaces is stored through different storage spaces, and the data of each interface does not affect each other, so that it is determined whether the picture data of the corresponding interface is written by detecting whether the data of each storage space is empty, and the method is reliable. It is conducive to the design of the tube and reduces the design cost.
  • the FPGA is used to read the picture data line by line from the DDR memory module, and convert the picture data into a data format readable by the timing control module, and then sent to all the timing control modules at the same time, so that the DDR memory module can receive the picture data from the interface module at the same time.
  • the operation efficiency is high, and the data processing capability of the drive circuit can be improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶面板的驱动电路、包括该驱动电路的液晶显示装置及液晶面板的驱动方法。该驱动电路包括至少两个信号输入接口、时序控制模块、存储模块和数据处理模块。当该存储模块接收到所有信号输入接口的同一显示画面的画面数据以后,该数据处理模块从存储模块读取画面数据后发往时序控制模块,时序控制模块对液晶面板进行驱动。

Description

一种液晶面板驱动电路、 液晶显示装置及一种驱动方法
【技术领域】
本发明涉及液晶显示领域, 更具体的说, 涉及一种液晶面板驱动电路、 液 晶显示装置及一种驱动方法。
【背景技术】
目前市场常规液晶电视的接口有 HDMI、 DVL Display Port等, 但对于解 析度为 3840X2160及以上的超高清解析度液晶面板(LCD Panel ), 由于带宽限 制目前单路输入能支援到如此高解析度的接口只有 30Hz HDMI输入信号, 但人 眼易观察到闪烁。 因此常用架构为双路信号输入, 如图 1所示, 以 DVI输入为 例,将图像信号分割为 1/2, 然后分别通过两路输入信号从 DVI接口输入到可编 程逻辑阵列 (FPGA ), FPGA再将两路接口的信号进行合并处理, 将两个 1/2图 像信号合并, 然后进行误差处理、行间移位补偿等算法运算后再分割为 1/2显示 信号分别输出给各 TCON。 但此方案常常出现左右两边画面并不同步的情形, 影响画面正常显示。
【发明内容】
本发明所要解决的技术问题是提供一种提升液晶面板画面同步性能的液晶 面板驱动电路、 液晶显示装置及一种驱动方法。
本发明的目的是通过以下技术方案来实现的:
一种液晶面板的驱动电路, 包括至少两个信号输入接口、 时序控制模块, 所述驱动电路还包括存储模块和数据处理模块;
当所述存储模块接收到所有信号输入接口的同一显示画面的画面数据以 后, 所述数据处理模块从存储模块读取画面数据后发往时序控制模块, 时序控 制模块对液晶面板进行驱动。
进一步的, 所述时序控制模块至少有两个, 数据处理模块从存储模块读取 画面数据进行处理后, 同时发给所有的时序控制模块。 通过不同的存储空间来 存储不同的接口的画面数据, 每个接口的数据相互不影响, 这样通过检测每个 存储空间的数据是否为空来判断对应接口的画面数据是否写入, 方法筒单可靠, 有利于筒化设计, 降低设计成本。
进一步的, 所述数据处理模块包括将画面数据转换成时序控制模块可读的 数据格式的转换单元。 由于输入的视频信号格式多种多样, 因此可以增加转换 单元来进行数据处理, 无须改变时序控制模块, 这样可以减轻时序控制模块的 负担, 并增强时序控制模块的通用性。
进一步的, 所述存储模块包括至少两个存储空间, 所述每个存储空间存储 一个信号输入接口的画面数据, 当所有存储空间都有画面数据存入的时候, 所 述数据处理模块同时读取每个存储空间的画面数据, 然后发往所述时序控制模 块。 通过不同的存储空间来存储不同的接口的画面数据, 每个接口的数据相互 不影响, 这样通过检测每个存储空间的数据是否为空来判断对应接口的画面数 据是否写入, 方法筒单可靠, 有利于筒化设计, 降低设计成本。
进一步的, 所述时序控制模块至少有两个, 所述数据处理模块包括将画面 数据转换成时序控制模块可读的数据格式的转换单元, 所述存储模块包括至少 两个存储空间, 所述每个存储空间存储一个信号输入接口的画面数据, 当所有 存储空间都有画面数据存入的时候, 所述数据处理模块同时读取每个存储空间 的画面数据, 通过转换单元将画面数据转换成时序控制模块可读的数据格式后, 同时发给所有的时序控制模块。 此为一种具体的液晶面板驱动电路。
进一步的, 所述信号输入接口有两个, 所述存储模块的存储空间也有两个, 其中一个存储空间先输入画面数据, 当另一个存储空间写入第一行数据后, 所 述两个存储空间同时开始逐行传送画面数据给所述数据处理模块, 所述数据处 理模块将画面数据转换成时序控制模块可读的数据格式, 然后同时发往所有的 时序控制模块。 此为一个双接口的技术方案, 可以采用主流的双通道存储模块
(如 DDR )来存储画面数据。 处理模块。 此为一种逐行传送的方式, 存储模块可以一边从接口模块接收画面 数据, 一边将画面数据发往数据处理模块, 运行效率高, 可以提升驱动电路的 数据处理能力。
进一步的, 所述信号输入接口为数字视频接口 (DVI : Digital Visual Interface )、 高清晰度多媒体接口 ( HDMI: High Definition Multimedia Interface ) 或高清数字显示接口 ( DisplayPort )中的任意一种; 所述数据处理模块为可编程 逻辑阵列 (FPGA: Field - Programmable Gate Array )„ 本发明适用于现有的多种 数据接口, 适用范围广。
一种液晶显示装置, 包括上述任意一种液晶面板的驱动电路。
一种多路信号输入的液晶面板的驱动方法, 包括步骤:
A、 等待每个输入信号接口输入的画面数据, 并存储到存储模块;
B、 当所有的输入信号接口在存储模块中都有同一画面数据存储的时候, 转 步骤 C; 否则返回步骤 A;
C、 将所有的当前画面数据同步发往时序控制模块对面板进行驱动。 进一步 的, 所述时序控制模块至少有两个, 所述步骤 A中包括: 在存储模块内建立两 个跟输入接口数量相同的存储空间, 将两个输入接口的画面数据分别写入对应 的存储空间; 所述步骤 B检测每个存储空间的内容, 如果两个存储空间内容都 不为空, 转步骤 C, 否则返回步骤 A。
所述步骤 C包括: 采用数据处理模块从存储模块读取画面数据, 并将画面 数据转换成时序控制模块可读的数据格式, 然后同时发往所有的时序控制模块。
通过不同的存储空间来存储不同的接口的画面数据, 每个接口的数据相互 不影响, 这样通过检测每个存储空间的数据是否为空来判断对应接口的画面数 据是否写入, 方法筒单可靠, 有利于筒化设计, 降低设计成本。
进一步的, 所述步骤 C包括: 采用数据处理模块从存储模块逐行读取画面 数据, 并将画面数据转换成时序控制模块可读的数据格式, 然后同时发往所有 的时序控制模块。 此为一种逐行传送的方式, 存储模块可以一边从接口模块接 收画面数据, 一边将画面数据发往数据处理模块, 运行效率高, 可以提升驱动 电路的数据处理能力。
发明人研究发现, 左右两边画面不同步的现象主要是由于显示卡或其他显 示装置在接受多路输入可能因为信道速度原因造成个别数据延迟, 画面数据存 在一定的时间差, 时间差异大小也不定(一行数据或者更多), 则 FPGA则会对 不同帧的数据当作同一帧的数据进行同时处理, 造成左右两边画面不能准确同 步, 从而影响画面正常显示。 而本发明由于采用了存储模块, 先将每一路输入 信号接口的画面数据先存储起来, 等每一路接口都有同一显示画面的画面数据 存储以后, 然后同时发往所有的时序控制模块, 这样每个时序控制模块就可以 在同一时间接收到同一显示画面的画面数据, 并同步驱动现有的数据线进行显 示, 这样每个时序控制模块对应的显示区域就在同一时间显示对应的画面, 形 成完整的画面, 解决了现有技术画面不同步的问题, 提升显示品质。
【附图说明】
图 1是现有的一种液晶面板的驱动示意图;
图 2是本发明原理示意图;
图 3是本发明实施例采用两路信号输入的原理示意图;
图 4是本发明实施例 DDR内存模块刚开始存储数据时, 两个存储空间的数 据结构示意图;
图 5是本发明实施例的 DDR内存模块刚存储数据后, 两个存储空间的数据 结构示意图;
图 6是本发明实施例的方法示意图。
【具体实施方式】
本发明公开了一种液晶显示装置, 液晶显示装置包括一种液晶面板的驱动 电路。 如图 2所示, 该液晶面板的驱动电路包括至少两个信号输入接口、 时序 控制模块, 驱动电路还包括存储模块和数据处理模块;
当所述存储模块接收到所有信号输入接口的同一显示画面的画面数据以 后, 数据处理模块从存储模块读取画面数据后发往时序控制模块, 时序控制模 块对液晶面板进行驱动。
发明人研究发现, 由于显示卡或其他显示装置在接受多路输入画面数据存 在一定的时间差, 时间差异大小也不定(一行数据或者更多), 造成左右两边画 面不同步, 从而影响画面正常显示。 本发明由于采用了存储模块, 先将每一路 输入信号接口的画面数据先存储起来, 等每一路接口都有同一显示画面的画面 数据存储以后, 然后同时发往所有的时序控制模块, 这样每个时序控制模块就 可以在同一时间接收到同一显示画面的画面数据, 并同步驱动现有的数据线进 行显示, 这样每个时序控制模块对应的显示区域就在同一时间显示对应的画面, 形成完整的画面, 解决了现有技术画面不同步的问题, 提升显示品质。
数据处理模块还可以包括将画面数据转换成时序控制模块可读的数据格式 的转换单元。 由于输入的视频信号格式多种多样, 因此可以增加转换单元来进 行数据处理, 无须改变时序控制模块, 这样可以减轻时序控制模块的负担, 并 增强时序控制模块的通用性。
下面以两路 DVI输入为例, 结合附图和较佳的实施例对本发明作进一步说 明。
图 3所示为一个 3840*2160超高清解析度液晶面板的驱动电路, 其包括两 个 DVI信号输入接口、 每个 DVI接收 1920*2160的数据流, 即同一显示画面的 1/2画面数据, 其对应的画面数据输入到 DDR内存模块中, DDR内存模块包括 两个存储空间 (地址 1和地址 2 ) , 每个存储空间存储一个 DVI信号输入接口的 画面数据。
数据处理模块可以选用可编程逻辑阵列(FPGA: Field - Programmable Gate Array ), 当所有存储空间都有画面数据存入的时候, 可编程逻辑阵列 ( FPGA: Field - Programmable Gate Array )同时读取每个存储空间的画面数据并转换成时 序控制模块可读的数据格式, 然后同时发往所有的时序控制模块。 通过不同的 存储空间来存储不同的接口的画面数据, 每个接口的数据相互不影响, 这样通 过检测每个存储空间的数据是否为空来判断对应接口的画面数据是否写入, 方 法筒单可靠, 有利于筒化设计, 降低设计成本。 一种逐行传送的方式, DDR内存模块可以一边从接口模块接收画面数据, 一边 将画面数据发往数据处理模块, 运行效率高, 可以提升驱动电路的数据处理能 力。
本实施例是一个双接口的技术方案, 可以采用主流的双通道存储模块(如 DDR )来存储画面数据。 当然, 本发明还仅适用于数字视频接口 (DVI: Digital Visual Interface ), 还可以应用于高清晰度多媒体接口 (HDMI: High Definition Multimedia Interface ), 高清数字显示接口 ( DisplayPort )等其他高清数据接口。
数据处理模块除了可编程逻辑阵列, 还可以采用其他可进行数据格式转换 及同步输出的电路。 当然, 数据处理模块也可以不带转换单元的功能。
在 DVI RX和 FPGA之间增加一颗 DDR, 用来存储 DVI RX丟出的左右两 边画面数据。 DDR接收和丟出数据均为先进先出架构( FIFO: First In First Out ), DDR两个不同存储空间分别存储两路 DVI数据(即左右画面数据)。
如图 4、 5所示, 假设数据 1和数据 2分别代表 RX两路输出信号, 因数据 传输时间差, 数据 1和数据 2到 DDR也存在时间差, 利用 FPGA来侦测两个存 储空间存储画面数据是否为空, 当侦测到两组数据均有存储时开始将 DDR数据 传输至 FPGA。 例如数据 1比数据 2先传输到 DDR, 则 DDR—直存储数据 1 的数据, 到第 N行时, FPGA侦测到数据 2传输完第一条数据后, 将数据 1和 数据 2数据逐行传送到 FPGA,再经由 FPGA处理后到时序控制模块( TCON ), 再由 TCON传送给液晶面板( LCD Panel ) , 与此同时, 数据 1和数据 2仍在传 送存储到 DDR中, 亦即后续数据 DDR存储数据 1 比数据 2多存储( N-1 )行 数据, 则可以实现画面正常显示以及同步。
本发明还公开了一种超高清解析度液晶面板的驱动方法, 包括步骤:
A、 将每个输入信号接口输入的画面数据先存储到存储模块;
A、 等待每个输入信号接口输入的画面数据, 并存储到存储模块;
B、 当所有的输入信号接口在存储模块中都有同一画面数据存储的时候, 转 步骤 C; 否则返回步骤 A;
C、将所有的当前画面数据同步发往时序控制模块对面板进行驱动。图 6中, 输入信号接口有两个,所述步骤 A中包括: 在 DDR内存模块内建立两个存储空 间, 将两个输入接口的画面数据分别写入两个存储空间; 所述步骤 B检测两个 存储空间的内容,如果两个存储空间内容都不为空, FPGA将画面数据转换成时 序控制模块可读的数据格式, 然后通过差分画面数据线(LVDSTX )同时发往所 有的时序控制模块(TCON )。 如果判断其中任何一个存储空间为空, 则返回步 骤 A继续存储数据。 通过不同的存储空间来存储不同的接口的画面数据, 每个 接口的数据相互不影响, 这样通过检测每个存储空间的数据是否为空来判断对 应接口的画面数据是否写入, 方法筒单可靠, 有利于筒化设计, 降低设计成本。
采用 FPGA从 DDR内存模块逐行读取画面数据,并将画面数据转换成时序 控制模块可读的数据格式, 然后同时发往所有的时序控制模块, 这样 DDR内存 模块可以一边从接口模块接收画面数据, 一边将画面数据发往 FPGA,运行效率 高, 可以提升驱动电路的数据处理能力。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明, 不 能认定本发明的具体实施只局限于这些说明。 对于本发明所属技术领域的普通 技术人员来说, 在不脱离本发明构思的前提下, 还可以做出若干筒单推演或替 换, 都应当视为属于本发明的保护范围。

Claims

权利要求
1、一种液晶面板的驱动电路, 包括至少两个信号输入接口、 时序控制模块, 所述驱动电路还包括存储模块和数据处理模块;
当所述存储模块接收到所有信号输入接口的同一显示画面的画面数据以 后, 所述数据处理模块从存储模块读取画面数据后发往时序控制模块, 时序控 制模块对液晶面板进行驱动。
2、 如权利要求 1所述的一种液晶面板的驱动电路, 其中, 所述时序控制模 块至少有两个, 数据处理模块从存储模块读取画面数据进行处理后, 同时发给 所有的时序控制模块。
3、 如权利要求 1所述的一种液晶面板的驱动电路, 其中, 所述数据处理模 块包括将画面数据转换成时序控制模块可读的数据格式的转换单元。
4、 如权利要求 1所述的一种液晶面板的驱动电路, 其中, 所述存储模块包 括至少两个存储空间, 所述每个存储空间存储一个信号输入接口的画面数据, 当所有存储空间都有画面数据存入的时候, 所述数据处理模块同时读取每个存 储空间的画面数据, 然后发往所述时序控制模块。
5、 如权利要求 1所述的一种液晶面板的驱动电路, 其中, 所述时序控制模 块至少有两个, 所述数据处理模块包括将画面数据转换成时序控制模块可读的 数据格式的转换单元, 所述存储模块包括至少两个存储空间, 所述每个存储空 间存储一个信号输入接口的画面数据, 当所有存储空间都有画面数据存入的时 候, 所述数据处理模块同时读取每个存储空间的画面数据, 通过转换单元将画 面数据转换成时序控制模块可读的数据格式后, 同时发给所有的时序控制模块。
6、 如权利要求 1所述的一种液晶面板的驱动电路, 其中, 所述存储空间的 画面数据采用逐行传送的方式传送给所述数据处理模块。
7、 如权利要求 1所述的一种液晶面板的驱动电路, 其中, 所述信号输入接 口为数字视频接口、 高清晰度多媒体接口或高清数字显示接口中的任意一种; 所述数据处理模块为可编程逻辑阵列。
8、 一种液晶显示装置, 包括一种液晶面板的驱动电路, 所述液晶面板的驱 动电路, 包括至少两个信号输入接口、 时序控制模块, 所述驱动电路还包括存 储模块和数据处理模块;
当所述存储模块接收到所有信号输入接口的同一显示画面的画面数据以 后, 所述数据处理模块从存储模块读取画面数据后发往时序控制模块, 时序控 制模块对液晶面板进行驱动。
9、 如权利要求 8所述的一种液晶显示装置, 其中, 所述时序控制模块至少 有两个, 数据处理模块从存储模块读取画面数据进行处理后, 同时发给所有的 时序控制模块。
10、 如权利要求 8所述的一种液晶显示装置, 其中, 所述数据处理模块包 括将画面数据转换成时序控制模块可读的数据格式的转换单元。
11、 如权利要求 8 所述的一种液晶显示装置, 其中, 所述存储模块包括至 少两个存储空间, 所述每个存储空间存储一个信号输入接口的画面数据, 当所 有存储空间都有画面数据存入的时候, 所述数据处理模块同时读取每个存储空 间的画面数据, 然后发往所述时序控制模块。
12、 如权利要求 8所述的一种液晶显示装置, 其中, 所述时序控制模块至 少有两个, 所述数据处理模块包括将画面数据转换成时序控制模块可读的数据 格式的转换单元, 所述存储模块包括至少两个存储空间, 所述每个存储空间存 储一个信号输入接口的画面数据, 当所有存储空间都有画面数据存入的时候, 所述数据处理模块同时读取每个存储空间的画面数据, 通过转换单元将画面数 据转换成时序控制模块可读的数据格式后, 同时发给所有的时序控制模块。
13、 如权利要求 8所述的一种液晶显示装置, 其中, 所述存储空间的画面 数据采用逐行传送的方式传送给所述数据处理模块。
14、 如权利要求 8所述的一种液晶显示装置, 其中, 所述信号输入接口为 数字视频接口、 高清晰度多媒体接口或高清数字显示接口中的任意一种; 所述 数据处理模块为可编程逻辑阵列。
15、 一种多路信号输入的液晶面板的驱动方法, 包括步骤:
A、 等待每个输入信号接口输入的画面数据, 并存储到存储模块;
B、 当所有的输入信号接口在存储模块中都有同一画面数据存储的时候, 转 步骤 C; 否则返回步骤 A;
C、 将所有的当前画面数据同步发往时序控制模块对面板进行驱动。
16、如权利要求 15所述的一种多路信号输入的液晶面板的驱动方法,其中, 所述时序控制模块至少有两个, 所述步骤 A中包括: 在存储模块内建立两个跟 输入接口数量相同的存储空间, 将两个输入接口的画面数据分别写入对应的存 储空间; 所述步骤 B检测每个存储空间的内容, 如果两个存储空间内容都不为 空, 转步骤 C, 否则返回步骤 A;
所述步骤 C包括: 采用数据处理模块从存储模块读取画面数据, 并将画面 数据转换成时序控制模块可读的数据格式, 然后同时发往所有的时序控制模块。
PCT/CN2012/085478 2012-11-27 2012-11-28 一种液晶面板驱动电路、液晶显示装置及一种驱动方法 WO2014082231A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/807,734 US20150279312A1 (en) 2012-11-27 2012-11-28 Lcd panel driving circuit, lcd device, and driving method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210487345.5A CN102968972B (zh) 2012-11-27 2012-11-27 一种液晶面板驱动电路、液晶显示装置及一种驱动方法
CN201210487345.5 2012-11-27

Publications (1)

Publication Number Publication Date
WO2014082231A1 true WO2014082231A1 (zh) 2014-06-05

Family

ID=47799081

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/085478 WO2014082231A1 (zh) 2012-11-27 2012-11-28 一种液晶面板驱动电路、液晶显示装置及一种驱动方法

Country Status (3)

Country Link
US (1) US20150279312A1 (zh)
CN (1) CN102968972B (zh)
WO (1) WO2014082231A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103236243B (zh) * 2013-04-24 2016-03-30 青岛海信电器股份有限公司 一种显示装置和电视机
CN103778893A (zh) * 2014-02-07 2014-05-07 北京京东方视讯科技有限公司 一种背光控制方法、背光控制装置及显示设备
CN103956149B (zh) * 2014-04-21 2016-03-23 合肥鑫晟光电科技有限公司 显示器、显示系统和数据处理方法
US10388243B2 (en) 2014-05-06 2019-08-20 Novatek Microelectronics Corp. Driving system and method for driving display panel and display device thereof
CN105096848A (zh) * 2014-05-19 2015-11-25 联咏科技股份有限公司 控制源极驱动电路的方法、控制芯片及显示设备
CN105704446B (zh) * 2016-01-19 2018-12-07 浙江大华技术股份有限公司 一种多窗口视频切换的方法及装置
CN106205454A (zh) * 2016-07-06 2016-12-07 昀光微电子(上海)有限公司 一种硅基微显示器模组
CN108470549A (zh) * 2018-05-22 2018-08-31 深圳市国华光电科技有限公司 一种基于电润湿电子纸的显示系统及方法
CN111464866B (zh) * 2020-04-08 2022-03-08 Tcl华星光电技术有限公司 时序控制芯片、视频格式转换系统及方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844574A (en) * 1995-05-22 1998-12-01 Umax Data Systems, Inc. System for enabling a CPU and an image processor to synchronously access a RAM
CN101136189A (zh) * 2007-10-16 2008-03-05 友达光电股份有限公司 显示器及其中传送影像数据的方法
CN101174389A (zh) * 2006-10-31 2008-05-07 奇美电子股份有限公司 液晶显示器的驱动电路与方法
CN101516015A (zh) * 2008-12-31 2009-08-26 广东威创视讯科技股份有限公司 多路视频数据采集处理和传输的装置及其方法
CN101727875A (zh) * 2009-12-24 2010-06-09 中国航空工业集团公司第六三一研究所 一种图形处理设备及方法
US8294656B2 (en) * 2006-08-03 2012-10-23 Samsung Display Co., Ltd. Signal control device, liquid crystal display having the same and signal control method using the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4572128B2 (ja) * 2005-03-04 2010-10-27 Nec液晶テクノロジー株式会社 表示パネルの駆動方法及びその装置
US20070262944A1 (en) * 2006-05-09 2007-11-15 Himax Technologies Limited Apparatus and method for driving a display panel
KR101642849B1 (ko) * 2009-06-02 2016-07-27 삼성디스플레이 주식회사 구동 장치의 동기화 방법 및 이를 수행하기 위한 표시 장치
TWI462076B (zh) * 2012-03-09 2014-11-21 Au Optronics Corp 顯示裝置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844574A (en) * 1995-05-22 1998-12-01 Umax Data Systems, Inc. System for enabling a CPU and an image processor to synchronously access a RAM
US8294656B2 (en) * 2006-08-03 2012-10-23 Samsung Display Co., Ltd. Signal control device, liquid crystal display having the same and signal control method using the same
CN101174389A (zh) * 2006-10-31 2008-05-07 奇美电子股份有限公司 液晶显示器的驱动电路与方法
CN101136189A (zh) * 2007-10-16 2008-03-05 友达光电股份有限公司 显示器及其中传送影像数据的方法
CN101516015A (zh) * 2008-12-31 2009-08-26 广东威创视讯科技股份有限公司 多路视频数据采集处理和传输的装置及其方法
CN101727875A (zh) * 2009-12-24 2010-06-09 中国航空工业集团公司第六三一研究所 一种图形处理设备及方法

Also Published As

Publication number Publication date
CN102968972B (zh) 2016-03-02
CN102968972A (zh) 2013-03-13
US20150279312A1 (en) 2015-10-01

Similar Documents

Publication Publication Date Title
WO2014082231A1 (zh) 一种液晶面板驱动电路、液晶显示装置及一种驱动方法
WO2017113951A1 (zh) 拼接显示系统及其显示方法
JP5766403B2 (ja) 液晶ディスプレーの駆動回路および駆動方法
CN103957374A (zh) 一种基于dp接口的8k超高清显示系统
TWI579819B (zh) 顯示驅動器積體電路及其顯示資料處理方法
CN103065598B (zh) 一种防止液晶显示器花屏的控制方法
WO2022022106A1 (zh) 图像数据处理装置、方法及显示装置
CN107249107B (zh) 视频控制器和图像处理方法及装置
WO2015161574A1 (zh) 用于led电视的数据处理方法、装置及led电视
US20120147976A1 (en) Video Transmission On A Serial Interface
WO2020156284A1 (zh) 显示驱动装置、其控制方法及显示装置
TWI514844B (zh) 具有視訊格式轉換的時序控制裝置、時序控制裝置的方法以及其顯示系統
CN104038719A (zh) 一种基于视频帧的超高清视频显示系统及方法
WO2023116320A1 (zh) 基于fpga的数据流处理方法、装置及pg设备
JP2014067415A (ja) ディスプレードライバ集積回路及びディスプレーデータ処理方法
JP2020071469A (ja) 画像制御装置およびそれを用いたディスプレイウォールシステム並びにディスプレイウォールに画像を出力する制御方法
KR20170039335A (ko) 디스플레이 장치, 그의 디스플레이 방법 및 디스플레이 시스템
CN114267293B (zh) 显示装置及其显示方法
CN102625086B (zh) 一种用于高清数字矩阵的ddr2存储方法和系统
TWI411834B (zh) 液晶顯示裝置及其驅動方法
TWI559291B (zh) 資料緩衝裝置以及資料緩衝方法
CN108259875B (zh) 一种数字图像伽马校正硬件实现方法及系统
TW201246177A (en) Timing controller and driving method thereof
CN202205442U (zh) 多画面液晶显示控制电路
JP2002221952A (ja) 画像データ伝送方法並びに該伝送方法を用いた画像表示システム及び表示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13807734

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12889271

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12889271

Country of ref document: EP

Kind code of ref document: A1