WO2015161574A1 - 用于led电视的数据处理方法、装置及led电视 - Google Patents

用于led电视的数据处理方法、装置及led电视 Download PDF

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Publication number
WO2015161574A1
WO2015161574A1 PCT/CN2014/083167 CN2014083167W WO2015161574A1 WO 2015161574 A1 WO2015161574 A1 WO 2015161574A1 CN 2014083167 W CN2014083167 W CN 2014083167W WO 2015161574 A1 WO2015161574 A1 WO 2015161574A1
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WIPO (PCT)
Prior art keywords
video
signal
video signal
data
led
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Application number
PCT/CN2014/083167
Other languages
English (en)
French (fr)
Inventor
雷伟林
卢长军
张龙虎
孙铮
Original Assignee
利亚德光电股份有限公司
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Filing date
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Application filed by 利亚德光电股份有限公司 filed Critical 利亚德光电股份有限公司
Priority to KR1020167017665A priority Critical patent/KR102027371B1/ko
Priority to US15/111,381 priority patent/US9762814B2/en
Priority to CA2936373A priority patent/CA2936373C/en
Priority to JP2016544615A priority patent/JP2017520939A/ja
Priority to EP14889939.6A priority patent/EP3082334A4/en
Publication of WO2015161574A1 publication Critical patent/WO2015161574A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/265—Mixing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005—Adapting incoming signals to the display format of the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/92—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
    • H04N5/9201—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving the multiplexing of an additional signal and the video signal
    • H04N5/9205—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving the multiplexing of an additional signal and the video signal the additional signal being at least another television signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/123—Frame memory handling using interleaving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/126—The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/127—Updating a frame memory using a transfer of data from a source area to a destination area
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • the present invention relates to the field of LEDs, and in particular to a data processing method and apparatus for an LED television and an LED television.
  • BACKGROUND OF THE INVENTION Currently, self-illuminating LED TVs are display device products that have appeared recently with the development of LED display technology. High-definition self-illuminating LED displays can realize ultra-small pitch, high-definition physical resolution and other functions, and have strong color performance. The advantages of gray scale and contrast are obvious. It is completely suitable for displaying signals and images in various video interface forms. However, the existing LED TV has a single video interface and displays the received TV signal directly on the LED display. The picture is very poor and the user's visual effect is very poor.
  • the past LED display technology mainly appears in the form of a display screen, generally a single video interface access form (such as VGA or DVI, etc.), and directly displays the connected TV signal on the screen, without
  • the signal to be accessed is processed in any way, that is, the existing LED TV is often only used as a function of the display screen, and does not have the function of a television, and the displayed picture quality is poor.
  • the LED television can only display a single-standard television signal in the prior art, an effective solution has not been proposed yet.
  • SUMMARY OF THE INVENTION In view of the problem that the LED television can only display a single-standard television signal in the related art, an effective solution has not been proposed yet.
  • a data processing apparatus for an LED television includes: a signal processing chip, configured to perform a standard conversion of the received television signal.
  • the first video signal is set; the video processing chip is connected to the signal processing chip, and is configured to perform clock synchronization processing on the first video signal to obtain a second video signal, and output the second video signal to the LED display.
  • the signal processing chip transmits the first video signal to the video processing chip through the low voltage differential interface, wherein the low voltage differential interface is configured to divide the first video signal into the first low voltage differential according to the resolution of the video.
  • the video stream and the second low voltage differential video stream transmit the first low voltage differential video stream and the second low voltage differential video stream to the video processing chip, the first low voltage differential video stream comprising two differential data streams.
  • the video processing chip includes: a decoder connected to the signal processing chip, configured to decode the first low-voltage differential video stream to obtain two video signals, and decode the second low-voltage differential video stream to obtain a third video signal; And connected to the decoder, configured to perform clock synchronization processing on the two video signals and the third video signal to obtain a second video signal.
  • the clock processor includes: a video combiner connected to the decoder, configured to combine the two video signals into a fourth video signal; and the clock processor is configured to perform clock synchronization processing on the third video signal and the fourth video signal. Second video signal.
  • the video combiner includes: two line buffers, the two line buffers are connected to the decoder, and the video streams of the two data channels of the two video signals are respectively input into the corresponding line buffers;
  • the reader is connected to the two line buffers for performing a data reading operation on the two line buffers at a double clock frequency to obtain a fourth video signal.
  • the video processing chip further includes: a video output port, connected to the signal processing chip, configured to divide the second video signal into a preset number of sub-videos, and output the sub-video to a display unit corresponding to the LED display for display .
  • the data processing apparatus further includes: a control chip, configured to send the determined preset coordinates to the video output port; and the video output port is configured to output the sub video to the corresponding display unit according to the preset coordinates.
  • the video output port includes: a frame memory, configured to store a second video signal, wherein the frame memory includes a preset number of sub-ports; and the second reader is connected to the frame memory for reading according to a preset The rule reads the video data from the sub-port polling; the buffer is configured to cache the video data of each channel read, and exchanges the video data of each channel in a clock domain to obtain a preset number of sub-videos; an output interface, Connected to the buffer for outputting a preset number of sub-videos using time division multiplexing.
  • an LED television including a data processing apparatus including a data processing apparatus.
  • a data processing method for an LED television includes: performing a system conversion on a received television signal to obtain a first video of a preset format. Signal; performing clock synchronization processing on the first video signal to obtain a second video signal; The frequency signal is divided into a preset number of sub-videos; the sub-video is output to a display unit corresponding to the LED display for display.
  • a data processing apparatus for an LED television is provided.
  • the data processing apparatus includes: a conversion module, configured to perform a standard conversion of the received television signal to obtain a preset a first video signal of the system; a clock processing module, configured to perform clock synchronization processing on the first video signal to obtain a second video signal; and a segmentation module, configured to divide the second video signal into a preset number of sub-videos; , for outputting the sub video to the display unit corresponding to the LED display for display.
  • the received television signal is converted into a preset standard video signal by the signal processing chip, and the video processing chip processes the output value LED display, which can solve the prior art that the LED television can only display the single standard television signal.
  • the problem is that the LED TV can display the effects of multiple formats and multiple formats of video.
  • FIG. 1 is a schematic structural diagram of a data processing apparatus for an LED television according to an embodiment of the present invention
  • FIG. 2 is an alternative structure of a data processing apparatus for an LED television according to an embodiment of the present invention.
  • FIG. 3 is a timing diagram of acquiring a fourth video signal according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a region for determining a display unit according to an embodiment of the present invention
  • FIG. 5 is a view for reading sub-video data according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of a data processing method for an LED television according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a data processing apparatus for an LED television according to an embodiment of the present invention.
  • LED autonomous illumination means that the LED device can actively emit light after being excited by electricity or other energy, and the liquid crystal itself does not emit light, indicating light transmission.
  • FIG. 1 is a block diagram showing the structure of a data processing apparatus for an LED television according to an embodiment of the present invention.
  • 2 is a block diagram showing an alternative data processing apparatus for an LED television in accordance with an embodiment of the present invention. As shown in FIG. 1 and FIG.
  • the apparatus may include: a signal processing chip 10, configured to perform a system conversion on the received television signal to obtain a first video signal of a preset format; a video processing chip 20, and a signal processing chip 10
  • the connection is configured to perform clock synchronization processing on the first video signal to obtain a second video signal, and output the second video signal to the LED display 40.
  • the signal processing chip 10 in the above embodiment may be a TV processing chip, such as Pixelworks (the top image display chip manufacturer in the US), Mstar (embedded IC chip), and the video processing chip 20 uses a programmable logic array FPGA.
  • the signal processing chip 10 and the video processing chip 20 each have a memory with a storage capacity greater than 128 Mbit (such as a frame memory SDRAM, DDR), and the signal processing chip performs television through the accessed TV television signal (including a high frequency head).
  • the standard conversion, image enhancement and scaling processing in addition, the signal processing chip can also access other signals HDMI (high-definition multimedia interface, which is a digital interface), USB (Universal Serial Bus) and YPrPb (color difference terminal ), etc. to process the signal.
  • HDMI high-definition multimedia interface, which is a digital interface
  • USB Universal Serial Bus
  • YPrPb color difference terminal
  • SDRAM is synchronous dynamic random access memory
  • DDR is double rate synchronous dynamic random access memory
  • IC chip is integrated circuit.
  • the data processing device for the LED television in the above embodiment can be built in the LED TV.
  • the received television signal is converted into a preset standard video signal by the signal processing chip, and the video processing chip processes the output value LED display, which can solve the prior art that the LED television can only display the single standard television signal.
  • the problem is that the LED TV can display the effects of multiple formats and multiple formats of video.
  • the television processing chip performs the system conversion of the television signal, the video decoding and decryption of the plurality of interfaces, the image scaling, the image quality enhancement, and the remote control function.
  • the first video signal obtained by the television processing chip 10 is a fixed resolution video stream, and the video stream is output to the video processing chip in the form of a protocol of LVDS (Low Voltage Differential Signal Technology Interface), and the video processing chip A programmable logic array is used to process the input video stream of the television processing chip through a programmable logic chip.
  • the signal processing chip transmits the first video signal to the video processing chip through the low voltage differential interface, wherein the low voltage differential interface is configured to divide the first video signal into the first according to the resolution of the video.
  • the low voltage differential video stream and the second low voltage differential video stream transmit the first low voltage differential video stream and the second low voltage differential video stream to the video processing chip, the first low voltage differential video stream comprising two differential data streams.
  • the video stream of the first video signal processed by the television processing chip may be divided into one group or two groups of LVDS video outputs to a programmable logic chip (ie, a video processing chip) according to the resolution of the video, and each group of LVDS— Generally includes 1 pair of differential clocks, and 3 or 4 pairs of differential data streams.
  • the video processing chip 20 may include: a decoder connected to the signal processing chip, configured to decode the first low-voltage differential video stream to obtain two video signals, and decode the second low-voltage differential video stream.
  • the video processing chip After receiving the first low-voltage differential video stream and the second low-voltage differential video stream, the video processing chip first performs LVDS video stream decoding, and performs clock synchronization on the decoded data when decoding the same. In the above processing, for two sets of LVDS-transmitted high-resolution video streams (ie, the first low-voltage differential video stream), the video processing chip needs to decode and combine the two video signals in the first low-voltage differential video stream.
  • the clock processor may include: a video combiner connected to the decoder, configured to combine the two video signals into a fourth video signal; and a clock processor configured to clock synchronize the third video signal and the fourth video signal A second video signal is obtained.
  • the video combiner may include: two line buffers, the two line buffers are connected to the decoder, and the video streams of the two data channels of the two video signals are respectively input to the corresponding line buffers.
  • the first data reader is connected to the two line buffers for performing a data reading operation on the two line buffers at a clock frequency that is doubled to obtain a fourth video signal. As shown in FIG.
  • two video signals are combined (one of the video signals is data 01, 02, 03, 04, 05, 06, 07, ..., ...) of the data channel 1, and the other video signal is a data channel.
  • the processing data of 2, El, E2, E3, E4, E5, E6, E7, ...) is to interleave two channels of data into one channel of data, that is, to output data of data channel 1 by data, and then output data.
  • One data of channel 2 is sequentially interleaved to output data of two channels. Since the time of the line validity period is unchanged, the combined pixel data clock frequency is doubled.
  • two line buffers are used, and the video streams of the two data channels are respectively input into the respective line buffers, and the data buffer of the two line buffers is read by using the clock frequency clock which is doubled. Operation, that is, one data is read in the line buffer 1, and then another data is read in another buffer, and sequentially performed alternately to obtain a fourth video signal, as shown in FIG. 3: 01, El, 02, E2 03, E3, 04, E4, 05, E5, 06, E6, 07, E7, ....
  • a low resolution video stream ie, a second low voltage differential video stream
  • no merging of video data is required.
  • the video processing chip may further include: a video output port, connected to the signal processing chip, configured to divide the second video signal into a preset number of sub-videos, and output the sub-video to the LED
  • the display unit corresponding to the display is displayed. Since the LED high-definition television panel adopts the display unit to be spliced into an overall display screen, the data stream transmitted by the video processing chip to the LED display can adopt a multi-channel parallel data stream, specifically, setting the data stream output to the LED screen.
  • the entire frame of the video image can be divided into n sub-pictures (n blocks can be spliced into one complete image), and the corresponding sub-pictures of each video are output to the corresponding display unit for display, then fixed
  • the transfer rate is greatly reduced.
  • n is the preset number and n is a natural number.
  • the 1/n data amount of the original image is transmitted in one field period, and the transmission rate is about 1/n of the original, which improves the reliability of video transmission.
  • the data processing apparatus may further include: the control chip 30 shown in FIG.
  • the control chip can be implemented by using a microcontroller MCU.
  • the LED processing chip, the video processing chip and the control chip are combined to realize the LED high-definition television processing system, which not only improves the reliability of the video transmission, but also improves the flexibility of the video control.
  • a flexible configuration can be used to set the range of each specific transmitted image area. Specifically, the range of the transmission image is determined by the preset coordinates determined by the control chip to output the sub video to the corresponding display unit.
  • each transmitted image area is determined by setting the position (X, Y) of the upper left corner of the image area in the entire frame image.
  • four sub-video outputs are shown to the LED display screen, and the display units corresponding to the four-way sub-video are area 1, area 2, area 3 and area 4, respectively, wherein the area of each display unit is determined using the upper left.
  • the angular coordinates (x, y) determine their position in the entire frame image, as shown in Figure 4, the four coordinates (xl, yl), (x2, y2), (x3, y3), and (x4, y4)
  • the display position (or display unit) of the area 1 to the area 4 is determined.
  • the position of the respective area can be adjusted by setting the coordinates of X, Y (ie, preset coordinates).
  • the microprocessor ie, the control chip
  • the control chip is used to obtain the preset coordinates.
  • the control chip may be configured in a form of a network or a serial port to obtain preset coordinates.
  • each sub-video can also be encoded by LVDS again, and then output to the LED screen display.
  • the video output port may include: a frame memory, configured to store a second video signal, where the frame memory includes a preset number of sub-ports; and a second reader is coupled to the frame memory for
  • the preset read rule reads the video data from the sub-port polling; the buffer is used to buffer the video data of each channel read, and the video data of each channel is exchanged in the clock domain to obtain a preset number of sub-videos.
  • the output interface is connected to the buffer for outputting a preset number of sub-videos by means of time division multiplexing.
  • the frame memory may be used for storage, and then the video data is read according to a preset reading rule.
  • the number of data is 256) is the data of port 0, the second time to read 256 pixel data of port 1, the third time to read 256 pixel data of port 2, the fourth time to read port 256 of 256 Pixel data, so that the four ports are cyclically read, and then the video data of each channel is buffered for buffering of the clock domain.
  • the clock frequency of the buffer writing is approximately four times the reading frequency, so that the reading is performed.
  • the data stream will be contiguous.
  • the multi-output mode will ensure the strict synchronous output of the 4-channel video, so that the problem of the unsynchronized tear-like image feeling of the full-screen display moving image due to the high LED refresh frequency is not generated.
  • the present invention also provides an LED display device, which may include the data processing device of any of the above embodiments.
  • the received television signal is converted into a preset standard video signal by the signal processing chip, and the video processing chip processes the output value LED display, which can solve the prior art that the LED television can only display the single standard television signal.
  • the problem is that the LED TV can display the effects of multiple formats and multiple formats of video.
  • Step S602 Perform a standard conversion of the received television signal to obtain a first video signal of a preset format.
  • Step S604 Perform clock synchronization processing on the first video signal to obtain a second video signal.
  • Step S606 The second video signal is divided into a preset number of sub-videos.
  • Step S608 Output the sub video to the display unit corresponding to the LED display for display.
  • the received television signal is converted into a preset standard video signal by the signal processing chip, and the video processing chip processes the output value LED display, which can solve the prior art that the LED television can only display the single standard television signal.
  • the problem is that the LED TV can display the effects of multiple formats and multiple formats of video; and after dividing the second video signal into a preset number of sub-videos, the sub-video is output to the corresponding display unit of the LED display. Displaying can improve the reliability of video transmission and increase the flexibility of video control.
  • the data processing method in this embodiment of the present invention can be implemented by using a method for processing video data by each chip in the above embodiment.
  • FIG. 7 is a schematic diagram of a data processing apparatus for an LED television in accordance with an embodiment of the present invention. As shown in FIG.
  • the data processing apparatus may include: a conversion module 50, configured to perform a system conversion on the received television signal to obtain a first video signal of a preset format; and a clock processing module 60, configured to use the first video signal Performing a clock synchronization process to obtain a second video signal; a segmentation module 70, configured to divide the second video signal into a preset number of sub-videos; and an output module 80, configured to output the sub-video to a display unit corresponding to the LED display for display .
  • the received television signal is converted into a preset standard video signal by the signal processing chip, and the video processing chip processes the output value LED display, which can solve the prior art that the LED television can only display the single standard television signal.
  • the problem is that the LED TV can display the effects of multiple formats and multiple formats of video; and after dividing the second video signal into a preset number of sub-videos, the sub-video is output to the corresponding display unit of the LED display. Displaying can improve the reliability of video transmission and increase the flexibility of video control.
  • the data processing apparatus in this embodiment of the present invention can be implemented by using a method for processing video data by each chip in the above method embodiment. Through the invention, the functions of television signal access, signal enhancement, remote control and the like of the LED self-illuminating television can be realized, and after processing the television signal and various video signals, it is suitable for the display function of the LED high-definition television system.
  • the present invention achieves the following technical effects:
  • the television signal of the high-definition LED television and the access, processing and display of various video signals can be realized;
  • the video stream is combined and synchronized, and the multi-channel video flexible configuration output conforming to the LED display mode, and the time-division multiplexing multi-channel video strict synchronization output processing method improves the image display quality and the reliability of signal transmission.
  • the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices.
  • the invention is not limited to any specific combination of hardware and software.
  • the above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Abstract

本发明公开了一种用于LED电视的数据处理方法、装置及LED电视。其中，该数据处理装置包括：信号处理芯片，用于将接收到的电视信号进行制式转换得到预设制式的第一视频信号；视频处理芯片，与信号处理芯片连接，用于对第一视频信号进行时钟同步处理得到第二视频信号，输出第二视频信号至LED显示器。采用本发明，解决现有技术中LED电视只能显示单一制式的电视信号的问题，实现了LED电视可以显示多种制式、多种格式的视频的效果。

Description

用于 LED电视的数据处理方法、 装置及 LED电视 技术领域 本发明涉及 LED领域， 具体而言， 涉及一种用于 LED电视的数据处理方法、 装 置及 LED电视。 背景技术 目前自主发光的 LED电视是随着 LED显示技术的发展近期才出现的显示设备产 品， 高清晰自主发光的 LED显示屏可以实现超小间距， 高清物理分辨率等功能， 且色 彩表现能力强， 灰阶及对比度优势明显， 完全适合于显示各种视频接口形式的信号与 图像， 但是现有的 LED电视的视频接口形式单一， 并且将接收到的电视信号直接显示 在 LED显示屏上， 显示的画面效果很差， 用户的视觉效果也很差。 具体地， 过去的 LED 显示技术主要是以显示屏的形式出现， 一般是单一视频接口接入形 式 （如 VGA或 DVI等）， 并且直接将接入的电视信号显示在屏幕上， 而不会对接入的信号做任 何的处理， 也即现有的 LED 电视往往只是作为显示屏的功能， 不具备电视的功能， 显示的画 面质量差。 针对现有技术中 LED电视只能显示单一制式的电视信号的问题， 目前尚未提出有 效的解决方案。 发明内容 针对相关技术中 LED电视只能显示单一制式的电视信号的问题， 目前尚未提出有 效的解决方案，为此，本发明的主要目的在于提供一种用于 LED电视的数据处理方法、 装置及 LED电视， 以解决上述问题。 为了实现上述目的， 根据本发明实施例的一个方面， 提供了一种用于 LED电视的 数据处理装置， 该数据处理装置包括： 信号处理芯片， 用于将接收到的电视信号进行 制式转换得到预设制式的第一视频信号； 视频处理芯片， 与信号处理芯片连接， 用于 对第一视频信号进行时钟同步处理得到第二视频信号，输出第二视频信号至 LED显示 器。 进一步地，信号处理芯片通过低压差分接口将第一视频信号传输至视频处理芯片， 其中， 低压差分接口用于按照视频的分辨率的大小将第一视频信号分为第一低压差分 视频流和第二低压差分视频流， 将第一低压差分视频流和第二低压差分视频流传输至 视频处理芯片， 第一低压差分视频流包括两路差分数据流。 进一步地， 视频处理芯片包括： 解码器， 与信号处理芯片连接， 用于对第一低压 差分视频流解码得到两路视频信号，并对第二低压差分视频流解码得到第三视频信号； 时钟处理器， 与解码器连接， 用于将两路视频信号和第三视频信号进行时钟同步处理 得到第二视频信号。 进一步地， 时钟处理器包括： 视频合并器， 与解码器连接， 用于将两路视频信号 合并为第四视频信号； 时钟处理器用于将第三视频信号和第四视频信号进行时钟同步 处理得到第二视频信号。 进一步地， 视频合并器包括： 两个行缓存器， 两个行缓存器与解码器连接， 两路 视频信号的两个数据通道的视频流分别输入至各自对应的行缓存器中； 第一数据读取 器， 与两个行缓存器连接， 用于按照增大一倍的时钟频率对两个行缓存器进行数据读 取操作得到第四视频信号。 进一步地， 视频处理芯片还包括： 视频输出端口， 与信号处理芯片连接， 用于将 第二视频信号分割为预设个数的子视频，并将子视频输出至 LED显示器对应的显示单 元进行显示。 进一步地， 数据处理装置还包括： 控制芯片， 用于将确定的预设坐标发送至视频 输出端口； 视频输出端口用于按照预设坐标确定将子视频输出至对应的显示单元。 进一步地， 视频输出端口包括： 帧存储器， 用于存储第二视频信号， 其中， 帧存 储器包括预设个数的子端口； 第二读取器， 与帧存储器连接， 用于按照预设读取规则 从子端口轮询读取视频数据； 缓存器， 用于缓存读取到的每一路的视频数据， 并将每 一路的视频数据进行时钟域交换得到预设个数的子视频； 输出接口， 与缓存器连接， 用于使用时分复用的方式输出预设个数的子视频。 为了实现上述目的， 根据本发明实施例的一个方面， 提供了一种 LED 电视， 该 LED电视包括数据处理装置。 为了实现上述目的， 根据本发明实施例的一个方面， 提供了一种用于 LED电视的 数据处理方法， 该数据处理方法包括： 将接收到的电视信号进行制式转换得到预设制 式的第一视频信号； 对第一视频信号进行时钟同步处理得到第二视频信号； 将第二视 频信号分割为预设个数的子视频；将子视频输出至 LED显示器对应的显示单元进行显 示。 为了实现上述目的， 根据本发明实施例的一个方面， 提供了一种用于 LED电视的 数据处理装置， 该数据处理装置包括： 转换模块， 用于将接收到的电视信号进行制式 转换得到预设制式的第一视频信号； 时钟处理模块， 用于对第一视频信号进行时钟同 步处理得到第二视频信号； 分割模块，用于将第二视频信号分割为预设个数的子视频; 输出模块， 用于将子视频输出至 LED显示器对应的显示单元进行显示。 采用本发明，通过信号处理芯片将接收到的电视信号转换为预设制式的视频信号， 视频处理芯片处理后输出值 LED显示器， 可以解决现有技术中 LED电视只能显示单 一制式的电视信号的问题， 实现了 LED电视可以显示多种制式、多种格式的视频的效 果。 附图说明 此处所说明的附图用来提供对本发明的进一步理解， 构成本申请的一部分， 本发 明的示意性实施例及其说明用于解释本发明， 并不构成对本发明的不当限定。 在附图 中： 图 1是根据本发明实施例的用于 LED电视的数据处理装置的结构示意图； 图 2是根据本发明实施例的一种可选的用于 LED电视的数据处理装置的结构示意 图； 图 3是根据本发明实施例的获取第四视频信号的时序图； 图 4是根据本发明实施例的确定显示单元的区域示意图； 图 5是根据本发明实施例的读取子视频数据读取方法的时序图； 图 6是根据本发明实施例的用于 LED电视的数据处理方法的流程图； 以及 图 7是根据本发明实施例的用于 LED电视的数据处理装置的示意图。 具体实施方式 首先， 在对本发明实施例进行描述的过程中出现的部分名词或术语适用于如下解 LED: 发光二极管。
LED 自主发光是指 LED器件在被电或其他能量激励以后能够主动发光， 而液晶 本身不发光， 指示透光。 为了使本技术领域的人员更好地理解本发明方案， 下面将结合本发明实施例中的 附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例 仅仅是本发明一部分的实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领 域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例， 都应当属于 本发明保护的范围。 需要说明的是， 本发明的说明书和权利要求书及上述附图中的术语 "第一"、 "第 二"等是用于区别类似的对象， 而不必用于描述特定的顺序或先后次序。 应该理解这 样使用的数据在适当情况下可以互换， 以便这里描述的本发明的实施例能够以除了在 这里图示或描述的那些以外的顺序实施。 此外， 术语 "包括"和 "具有" 以及他们的 任何变形， 意图在于覆盖不排他的包含， 例如， 包含了一系列步骤或单元的过程、 方 法、 系统、 产品或设备不必限于清楚地列出的那些歩骤或单元， 而是可包括没有清楚 地列出的或对于这些过程、 方法、 产品或设备固有的其它步骤或单元。 图 1是根据本发明实施例的用于 LED电视的数据处理装置的结构示意图。图 2是 根据本发明实施例的一种可选的用于 LED电视的数据处理装置的结构示意图。 如图 1和图 2所示， 该装置可以包括： 信号处理芯片 10， 用于将接收到的电视信 号进行制式转换得到预设制式的第一视频信号； 视频处理芯片 20， 与信号处理芯片 10 连接， 用于对第一视频信号进行时钟同步处理得到第二视频信号， 输出第二视频信号 至 LED显示器 40。 其中， 上述实施例中的信号处理芯片 10可以为电视处理芯片， 如 Pixelworks (美 国顶级图像显示芯片厂商）， Mstar (嵌入式 IC芯片）， 视频处理芯片 20采用可编程逻 辑阵列 FPGA。 具体地， 信号处理芯片 10和视频处理芯片 20各可以有 1片存储容量 大于 128Mbit的存储器 （如帧存储器 SDRAM、 DDR), 信号处理芯片通过接入的 TV 电视信号 （含高频头） 进行电视的制式转换、 图像增强及缩放处理， 此外， 信号处理 芯片还可以对接入的其他信号 HDMI (高清晰度多媒体接口， 其为数字化接口）、 USB (通用串行总线） 以及 YPrPb (色差分量端子） 等进行信号的处理。 其中， SDRAM 为同步动态随机存储器， DDR为双倍速率同步动态随机存储器， IC 芯片即为集成电 路。 上述实施例中的用于 LED电视的数据处理装置可以内置于 LED电视。 采用本发明，通过信号处理芯片将接收到的电视信号转换为预设制式的视频信号， 视频处理芯片处理后输出值 LED显示器， 可以解决现有技术中 LED电视只能显示单 一制式的电视信号的问题， 实现了 LED电视可以显示多种制式、多种格式的视频的效 果。 具体地， 上述实施例中经过电视处理芯片进行电视信号的制式转换、 多种接口的 视频解码及解密、 图像缩放、 图像质量增强以及遥控功能。 在上述实施例中， 通过电 视处理芯片 10得到的第一视频信号为固定分辨率的视频流， 这种视频流以 LVDS (低 压差分信号技术接口） 的协议形式输出至视频处理芯片， 视频处理芯片采用可编程逻 辑阵列，通过可编程逻辑芯片对电视处理芯片的输入的视频流进行处理。 在本发明的上述实施例中， 信号处理芯片通过低压差分接口将第一视频信号传输 至视频处理芯片， 其中， 低压差分接口用于按照视频的分辨率的大小将第一视频信号 分为第一低压差分视频流和第二低压差分视频流， 将第一低压差分视频流和第二低压 差分视频流传输至视频处理芯片， 第一低压差分视频流包括两路差分数据流。 具体地， 可以将电视处理芯片处理的第一视频信号的视频流根据视频的分辨率大 小分为 1组或者 2组 LVDS视频输出至可编程逻辑芯片 （即视频处理芯片）， 每组的 LVDS—般包括 1对差分时钟， 和 3或者 4对的差分数据流。 更具体地， 对于高分辨 率的视频信号 （即第一低压差分视频流， 如 1080P的分辨率）， 一般采用 2组 LVDS 输出至视频处理芯片；对于低分辨率的视频信号（即第二低压差分视频流，如 1366*768 及其以下的视频分辨率）， 采用 1组 LVDS输出至视频处理芯片。 根据本发明的上述实施例， 视频处理芯片 20可以包括： 解码器， 与信号处理芯片 连接， 用于对第一低压差分视频流解码得到两路视频信号， 并对第二低压差分视频流 解码得到第三视频信号； 时钟处理器， 与解码器连接， 用于将两路视频信号和第三视 频信号进行时钟同步处理得到第二视频信号。 具体地， 视频处理芯片接收到第一低压差分视频流和第二低压差分视频流后， 首 先对其进行 LVDS的视频流解码， 对其进行解码时需要对解码后的数据进行数据的时 钟同步。 在上述处理过程中， 对于 2组 LVDS传送的高分辨率视频流 （即第一低压差 分视频流），视频处理芯片需要解码后将第一低压差分视频流中的两路视频信号进行合 并。 具体地， 时钟处理器可以包括： 视频合并器， 与解码器连接， 用于将两路视频信 号合并为第四视频信号； 时钟处理器用于将第三视频信号和第四视频信号进行时钟同 步处理得到第二视频信号。 根据本发明的上述实施例， 视频合并器可以包括： 两个行缓存器， 两个行缓存器 与解码器连接， 两路视频信号的两个数据通道的视频流分别输入至各自对应的行缓存 器中； 第一数据读取器， 与两个行缓存器连接， 用于按照增大一倍的时钟频率对两个 行缓存器进行数据读取操作得到第四视频信号。 如图 3所示， 合并两路视频信号 （其中一路视频信号为数据通道 1 的数据 01、 02、 03、 04、 05、 06、 07、 ······， 另一路视频信号为数据通道 2的数据 El、 E2、 E3、 E4、 E5、 E6、 E7、 ……） 的处理方法是将两路数据交错为一路数据， 即通过数据 使能输出数据通道 1的数据 1个， 接着输出数据通道 2的数据 1个， 依次交错循环输 出两个通道的数据。 由于行有效期的时间不变， 因此合并后的像素数据时钟频率增大 一倍。 本发明上述实施例中， 采用两个行缓存器， 两个数据通道的视频流分别输入至 各自的行缓存器中，采用增大一倍的时钟频率时钟对两个行缓存器进行数据读取操作， 即行缓存器 1中读取一个数据， 接着在另外一个缓存器中读取另外一个数据， 依次交 替进行， 得到第四视频信号， 如图 3所示的： 01、 El、 02、 E2、 03、 E3、 04、 E4、 05、 E5、 06、 E6、 07、 E7、 ……。 对于低分辨率视频流 （即第二低压差分视频流） 由于只有 1组 LVDS， 则不需要进行视频数据的合并处理。 在本发明的上述实施例中， 视频处理芯片还可以包括： 视频输出端口， 与信号处 理芯片连接， 用于将第二视频信号分割为预设个数的子视频， 并将子视频输出至 LED 显示器对应的显示单元进行显示。 由于 LED高清电视面板采用的是显示单元拼接为一个整体显示屏，视频处理芯片 传送至 LED显示器的数据流可以采用多路并行数据流的方式，具体地即为设定输出至 LED屏的数据流为 n路， 可以把视频图像的整帧画面分割为 n块子画面 （n块图像可 拼接为一帧完整图像）， 每路视频对应匹配的子画面输出至对应的显示单元进行显示， 那么固定一场时间的情况下， 传送速率大为减小。 其中， n为预设个数， n为自然数。 通过上述实施例， 在一场场周期下， 传送原有图像的 1/n数据量， 传送速率约为 原有的 l/n， 这样提高了视频传输的可靠性。 根据本发明的上述实施例， 数据处理装置还可以包括： 图 2所示的控制芯片 30， 用于将确定的预设坐标发送至视频输出端口； 视频输出端口用于按照预设坐标确定将 子视频输出至对应的显示单元。 其中， 控制芯片可以采用微控制器 MCU实现。 上述实施例中采用电视处理芯片、 视频处理芯片和控制芯片结合设计方式实现 LED高清电视处理系统，不仅能提高视频 传输的可靠性， 还可以提高对视频控制的灵活性。 为了增加每路传输图像的灵活性， 可以采用可灵活配置设定每路具体传输图像区 域的范围。 具体地， 通过控制芯片确定的预设坐标确定传输图像的范围， 以将子视频 输出至对应的显示单元。 例如， 每路传输的图像区域采用设定该图像区域左上角在整 帧图像中的位置 （X， Y) 来确定。 如图 4所示， 示出了 4路子视频输出至 LED显示屏， 四路子视频对应的显示单元 分别为区域 1， 区域 2， 区域 3和区域 4， 其中每个显示单元的区域的确定使用左上角 坐标 （x， y) 确定其在整帧图像中的位置， 如图 4所示的四个坐标 （xl， yl )、 (x2, y2)、 (x3 , y3 ) 以及 （x4， y4) 可以确定区域 1至区域 4的显示位置 （或显示单元）。 可选地， 可以通过设定 X， Y的坐标 （即预设坐标） 来调整各自区域的位置。 在上述 实施例中， 采用了微处理器 （即控制芯片） 获取预设坐标， 如图 2所示， 可采用网络 或者串口的形式对控制芯片进行命令配置以获取预设坐标。 在输出子视频之前， 每路 子视频还可以再次进行 LVDS的编码， 然后输出至 LED屏体显示。 需要进一步说明的是， 视频输出端口可以包括： 帧存储器， 用于存储第二视频信 号， 其中， 帧存储器包括预设个数的子端口； 第二读取器， 与帧存储器连接， 用于按 照预设读取规则从子端口轮询读取视频数据； 缓存器， 用于缓存读取到的每一路的视 频数据， 并将每一路的视频数据进行时钟域交换得到预设个数的子视频； 输出接口， 与缓存器连接， 用于使用时分复用的方式输出预设个数的子视频。 具体地， 对于任意一路子视频的配置实现， 可以先使用帧存储器进行存储， 然后 按照预设读取规则读取视频数据。如图 5所示， 读取时， 每启动四次（每次读数据 256 个数据） 过程为一个周期， 即每周期里面第一次读取的 256个像素数据 （每启动一次 读过程读取的数据个数是 256个） 是端口 0的数据， 第二次启动读取端口 1的 256个 像素数据， 第三次读取端口 2的 256个像素数据， 第四次读取端口 3的 256个像素数 据， 这样 4个端口轮循读取， 然后每一路的视频数据进行缓存器缓存以便进行时钟域 的夂换， 缓冲器写入的时钟频率大致是读取频率的 4倍， 这样读取的数据流将具有连 续性。 通过本发明， 这种多路输出的方式将保证 4路视频的严格同步输出， 从而不会 产生由于 LED刷新频率高而整屏显示运动剧烈图像的不同步撕裂状图像感问题。 本发明还提供了一种 LED显示装置，其可以包括上述实施例中任意一种的数据处 理装置。 采用本发明，通过信号处理芯片将接收到的电视信号转换为预设制式的视频信号， 视频处理芯片处理后输出值 LED显示器， 可以解决现有技术中 LED电视只能显示单 一制式的电视信号的问题， 实现了 LED电视可以显示多种制式、多种格式的视频的效 果。 通过本发明， 实现了 LED电视前端的整体方案， 实行了图像的显示处理， 对标清及高清图像 的输入显示均能保证系统的高可靠性。 图 6是根据本发明实施例的用于 LED电视的数据处理方法的流程图。如图 6所示， 该方法可以通过如下步骤实现： 步骤 S602: 将接收到的电视信号进行制式转换得到预设制式的第一视频信号。 步骤 S604: 对第一视频信号进行时钟同步处理得到第二视频信号。 步骤 S606: 将第二视频信号分割为预设个数的子视频。 步骤 S608: 将子视频输出至 LED显示器对应的显示单元进行显示。 采用本发明，通过信号处理芯片将接收到的电视信号转换为预设制式的视频信号， 视频处理芯片处理后输出值 LED显示器， 可以解决现有技术中 LED电视只能显示单 一制式的电视信号的问题， 实现了 LED电视可以显示多种制式、多种格式的视频的效 果； 并且在将第二视频信号分割为预设个数的子视频之后， 才将子视频输出至 LED显 示器对应的显示单元进行显示， 可以提高视频传输的可靠性， 还可以提高对视频控制 的灵活性。 本发明该实施例中的数据处理方法可以使用上述实施例中的各个芯片对视频数据 的处理方法实现。 需要说明的是， 在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的 计算机系统中执行， 并且， 虽然在流程图中示出了逻辑顺序， 但是在某些情况下， 可 以以不同于此处的顺序执行所示出或描述的步骤。 图 7是根据本发明实施例的用于 LED电视的数据处理装置的示意图。如图 7所示， 该数据处理装置可以包括： 转换模块 50， 用于将接收到的电视信号进行制式转换得到 预设制式的第一视频信号； 时钟处理模块 60， 用于对第一视频信号进行时钟同步处理 得到第二视频信号； 分割模块 70， 用于将第二视频信号分割为预设个数的子视频； 输 出模块 80， 用于将子视频输出至 LED显示器对应的显示单元进行显示。 采用本发明，通过信号处理芯片将接收到的电视信号转换为预设制式的视频信号， 视频处理芯片处理后输出值 LED显示器， 可以解决现有技术中 LED电视只能显示单 一制式的电视信号的问题， 实现了 LED电视可以显示多种制式、多种格式的视频的效 果； 并且在将第二视频信号分割为预设个数的子视频之后， 才将子视频输出至 LED显 示器对应的显示单元进行显示， 可以提高视频传输的可靠性， 还可以提高对视频控制 的灵活性。 本发明该实施例中的数据处理装置可以使用上述方法实施例中的各个芯片对视频 数据的处理方法实现。 通过本发明， 可以实现 LED自主发光电视的电视信号接入， 信号增强， 遥控等功 能， 通过处理电视信号及各种视频信号后， 使其适合 LED高清电视系统的显示功能。 从以上的描述中， 可以看出， 本发明实现了如下技术效果： 通过本发明， 可以实现高清晰 LED电视的电视信号以及各种视频信号的接入、处 理以及显示； 同时在视频处理芯片的视频流的合并同步处理， 以及符合 LED显示方式 的多路视频灵活配置输出， 采用时分复用的多路视频严格同步输出的处理方法， 提高 了图像显示的质量， 以及信号传输的可靠性。 显然， 本领域的技术人员应该明白， 上述的本发明的各模块或各步骤可以用通用 的计算装置来实现， 它们可以集中在单个的计算装置上， 或者分布在多个计算装置所 组成的网络上， 可选地， 它们可以用计算装置可执行的程序代码来实现， 从而， 可以 将它们存储在存储装置中由计算装置来执行， 或者将它们分别制作成各个集成电路模 块， 或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。 这样， 本发明 不限制于任何特定的硬件和软件结合。 以上所述仅为本发明的优选实施例而已， 并不用于限制本发明， 对于本领域的技 术人员来说， 本发明可以有各种更改和变化。 凡在本发明的精神和原则之内， 所作的 任何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

权 利 要 求 书
1. 一种用于 LED电视的数据处理装置， 其特征在于， 包括： 信号处理芯片， 用于将接收到的电视信号进行制式转换得到预设制式的第 一视频信号；
视频处理芯片， 与所述信号处理芯片连接， 用于对所述第一视频信号进行 时钟同步处理得到第二视频信号， 输出所述第二视频信号至 LED显示器。
2. 根据权利要求 1所述的数据处理装置， 其特征在于， 所述信号处理芯片通过低压差分接口将所述第一视频信号传输至所述视频 处理芯片， 其中， 所述低压差分接口用于按照视频的分辨率的大小将所述第一视频信 号分为第一低压差分视频流和第二低压差分视频流， 将所述第一低压差分视频 流和所述第二低压差分视频流传输至所述视频处理芯片， 所述第一低压差分视 频流包括两路差分数据流。
3. 根据权利要求 2所述的数据处理装置， 其特征在于， 所述视频处理芯片包括： 解码器， 与所述信号处理芯片连接， 用于对所述第一低压差分视频流解码 得到两路视频信号， 并对所述第二低压差分视频流解码得到第三视频信号； 时钟处理器， 与所述解码器连接， 用于将所述两路视频信号和所述第三视 频信号进行时钟同步处理得到所述第二视频信号。
4. 根据权利要求 3所述的数据处理装置， 其特征在于， 所述时钟处理器包括： 视频合并器， 与所述解码器连接， 用于将所述两路视频信号合并为第四视 频信号；
所述时钟处理器用于将所述第三视频信号和所述第四视频信号进行时钟同 步处理得到所述第二视频信号。
5. 根据权利要求 4所述的数据处理装置， 其特征在于， 所述视频合并器包括： 两个行缓存器， 两个所述行缓存器与所述解码器连接， 所述两路视频信号 的两个数据通道的视频流分别输入至各自对应的所述行缓存器中； 第一数据读取器， 与两个所述行缓存器连接， 用于按照增大一倍的时钟频 率对两个所述行缓存器进行数据读取操作得到所述第四视频信号。
6. 根据权利要求 1所述的数据处理装置，其特征在于，所述视频处理芯片还包括:
视频输出端口， 与所述信号处理芯片连接， 用于将所述第二视频信号分割 为预设个数的子视频，并将所述子视频输出至所述 LED显示器对应的显示单元 进行显示。
7. 根据权利要求 6所述的数据处理装置，其特征在于，所述数据处理装置还包括: 控制芯片， 用于将确定的预设坐标发送至所述视频输出端口； 所述视频输出端口用于按照所述预设坐标确定将所述子视频输出至对应的 所述显示单元。
8. 根据权利要求 6所述的数据处理装置， 其特征在于， 所述视频输出端口包括： 帧存储器， 用于存储所述第二视频信号， 其中， 所述帧存储器包括所述预 设个数的子端口；
第二读取器， 与所述帧存储器连接， 用于按照预设读取规则从所述子端口 轮询读取视频数据； 缓存器， 用于缓存读取到的每一路的所述视频数据， 并将所述每一路的所 述视频数据进行时钟域交换得到所述预设个数的子视频；
输出接口， 与所述缓存器连接， 用于使用时分复用的方式输出所述预设个 数的子视频。
9. 一种 LED电视，其特征在于，包括权利要求 1至 8中任意一项所述的数据处理 装置。
10. 一种用于 LED电视的数据处理方法， 其特征在于， 包括： 将接收到的电视信号进行制式转换得到预设制式的第一视频信号； 对所述第一视频信号进行时钟同步处理得到第二视频信号；
将所述第二视频信号分割为预设个数的子视频；
将所述子视频输出至 LED显示器对应的显示单元进行显示。
11. 一种用于 LED电视的数据处理装置， 其特征在于， 包括： 转换模块， 用于将接收到的电视信号进行制式转换得到预设制式的第一视 频信号；
时钟处理模块， 用于对所述第一视频信号进行时钟同步处理得到第二视频 信号；
分割模块， 用于将所述第二视频信号分割为预设个数的子视频； 输出模块， 用于将所述子视频输出至 LED 显示器对应的显示单元进行显 示。
PCT/CN2014/083167 2014-04-23 2014-07-28 用于led电视的数据处理方法、装置及led电视 WO2015161574A1 (zh)

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CA2936373A CA2936373C (en) 2014-04-23 2014-07-28 Data processing method and device for led television, and led television
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