WO2017049858A1 - 视频信号转换方法、视频信号转换装置以及显示系统 - Google Patents

视频信号转换方法、视频信号转换装置以及显示系统 Download PDF

Info

Publication number
WO2017049858A1
WO2017049858A1 PCT/CN2016/074030 CN2016074030W WO2017049858A1 WO 2017049858 A1 WO2017049858 A1 WO 2017049858A1 CN 2016074030 W CN2016074030 W CN 2016074030W WO 2017049858 A1 WO2017049858 A1 WO 2017049858A1
Authority
WO
WIPO (PCT)
Prior art keywords
image
video signal
sub
frame
conversion
Prior art date
Application number
PCT/CN2016/074030
Other languages
English (en)
French (fr)
Inventor
段然
耿立华
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/541,923 priority Critical patent/US20180013978A1/en
Publication of WO2017049858A1 publication Critical patent/WO2017049858A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0125—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level one of the standards being a high definition standard
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/026—Control of mixing and/or overlay of colours in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
    • H04N21/4312—Generation of visual interfaces for content selection or interaction; Content or additional data rendering involving specific graphical features, e.g. screen layout, special fonts or colors, blinking icons, highlights or animations
    • H04N21/4316—Generation of visual interfaces for content selection or interaction; Content or additional data rendering involving specific graphical features, e.g. screen layout, special fonts or colors, blinking icons, highlights or animations for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/47—End-user applications
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/67—Circuits for processing colour signals for matrixing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/14—Solving problems related to the presentation of information to be displayed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G09G2370/042—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller for monitor identification
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/12—Use of DVI or HDMI protocol in interfaces along the display data pipeline

Definitions

  • the present disclosure relates to the field of video display, and in particular to a video signal conversion method, a corresponding video signal conversion device, and a display system including the video signal conversion device.
  • the frequency of the source signal may not be required. Too high, such as 15Hz may meet the requirements, and because the current ultra-high-definition display generally uses a higher scanning frequency (for example, 60Hz), in order to match the ultra-high-definition display, the source signal needs to be converted so that Displayed on the Ultra HD display.
  • the present disclosure proposes a video signal conversion method, a corresponding video signal conversion device, and a display system including the video signal conversion device, so that a low resolution, for example, a (5124*2160, 5K2K) video signal can be used.
  • the conversion is stitched into a high resolution (for example, a 10K*4K video signal), so that a player playing a low resolution video signal (for example, 5K2K@60Hz) can be matched with an ultra high definition (eg, 10K4K@60Hz) display.
  • the display system displays high-resolution images stitched by low-resolution images on the ultra-high definition display.
  • a video signal conversion method comprising: receiving a plurality of sub-frames divided by a low-resolution image of a video signal in parallel; performing image processing on each of the received sub-frames; and The plurality of sub-frames after image processing are combined into one high-resolution image for display on the display device.
  • image processing is performed in parallel on a plurality of sub-frames divided by one frame of low-resolution image on a plurality of processing channels.
  • image processing includes: color space conversion, color enhancement processing, frame rate conversion, and image processing At least one of the prime format conversions.
  • the number of the plurality of subframes into which the low resolution image is to be divided is determined based on at least one of an image resolution of the low resolution image and a transmission rate of the data port receiving the low resolution rate image.
  • color space conversion includes converting the color space of the sub-frame from RGB to YUV.
  • the multiple of the frame rate conversion is determined based on the ratio of the image resolution of the high resolution image and the low resolution image.
  • the frame rate converted plurality of sub-frames are converted into LVDS signals by pixel format conversion, and the LVDS signals are converted into V-BY-ONE signals by signal format conversion and output to the display device.
  • a video signal conversion apparatus comprising: a video signal receiving port that receives a plurality of sub-frames divided by a low-resolution image in parallel; an image processor, each of the received sub-frames The frame performs image processing; and the video signal output port outputs the image-processed plurality of sub-frames to the display device for synthesis into a frame of high-resolution image for display.
  • the image processor performs image processing on the plurality of sub-frames divided by the one-frame low-resolution image in parallel on the plurality of channels.
  • the image processor includes: a color space conversion component that performs color space conversion on the received sub-frame; a color enhancement processing component that performs color enhancement processing on the sub-frame subjected to color space conversion; and a frame rate conversion component
  • the color enhancement processed sub-frame performs frame rate conversion; and the pixel format conversion unit performs pixel format conversion on the frame rate converted sub-frame for output to the video signal output port.
  • the video signal conversion apparatus of the present disclosure further includes a signal format conversion section, wherein the frame rate converted plurality of subframes are converted into LVDS signals by the pixel format conversion section, and the LVDS signals are converted into the LVDS signals by the signal format conversion section
  • the V-BY-ONE signal is output to the display device.
  • the video signal receiving port is a DVI port
  • the video signal output port is a V-BY-ONE port
  • the low resolution image is a 5124*2160 image and the high resolution image is a 10248x4320 image.
  • the image processor is implemented by one or more FPGAs.
  • a display system includes a playback device, a high definition display, and a video signal conversion device as described above.
  • Video signal conversion method, video signal conversion device, and corresponding display system which can re-splice relatively low-resolution video images on the ultra-high-definition display to form high-resolution video images for display, which enables playback of high-definition video images with high-definition video images.
  • the ultra-high-definition display of the video image is matched to display high-resolution images, which enhances the compatibility between the two, reduces the cost of the display system, and facilitates the popularization of the high-definition display system.
  • FIG. 1 is a flowchart of a video signal conversion method according to an embodiment of the present disclosure
  • 2A is a schematic diagram of dividing a frame of a low resolution (eg, 5K2K) image into a plurality of subframes, in accordance with an embodiment of the present disclosure
  • 2B is a schematic diagram of transmitting one subframe using multiple DVI ports, in accordance with an embodiment of the present disclosure
  • 3A-3B are schematic diagrams of transmitting multiple subframes using multiple DVI ports, in accordance with one embodiment of the present disclosure
  • 3C is a schematic diagram of stitching multiple subframes into one frame high resolution image, in accordance with an embodiment of the present disclosure
  • FIG. 4A is a flowchart of a method of image processing a video signal, in accordance with one embodiment of the present disclosure
  • FIG. 4B shows an exemplary corresponding processing flow
  • FIG. 5 is a schematic diagram of stitching received image processed multiple sub-frames into a frame high resolution (eg, 10K4K) image using a timing controller (T-CON) on a display screen, in accordance with one embodiment of the present disclosure
  • FIG. 6 is a schematic block diagram of a video signal conversion apparatus according to an embodiment of the present disclosure.
  • FIGS 7A-7B are schematic block diagrams of display systems in accordance with an embodiment of the present disclosure.
  • a video signal conversion method is proposed This makes it possible to synthesize a multi-frame low-resolution image of a video signal into a high-resolution image, so that a playback device that plays a low-resolution video image and a high-resolution display can be combined into a display system to display a high-resolution image.
  • a 5K2K low-resolution image output by a playback device that plays a low-resolution video image may be processed and then spliced into a high-resolution image of 10K4K for display.
  • the above-mentioned low resolution 5K2K and high resolution 10K4K are merely examples introduced for convenience of explaining the principle of the embodiment of the present invention.
  • the video signal conversion method of the present disclosure is not limited to the above resolution, but It can be applied to other various resolutions while maintaining the principles of the present invention.
  • a multi-frame low-resolution video image can be synthesized into a high-resolution image of one frame of 10K4K.
  • a video signal conversion method includes: S10, receiving a plurality of subframes divided by a low-resolution image; S20, performing image processing on each subframe; and S30, placing the image The processed plurality of sub-frames are combined into one frame of high-resolution image.
  • a frame of low resolution (eg, 5K2K) image is segmented into 4 subframes.
  • the number of subframes to be divided by one frame of image may be determined based at least on a transmission rate of a port for playing back display data and a resolution of an image to be transmitted by a playback device that plays the low-resolution video signal.
  • DVI Digital Visual Interface
  • the highest resolution supported by single channel DVI is generally 1920*1200
  • the highest resolution supported by dual channel DIV is generally 2560*1600.
  • the type of DVI port used can determine the number of DVI ports used and the number of sub-frames into which the image is to be segmented. For example, according to an embodiment of the present disclosure, in order to transmit an image with a frame resolution of 5K2K, eight DVI ports may be used to transmit four subframes divided by the frame image in parallel.
  • a playback device supporting 5K2K@60Hz is taken as an example.
  • the following manner may be adopted: modified by the video signal conversion device of the present disclosure.
  • Extensd Display Identification Data (EDID) information is displayed with the extension on the playback device, and is written to the display output of the playback device.
  • EDID Extensd Display Identification Data
  • the system such that the video image output by the playback device is divided into a plurality of sub-frames for output.
  • the transmission port DVI-A/B, the transmission port DVI-C/D, the transmission port DVI-E/F, and the transmission port DVI-G/H are respectively transmitted in parallel by a frame of 5K2K image. Split into four sub-frames.
  • the image to be transmitted may be divided and transmitted in different manners; for example, If the transmission rate of the data transmission port used is low, in order to transmit video images of the same resolution, it is necessary to increase the number of data transmission ports to ensure that excessive signal display delay is not introduced.
  • the above DVI port is only one example of the video data transmission port of the present disclosure, and the data transmission port for transmitting the video image output by the playback device to the video signal conversion device is not limited to the DVI port, but various other various types may be employed.
  • the data transmission port is not limited here.
  • a video signal conversion device is connected between the playback device and the display screen to convert the low resolution image so that the high resolution image can be displayed on the high definition display.
  • the video signal output by the playback device is transmitted to the video signal conversion device through a data transmission port (for example, a DVI port)
  • a data transmission port for example, a DVI port
  • 8 DVI ports transmit one frame of 5K2K images at a time
  • the high resolution of the 10K4K is spliced.
  • 8 DVI ports are required to sequentially transmit four frames of 5K2K video images in chronological order, and each of the 5K2K images is transmitted in parallel in four sub-frames.
  • 16 2562x1080 subframes may be required.
  • the number of subframes can be increased or decreased.
  • 3A-3B show schematic diagrams of transmitting 5K2K images in four DVI ports.
  • four frames of 5K2K video images are sequentially transmitted on the time axis, wherein the first frame video image is divided into four subframes, which are respectively labeled as subframe 1, subframe 5, subframe 9, and subframe 13,
  • the second frame video image is divided into four subframes, which are respectively labeled as subframe 2, subframe 6, subframe 10, and subframe 14
  • the third frame video image is divided into four subframes, which are respectively labeled as subframe 3 , subframe 7, subframe 11 and subframe 15
  • the fourth frame video image is divided into four subframes, which are labeled as subframe 4, subframe 8, subframe 12, and subframe 16, respectively.
  • DVI-A/B sequentially transmits subframes 1, 2, 3, and 4
  • DVI-C/D sequentially transmits subframes 5, 6, 7, and 8
  • DVI-E/F sequentially transmits the sub-frames.
  • DVI-G/H sequentially transmits subframes 13, 14, 15, and 16.
  • the playback device may add a start frame when transmitting the subframe.
  • the video conversion device receives the start frame, it can start counting to distinguish four sub-frames divided by one frame of video image to be transmitted. For example, as shown in FIG.
  • counting can be started, thereby distinguishing the subframe 1, the subframe 2, the subframe 3, and the subframe 4; similarly, for the transmission port DVI-C/D, after receiving the start subframe, the counting may be started, thereby distinguishing the subframe 5, the subframe 6, the subframe 7 and the subframe 8; the others and so on, and no further description is provided herein. .
  • the video signal conversion apparatus receives a plurality of subframes divided by a frame of low-resolution image
  • image processing of each subframe is required to finally splicing one on the high-definition display.
  • Frame high resolution image The following takes the DVI-A/B port as an example to illustrate the specific process of image processing for each sub-frame.
  • FIG. 4A first, after receiving a subframe (for example, subframe 1) through the transmission port DVI-A/B, as shown in step S400, color space conversion is performed on the subframe 1 for further processing thereafter. .
  • sub-frame 1 may be converted from RGB color space to YUV color space, and red (R), green (G), and blue (B) component values of each pixel in sub-frame 1 are converted to YUV values.
  • RGB red
  • G green
  • B blue
  • Y represents the luminance component of the pixel
  • U and V represent the color difference component of the pixel, respectively, thereby separating the luminance information of the pixel from the chrominance information, thereby facilitating more efficient representation of the color image.
  • the purpose of color space conversion is also to reduce the amount of data processing and improve data processing efficiency.
  • RGB to YUV color space conversion from RGB to YUV for a sub-frame
  • RGB to HSV color any other forms of color space conversion, such as RGB to HSV color, as needed.
  • Spatial conversion is not limited to RGB to YUV color space conversion.
  • step S410 the sub-frame is subjected to color enhancement processing, thereby improving the visual effect of the sub-frame image and highlighting the characteristics of the image.
  • color enhancement processing thereby improving the visual effect of the sub-frame image and highlighting the characteristics of the image.
  • various color enhancement algorithms can be employed for color enhancement to enhance the visual effect of sub-frame colors, details of which are not described herein.
  • step S420 frame rate conversion is performed on the sub-frame.
  • the purpose of frame rate conversion is to multiply the sub-frames in order to keep the refresh rate of the entire image unchanged after splicing the low-resolution sub-frames into high-resolution images.
  • step S430 the pixel format conversion can be performed after the frame rate conversion.
  • the image signals required to form a high-resolution image are transmitted to the timing controller (T-CON) of the high-definition display, and finally spliced into high-resolution video images on the high-definition display.
  • FIG. 4B shows a signal flow of image processing of a 2562 ⁇ 1080 sub-frame input with the transmission port DVI-A/B as an example.
  • the 2562x1080@60Hz subframe received by the transmission port DVI-A/B is decoded, it is subjected to color space conversion.
  • it is converted from the RGB space to the YUV space; then, the color space converted sub-frame is subjected to color enhancement processing on the YUV space.
  • two 1281x1080@60Hz video signals are simultaneously processed in parallel, each of which can be regarded as four 1281x1080@15Hz video signals in the time dimension.
  • frame rate conversion is performed for each sub-frame.
  • this can be implemented by performing frame rate conversion (Frame Rate Conversion) and double rate dynamic random access memory (DDRSDRAM, DDR for short) chips to complete a simple 4x frame copy.
  • a 15 Hz video signal can be written to the DDR chip, and the video signal can be read out from the DDR chip at 60 Hz, thereby achieving frame rate conversion.
  • the above takes a two-port DVI-A/B receiving a sub-frame of 2562 ⁇ 1080 as an example, and the specific steps of performing color space conversion, color enhancement processing, and frame rate conversion are illustrated with reference to FIG. 4B.
  • pixel format conversion is required for the plurality of sub-frames.
  • four subframes after frame rate conversion are performed, for example, four children of 2562 ⁇ 1080@60 Hz.
  • Frame 1, subframe 2, subframe 3, and subframe 4 are spliced into a sub-image of 2562x4320@60Hz in the column direction.
  • the sub-image may be divided into 6 ways for parallel processing, wherein each path is 424x4320@60Hz.
  • the 6-channel signals are processed in parallel by the pixel format conversion unit.
  • the other four sub-ports DVI-C/D, DVI-E/F, and DVI-G/H receive four consecutive sub-frames respectively after color space conversion, color enhancement processing, and frame rate conversion, and are also spliced into 2562x4320@60Hz.
  • the sub-image is divided into 6 signals 424x4320@60Hz and sent to the pixel format conversion unit for processing.
  • the pixel format conversion unit converts it into a Low Voltage Differential Signal (LVDS) signal output.
  • LVDS Low Voltage Differential Signal
  • the LVDS signal can be converted to V-BY by the conversion chip.
  • the ONE signal is transmitted to the timing controller of the HD display through the V-BY-ONE port of the video signal conversion device.
  • the LVDS signal output by the pixel format conversion unit can be converted into a V-BY-ONE signal by the signal conversion chip, and the sub-image having a resolution of 5K2K@60 Hz is output to the V-BY-ONE port of the 16 channel, for example.
  • the timing controller (T-CON) of the high-definition display converts the received V-BY-ONE digital signal into an RGB data drive signal and a scan drive signal, thereby driving the HD display to display an image.
  • T-CON converts the received V-BY-ONE digital signal into an RGB data drive signal and a scan drive signal, thereby driving the HD display to display an image.
  • an image with a resolution of 10K4K@60Hz is finally displayed on the display, as shown in FIG. 5, four 16-channel V-BY-ONE ports are required to transmit four frames of sub-images in parallel, thereby enabling display in high definition.
  • the four-frame sub-image is spliced into a complete 10K4K@60Hz high-definition image on the screen.
  • the subframe input by the DVI port may be appropriately added by several columns or several rows, for example, not limited to 2562 rows or 1080 columns in 2562 ⁇ 1080, but may be slightly more than 2562. Line or 1080 column.
  • FIG. 6 shows a block diagram of a structure of a video signal conversion apparatus according to an embodiment of the present disclosure.
  • the video signal conversion apparatus includes: at least one video signal receiving port 610, which receives a video signal from a video playing device; and an image processing chip 620 that performs image processing on each frame image in the received video signal; And at least one video signal output port 630 for outputting each frame image subjected to image processing to the display device.
  • the image processing chip includes: a color space conversion component 6210 that performs color space conversion on each frame image received by the video signal receiving port 610; a color enhancement component 6220 that performs color enhancement on each frame image; and a frame rate conversion component 6230 Performing frame rate conversion on each frame image subjected to color enhancement; and pixel format conversion unit 6240, performing pixel conversion on each frame image after frame rate conversion The format is converted and output to the video signal output port 630.
  • the image processing chip further includes an image decoding unit 6250 that performs image decoding on each received frame image before the color space conversion unit 6210 performs color space conversion on each frame image.
  • the video signal receiving port adopts a DVI port
  • the video signal output port uses a V-BY-ONE port.
  • an image processing chip is implemented by an FPGA (Field-Programmable Gate Array).
  • image processing may be performed on each frame by other hardware, including but not limited to DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), and CPLD (Complex Programmable Logic Device).
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • CPLD Complex Programmable Logic Device
  • Programmable logic device dedicated or general purpose image processor to achieve the same function, is not limited here.
  • the video signal conversion apparatus (or image processing chip 620) further includes an LVDS conversion section that converts the LVDS signal into a V-BY-ONE signal output.
  • the video signal is output to port 630.
  • the video signal conversion device of the embodiment of the present disclosure will be specifically described by taking a low-resolution video signal of 5K2K@60Hz outputted by the video playback device into a high-resolution video signal of 10K2K@60Hz as an example.
  • the number, type, and order of the various components for processing the video signal appearing in the following detailed description are not limiting of the principles of the present disclosure, but merely to facilitate understanding of the principles of the present disclosure. Introduced example.
  • those skilled in the art can increase or decrease the number of related components, replace certain types of components with other types of components, change the order between related processes, or make them parallel.
  • the implementation proceeds without departing from the principles of the present disclosure.
  • one or more of the elements of the present disclosure may be integrated together, or a single element may be separated into several elements to achieve the same function. These variations are also intended to fall within the scope of the present disclosure.
  • FIG. 7A-7B illustrate schematic structures of a display system in accordance with an embodiment of the present disclosure.
  • the video signal conversion device is connected between a player and a high definition display panel, wherein the video signal conversion device employs a DVI port as a video signal receiving port.
  • a DVI port as a video signal receiving port.
  • a video playback device including but not limited to a personal computer, a television, a DVR, a set top box, etc.
  • the video signal conversion device receives the video playback device output Low resolution video signal.
  • eight DVI ports are used to receive one frame of image output by the video playback device, wherein two DVI ports are grouped together, and the reception is performed by low resolution.
  • the image is divided into 2562x1080@60Hz subframes.
  • the sub-region output is performed to divide the one-video image into multiple sub-frames, and the video signal conversion device connected to the playback device may be modified.
  • the extended display identification data (EDID) information on the FPGA board is written to the display output system of the playback device, so that the video image output by the playback device is divided into a plurality of sub-frames and output.
  • the 5K2K@60Hz low resolution image output by the playback device is divided into four subframes, and each subframe is transmitted by two DVI ports.
  • the video signal receiving port of the video signal conversion device for receiving the video image output by the playback device is not limited to the DVI port, but various other ports may be used.
  • the HMDI port may be adopted, which is not limited herein.
  • the number of subframes into which the video image output by the playback device is divided may be determined according to the data transmission rate of the HMDI port.
  • a pair of DVI ports are used to receive a 5K2K@60Hz video signal output from a video playback device, wherein a pair of DVI ports correspond to two DVI channels, and receive a sub-frame of 2562 ⁇ 1080@60 Hz.
  • parallel four channels are used to simultaneously simultaneously divide four sub-frames divided by a 5K2K@60Hz video signal. Perform image processing. The following takes the DVI-A/B port as an example.
  • the received subframe is input to the image processing chip 620, and is decoded by the image decoding unit 6250 (of course, depending on the actual application, decoding may not be necessary.
  • the color space converting section 6210 performs color space conversion on the decoded subframe.
  • the sub-frame can be converted from the RGB color space to the YUV color space, and the red (R), green (G), and blue (B) component values of each pixel in the sub-frame are converted into YUV values, wherein Y represents the luminance component of the pixel, and U and V represent the color difference component of the pixel, respectively, thereby separating the luminance information of the pixel from the chrominance information, thereby facilitating more efficient representation of the color image.
  • RGB to HSV color space conversion not limited to RGB to YUV color Space conversion.
  • the color enhancement unit 622 After the color space conversion unit 6210 performs color space conversion on the sub-frame, the color enhancement unit 622 performs color enhancement processing on the sub-frame, thereby improving the visual effect of the sub-frame image and highlighting the characteristics of the image.
  • various color enhancement algorithms can be employed for color enhancement to enhance the visual effect of sub-frame colors, details of which are not described herein.
  • the frame rate conversion section 6230 performs frame rate conversion on the sub-frame.
  • the purpose of frame rate conversion is to multiply the sub-frames in order to keep the refresh rate of the image unchanged after splicing the low-resolution sub-frames into high-resolution images.
  • two 1281x1080@60Hz video signals can be simultaneously processed in parallel, wherein each channel can be divided into time dimensions. 4 channels of 1281x1080@15Hz video signals are processed.
  • the video signal of 1281 ⁇ 1080@15 Hz is multiplied by the frame rate conversion unit 6230.
  • the frame rate conversion unit 6230 can perform cross processing with the DDR chip to complete a simple 4 ⁇ frame copy.
  • a 15 Hz video signal can be written to the DDR chip, and the video signal can be read out from the DDR chip at 60 Hz, thereby achieving frame rate conversion.
  • a sub-frame composed of two DVI signals as an example, the specific process including color space conversion, color enhancement processing and frame rate conversion is illustrated.
  • a pair of DVI ports DVI-A and DVI-B sequentially receive four sub-frames 1, 2, 3 and 4 of 2562 ⁇ 1080@60 Hz, in order to finally display the panel in HD.
  • the video image of 10248x4320 is displayed, and 16 subframes received by four pairs of DVI ports need to be spliced.
  • the splicing can be performed according to the arrangement of FIG. 3C, wherein the subframes 1, 2, 3, and 4 are sequentially derived from DVI-A.
  • subframes 5, 6, 7, and 8 are sequentially derived from DVI-C/D
  • subframes 9, 10, 11, and 12 are sequentially derived from DVI-E/F
  • subframes 13, 14, 15, and 16 are sequentially derived from On DVI-G/H. If this 2562x1080@60Hz sub-frame is directly spliced into a high-resolution image of 10248x4320, the refresh rate of the video image on the high-definition display panel will be reduced. Therefore, before splicing, each sub-frame is separately copied by 4 times using a frame rate conversion component to match the performance of the display panel 10248x4320@60Hz.
  • each sub-frame finally spliced into a 10K4K@60 Hz high-resolution image can be transmitted from the video signal conversion device to the high-definition display panel.
  • Four sub-frames after frame rate conversion for example, 2562x1080@60Hz subframe 1, subframe 2, subframe 3, and subframe 4 are spliced into a sub-image of 2562x4320@60Hz in the column direction.
  • the sub-image can be divided into 6 ways for parallel processing as shown in FIG. 4B, wherein each path represents 424x4320@60Hz.
  • the six signals are sent to the pixel format conversion unit 6240 for parallel processing, and converted into a low voltage differential signal (LVDS) signal output.
  • LVDS low voltage differential signal
  • the above is only processing the sub-frames received by the pair of DVI ports, and the sub-frames received by the other three pairs of DVI ports are also output to the pixel format conversion unit 6240 after being processed separately; thus, the four pairs of DVI ports are received.
  • the 16 sub-frames are converted into LVDS image signals by the pixel format conversion section after being processed by the color space conversion section, the color enhancement section, and the frame rate conversion section.
  • the LVDS signal can be converted to V-BY by the conversion chip.
  • the ONE signal is transmitted to the timing controller of the high-definition display panel through the V-BY-ONE port of the video signal conversion device.
  • the LVDS signal output by the pixel format conversion unit can be converted into a V-BY-ONE signal by the signal conversion chip, and the sub-picture of 5K2K@60Hz is output to the high definition display panel, for example, through the 16-channel V-BY-ONE port.
  • the timing controller (T-CON), the T-CON converts the received V-BY-ONE digital signal into an RGB data drive signal and a scan drive signal, thereby driving the HD display panel to display an image.
  • the timing controller (T-CON)
  • the T-CON converts the received V-BY-ONE digital signal into an RGB data drive signal and a scan drive signal, thereby driving the HD display panel to display an image.
  • an image with a resolution of 10K4K@60Hz is finally displayed on the display, as shown in FIG. 5, four 16-channel V-BY-ONE ports are required to transmit four frames of sub-images in parallel, thereby enabling display in high definition.
  • the four-frame sub-image is spliced into a complete 10K4K@60Hz high-definition image on the panel.
  • the subframe input by the DVI port may be appropriately added by several columns or several rows, for example, not limited to 2562 rows or 1080 columns in 2562 ⁇ 1080, but may be slightly more than 2562. Line or 1080 column.
  • the image processing chip in the video signal conversion device in the present disclosure can be realized by an FPGA.
  • image processing of a subframe received by all video signal receiving ports may be implemented by using one FPGA, wherein a separate image processing channel is set for each pair of DVI ports, thereby implementing each sub- Frame color space conversion, color enhancement, and frame rate conversion, and finally pixel format conversion for all sub-frames, and output of the pixel format conversion component
  • the LVDS signal is converted to a V-BY-ONE signal and output to the display panel through the video signal output port.
  • a separate piece of FPGA may be set for each pair of DVI ports, and image processing of each sub-frame received by the pair of DVI ports may be completed, that is, each piece of FPGA is separately paired with a pair of DVI ports.
  • the received sub-frame performs color space conversion, color enhancement, frame rate conversion, pixel format conversion, and converts the LVDS signal output by the pixel format conversion unit into a V-BY-ONE signal and outputs it to the display panel through the video signal output port.
  • the sub-frames received for each pair of DVI ports use their respective FPGAs for video signal conversion.
  • the high definition display panel includes four timing controllers (T-CON), each of which is used for a video signal transmitted by one 16-channel V-BY-ONE port, that is, 5K2K@ The 60Hz signal, however, is just an example.
  • a timing controller can be used to process the video signals transmitted by the four 16-channel V-BY-ONE ports, thereby driving the HD display panel to display 10K4K@60Hz video images. Therefore, in the present disclosure, the number of timing controllers in the high definition display panel is not limited.
  • relatively low resolution video images can be re-spliced on an ultra high definition display to form a high resolution video image for display, which makes A playback device that plays low-resolution video images can be used to match an ultra-high definition display that displays high-resolution video images, thereby displaying high-resolution images, enhancing compatibility between the two, reducing the cost of the display system, and facilitating The popularity of high-definition display systems.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Business, Economics & Management (AREA)
  • Marketing (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Television Systems (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

一种视频信号转换方法、相应的视频信号转换装置以及包括该视频信号转换装置的显示系统，使得可以将低分辨率的视频信号转换拼接为高分辨率的视频信号，从而在超高清显示屏上显示由低分辨率图像拼接的高分辨率图像。该视频信号转换方法，包括：并行地接收由视频信号的低分辨率图像分割而成的多个子帧(S10)；对接收到的每个子帧进行图像处理(S20)；以及将图像处理后的多个子帧合成为一帧高分辨率图像而在显示设备上进行显示(S30)。

Description

视频信号转换方法、视频信号转换装置以及显示系统 技术领域
本公开涉及视频显示领域，具体涉及一种视频信号转换方法，相应的视频信号转换装置，以及包括该视频信号转换装置的显示系统。
背景技术
随着显示技术的飞速发展，显示面板的分辨率越来越高，使得超高清显示屏逐渐应用到各种领域。为了与这种超高清显示屏进行匹配，需要能够播放超高清视频信号的播放设备。然而，目前这种能够播放超高清视频信号的播放设备的成本高昂，导致了超高清显示系统难以普及。
另一方面，在某些应用场景中，例如，广告牌、公共信息显示牌、会议公告牌等需要以高分辨率(例如10248x4320,10K4K)显示电子标识的场景，片源信号的频率可能不需要太高，例如15Hz可能就满足要求，而由于目前超高清显示屏一般应用的扫描频率比较高(例如，60Hz)，为了与超高清显示屏进行匹配，需要对片源信号进行转换，以便能够在超高清显示屏上进行显示。
发明内容
针对以上问题，本公开提出了一种视频信号转换方法、相应的视频信号转换装置以及包括该视频信号转换装置的显示系统，使得可以将低分辨率，例如(5124*2160，5K2K)的视频信号转换拼接为高分辨率(例如，10K*4K的视频信号)，从而使得播放低分辨率视频信号(例如5K2K@60Hz)的播放器能够与超高清(例如10K4K@60Hz)显示屏进行匹配而组成显示系统，而在超高清显示屏上显示由低分辨率图像拼接的高分辨率图像。
根据本公开的一方面，提出了一种视频信号转换方法，包括：并行地接收由视频信号的低分辨率图像分割而成的多个子帧；对接收到的每个子帧进行图像处理；以及将图像处理后的多个子帧合成为一帧高分辨率图像从而在显示设备上进行显示。
可选地，在多个处理通道上对由一帧低分辨率图像分割而成的多个子帧并行地进行图像处理。
可选地，图像处理包括：色彩空间转换、色彩增强处理、帧率转换和像 素格式转换中的至少一个。
可选地，基于低分辨率图像的图像分辨率和接收低分辨率率图像的数据端口的传输率中的至少一个来确定低分辨率图像将分割成的多个子帧的数量。
可选地，色彩空间转换包括将子帧的色彩空间从RGB转换到YUV。
可选地，基于高分辨率图像和低分辨率图像的图像分辨率的比例来确定帧率转换的倍数。
可选地，通过像素格式转换将帧率转换后的多个子帧转换为LVDS信号，并且通过信号格式转换将LVDS信号转换为V-BY-ONE信号输出给显示设备。
根据本公开的另一方面，提出了一种视频信号转换装置，包括：视频信号接收端口，并行地接收由低分辨率图像分割而成的多个子帧；图像处理器，对接收到的每个子帧进行图像处理；以及视频信号输出端口，将图像处理后的多个子帧输出给显示设备以便合成为一帧高分辨率图像进行显示。
可选地，图像处理器在多个通道上对由一帧低分辨率图像分割而成的多个子帧并行地进行图像处理。
可选地，图像处理器包括：色彩空间转换部件，对接收到的子帧进行色彩空间转换；色彩增强处理部件，对经过色彩空间转换的子帧进行色彩增强处理；帧率转换部件，对经过色彩增强处理的子帧进行帧率转换；以及像素格式转换部件，对帧率转换后的子帧进行像素格式转换，以便输出给视频信号输出端口。
可选地，本公开的视频信号转换装置还包括信号格式转换部件，其中，通过像素格式转换部件将帧率转换后的多个子帧转换为LVDS信号，并且通过信号格式转换部件将LVDS信号转换为V-BY-ONE信号输出给显示设备。
可选地，其中视频信号接收端口是DVI端口，视频信号输出端口是V-BY-ONE端口。
可选地，低分辨率图像是分辨率为5124*2160图像，高分辨率图像是分辨率为10248x4320的图像。
可选地，图像处理器由一个或者多个FPGA实现。
根据本公开的又一方面，提出了一种显示系统，包括播放设备、高清显示器以及如上所述的视频信号转换装置。
根据本公开的视频信号转换方法、视频信号转换装置以及相应的显示系 统，可以将相对较低分辨率的视频图像在超高清显示屏上进行重新拼接而形成高分辨率视频图像进行显示，这使得可以利用播放低分辨率视频图像的播放设备来与显示高分辨率视频图像的超高清显示屏进行匹配，从而显示高分辨率图像，增强了二者的兼容性，降低了显示系统的成本，便于高清显示系统的普及。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍。显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是根据本公开的一个实施例的视频信号转换方法的流程图；
图2A是根据本公开的一个实施例的将一帧低分辨率(例如5K2K)图像分割为多个子帧的示意图；
图2B是根据本公开的实施例的利用多个DVI端口传输一个子帧的示意图；
图3A-3B是根据本公开的一个实施例的利用多个DVI端口传输多个子帧的示意图；
图3C是根据本公开的实施例的将多个子帧拼接为一帧高分辨率图像的示意图；
图4A是根据本公开的一个实施例的对视频信号进行图像处理的方法的流程图；
图4B示出了示意性的相应处理流程；
图5是根据本公开的一个实施例的利用显示屏上的时序控制器(T-CON)将接收到的经过图像处理的多个子帧拼接成一帧高分辨率(例如10K4K)图像的示意图；
图6是根据本公开的一个实施例的视频信号转换装置的示意性框图；
图7A-7B是根据本公开的实施例的显示系统的示意性框图。
具体实施方式
下面将结合附图对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。 基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，也属于本公开保护的范围。
如上所述，为了使得一般的用于播放低分辨率视频信号的播放设备与显示高分辨率视频信号的高分辨率显示屏相互兼容，根据本公开的一个方面，提出了一种视频信号转换方法，使得可以将视频信号的多帧低分辨率图像合成为一帧高分辨率图像，从而可以将播放低分辨率视频图像的播放设备与高分辨率显示屏组成显示系统以便显示高分辨率图像。作为示例，根据本公开的视频信号转换方法，可以将由播放低分辨率视频图像的播放设备输出的5K2K的低分辨率图像进行处理后，拼接为10K4K的高分辨率图像进行显示。需要说明的是，上述低分辨率5K2K以及高分辨率10K4K仅仅是为了便于说明本发明实施例的原理而引入的示例，实际上，本公开的视频信号转换方法不限于针对上述分辨率，而是可以应用到其它各种分辨率，同时保持本发明的原理。以分辨率为10K4K的高清显示屏为例，根据本公开的原理，可以由多帧低分辨率视频图像合成为一帧10K4K的高分辨率图像。如图1所示，根据本公开一实施例的视频信号转换方法包括：S10，接收由低分辨率图像分割而成的多个子帧；S20，对各个子帧进行图像处理；以及S30，将图像处理后的多个子帧合成为一帧高分辨率图像。
作为示例，如图2A所示，将一帧低分辨率(例如5K2K)图像分割为4个子帧。其中，一帧图像所要分割而成的子帧的数量至少可以基于播放低分辨率视频信号的播放设备用于输出显示数据的端口的传输率和/或要传输的图像的分辨率来确定。以目前比较流行的DVI(Digital Visual Interface)数据传输端口为例，单信道DVI支持的最高分辨率一般为1920*1200，而双信道DIV支持的最高分辨率一般为2560*1600。因此，根据要传输的图像的分辨率，所采用的DVI端口的类型，可以确定采用DVI端口的数量以及该图像所要分割而成的子帧的数量。例如，根据本公开的一个实施例，为了对一帧分辨率为5K2K的图像进行传输，可以采用8个DVI端口并行传输由该帧图像分割而成的四个子帧。
根据本公开的一实施例，以支持5K2K@60Hz的播放设备为例，为将一帧视频图像分割为多个子帧而进行分区域输出，可以采用以下方式：通过本公开的视频信号转换装置修改与播放设备上的扩充显示识别数据(Extend Display Identification Data,EDID)信息，并且将其写入播放设备的显示输出 系统，从而使得播放设备输出的视频图像被分割为多个子帧而输出。
根据一个示例，如图2B所示，传输端口DVI-A/B、传输端口DVI-C/D、传输端口DVI-E/F以及传输端口DVI-G/H并行地分别传输由一帧5K2K图像分割而成的四个子帧。实际上，如上所述，根据采用的用于传输视频信号的数据端口的传输率以及要传输的图像的分辨率，可以采用不同的方式来对要传输的图像进行子帧分割并传输；例如，如果采用的数据传输端口的传输率较低，则为了传输同样分辨率的视频图像，则需要增加数据传输端口的数量，以保证不会引入过多的信号显示延迟。自然地，上述DVI端口仅仅作为本公开的视频数据传输端口的一个示例，用于将播放设备输出的视频图像传输给视频信号转换装置的数据传输端口不限于DVI端口，而是可以采用其它各种数据传输端口，在此不作限制。
以播放分辨率为5K2K的视频图像的播放设备为例，为在10K4K高清显示屏上进行显示，需要将4帧5K2K的视频图像进行拼接以便在10K4K显示屏上进行显示；同时，由于将低分辨率图像直接拼接为高分辨率图像降低了刷新频率，而播放设备与显示屏的刷新频率一般保持一致，因此，还需要在拼接之前对低分辨率图像进行倍频，因此根据本公开的实施例，在播放设备和显示屏之间接入了视频信号转换装置，以便对低分辨率图像进行转换从而可以在高清显示屏上显示高分辨率图像。可选地，考虑到将播放设备输出的视频信号通过数据传输端口(例如，DVI端口)传输到视频信号转换装置，如果8个DVI端口一次传输一帧5K2K的图像，为拼接10K4K的高分辨率图像，则需要8个DVI端口按时间顺序依次传输四帧5K2K视频图像，而其中每一帧5K2K图像以分割而成的四个子帧并行传输。换句话说，如图3C所示，为了得到一帧10K4K高分辨率图像，可能需要16个2562x1080的子帧。当然，取决于子帧的分辨率，子帧的数量可以增加或者减少。图3A-3B示出了以四个DVI端口传输5K2K图像的示意图。如图3A所示，在时间轴上，依次传输四帧5K2K视频图像，其中第一帧视频图像被分割为四个子帧，分别标记为子帧1、子帧5、子帧9和子帧13，第二帧视频图像被分割为四个子帧，分别被标记为子帧2、子帧6、子帧10和子帧14，第三帧视频图像被分割为四个子帧，分别被标记为子帧3、子帧7、子帧11和子帧15，第四帧视频图像被分割为四个子帧，分别被标记为子帧4、子帧8、子帧12和子帧16。在时间顺序上，DVI-A/B依次传输子帧1、2、3和4，DVI-C/D依次传输子帧5、6、7和8，DVI-E/F依次传输子 帧9、10、11和12，而DVI-G/H依次传输子帧13、14、15和16。
相应地，根据本公开的一实施例，为便于在视频转换装置对各个子帧进行解析，可以播放设备发送子帧时加入一起始帧。这样，在视频转换装置接收到起始帧时，可以开始计数，从而区分出由要传输的一帧视频图像所分割而成的四个子帧。例如，如图3B所示，对于传输端口DVI-A/B，在接收到起始帧时，可以开始计数，从而区分出子帧1、子帧2、子帧3和子帧4；类似地，对于传输端口DVI-C/D，在接收到起始子帧之后，可以开始计数，从而区分出子帧5、子帧6、子帧7和子帧8；其它以此类推，在此不再赘述。
根据本公开的一实施例，在视频信号转换装置接收到由一帧低分辨率图像分割而成的多个子帧之后，需要对各个子帧进行图像处理，以便最终在高清显示屏上拼接出一帧高分辨率图像。以下以DVI-A/B端口为例，来说明对各个子帧所进行的图像处理的具体过程。如图4A所示，首先，在通过传输端口DVI-A/B接收到子帧(例如子帧1)之后，如步骤S400所示，对子帧1进行色彩空间转换，以便于之后的进一步处理。作为示例，可以对子帧1进行RGB色彩空间到YUV色彩空间的转换，将子帧1中每个像素点的红色(R)、绿色(G)和蓝色(B)分量值转换为YUV值，其中Y表示像素点的亮度分量，而U和V分别表示像素点的色差分量，从而将像素点的亮度信息从色度信息中分离出去，便于更有效地表示彩色图像。进行色彩空间转换的目的还在于可以降低数据处理量，提高数据处理效率。
当然，上述对子帧进行从RGB到YUV的色彩空间转换仅仅是本公开的示例，对于本领域技术人员而言，根据需要，完全可以采用其它各种形式的色彩空间转换，例如RGB到HSV色彩空间转换，而不限于进行RGB到YUV色彩空间转换。
在进行了色彩空间转换之后，如步骤S410所示，对子帧进行色彩增强处理，从而改善子帧图像的视觉效果，突出图像的特征。实际上，如本领域技术人员所熟知的，可以采用各种色彩增强算法来进行色彩增强，从而提高子帧色彩的视觉效果，具体细节不在此赘述。
在完成了色彩增强处理之后，如步骤S420所示，对子帧进行帧率转换。帧率转换的目的在于，为了在将低分辨率的子帧拼接为高分辨率的图像之后保持整个图像的刷新频率不变，需要将子帧进行倍频处理。
另外，考虑到将多个子帧最终在高清显示屏上合成为一帧高分辨率图像 进行显示，而视频信号转换装置与高清显示屏之间的数据传输端口的数据传输率有限，如步骤S430所示，可以在帧率转换之后，进行像素格式转换。换句话说，为了充分利用视频信号转换装置和高清显示屏之间的数据传输端口的性能，提高信号传输效率，需要对要传输的图像信号进行像素格式转换，以便以合适的数据传输方式将要拼接成一帧高分辨率图像所需的图像信号传输给高清显示屏的时序控制器(T-CON)，并且最终由其在高清显示屏上拼接为高分辨率视频图像。
需要说明的是，尽管在图4A中，对于各个子帧进行的上述图像处理的步骤是按照一定的顺序进行的。然而，这不表明必须严格按照这样的顺序来实施本公开的视频信号转换方法，也不表明其中所有的步骤在任何情况下都是必需的。实际上，根据实际需要，本领域技术人员可以改变各个步骤之间的先后顺序，甚至去除其中的一个或者多个步骤，而不脱离本发明的原理。例如，其中的色彩空间转换步骤或者色彩增强处理步骤可以根据实际需要而调整。
图4B示出了以传输端口DVI-A/B输入的2562x1080的子帧为例，对其进行图像处理的信号流程。如图4B所示，由传输端口DVI-A/B接收的2562x1080@60Hz的子帧被解码之后，对其进行色彩空间转换。可选地，将其从RGB空间转换到YUV空间；然后，在YUV空间上对色彩空间转换后的子帧进行色彩增强处理。为了提高系统的处理效率并且降低系统的硬件成本，两路1281x1080@60Hz的视频信号同时进行并行处理，其中每一路在时间的维度上可视为4路1281x1080@15Hz的视频信号。在完成了色彩增强处理之后，对各个子帧进行帧率转换。根据本公开的一实施例，这可以通过帧率转换模块(Frame Rate Conversion)与双倍速率动态随机存储器(DDRSDRAM，简称DDR)芯片进行交互处理，完成简单的4倍帧复制而实现。可选地，可以将15Hz的视频信号写入DDR芯片，并且以60Hz从DDR芯片读出视频信号，从而实现帧率转换。
以上以双端口DVI-A/B接收一个2562x1080的子帧为例，参照图4B说明了对其进行色彩空间转换、色彩增强处理以及帧率转换的具体步骤。在完成了帧率转换之后，为将经过处理的各个子帧由视频信号转换装置传输到高清显示屏以便拼接成一帧高分辨率图像，需要对多个子帧进行像素格式转换。可选地，进行了帧率转换后的四个子帧，例如，2562x1080@60Hz的四个子 帧1、子帧2、子帧3和子帧4，在列方向被拼接成2562x4320@60Hz的子图像。为了提高处理速度，降低对处理硬件的需求，可选地，可以将该子图像分割为6路进行并行处理，其中每一路为424x4320@60Hz。在像素格式转换部件对这6路信号进行并行处理。其它双端口DVI-C/D,DVI-E/F,DVI-G/H分别接收的连续四个子帧在各自进行了色彩空间转换、色彩增强处理以及帧率转换之后，同样拼接成2562x4320@60Hz的子图像，并且分割成6路信号424x4320@60Hz送入像素格式转换部件进行处理。像素格式转换部件将其转换为低压差分信号(Low Voltage Differential Signal,LVDS)信号输出。为了提高数据传输率、减少信号电缆和连接器的数量，从而减少成本和节省空间，并且考虑到增加信号传输的抗干扰能力，可选地，可以通过转换芯片将LVDS信号转换为V-BY-ONE信号，并且通过视频信号转换装置的V-BY-ONE端口将其传输给高清显示屏的时序控制器。具体地，可以通过信号转换芯片将像素格式转换部件输出的LVDS信号转换为V-BY-ONE信号，并且例如通过16信道的V-BY-ONE端口将分辨率为5K2K@60Hz的子图像输出给高清显示屏的时序控制器(T-CON)，T-CON将接收的V-BY-ONE数字信号转换为RGB数据驱动信号及扫描驱动信号，从而驱动高清显示屏显示图像。考虑到最终在显示器上显示例如分辨率为10K4K@60Hz的图像，因此，如图5所示，需要4路16信道的V-BY-ONE端口来并行传输四帧子图像，从而能够在高清显示屏上利用该四帧子图像拼接成一帧完整的10K4K@60Hz的高清图像。
可选地，考虑到相邻边界的处理情况，由DVI端口所输入的子帧可以适当增加几列或者几行，例如不限于2562x 1080中的2562行或者1080列，而是可以稍多于2562行或者1080列。
图6示出了根据本公开的一实施例的视频信号转换装置的结构框图。如图6所示，该视频信号转换装置包括：至少一个视频信号接收端口610，接收来自视频播放设备的视频信号；图像处理芯片620，对接收到的视频信号中的各帧图像进行图像处理；以及至少一个视频信号输出端口630，将进行了图像处理的各帧图像输出给显示设备。
可选地，图像处理芯片包括：色彩空间转换部件6210，对视频信号接收端口610接收的各帧图像进行色彩空间转换；色彩增强部件6220，对各帧图像进行色彩增强；以及帧率转换部件6230，对进行了色彩增强的各帧图像进行帧率转换；以及像素格式转换部件6240，将帧率转换后的各帧图像进行像素 格式转换，并且输出给视频信号输出端口630。
可选地，图像处理芯片还包括，图像解码部件6250，在色彩空间转换部件6210对各帧图像进行色彩空间转换之前，对接收到的各帧图像进行图像解码。
可选地，视频信号接收端口采用DVI端口，视频信号输出端口采用V-BY-ONE端口。
可选地，由FPGA(Field－Programmable Gate Array，现场可编程门阵列)实现图像处理芯片。作为替代，也可以由其它硬件来实现对各帧进行图像处理，其包括但不限于DSP(数字信号处理器)、ASIC(Application Specific Integrated Circuit，专用集成电路)、CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)，专用或者通用的图像处理器来实现相同的功能，在此不作限制。
可选地，在像素格式转换部件输出的信号是LVDS信号的情况下，该视频信号转换装置(或者图像处理芯片620)还包括LVDS转换部件，其将LVDS信号转换为V-BY-ONE信号输出给视频信号输出端口630。
以下以将视频播放设备输出的5K2K@60Hz的低分辨率视频信号转换为10K2K@60Hz的高分辨率视频信号为例，对本公开实施例的视频信号转换装置进行具体说明。应注意到，以下的具体说明中出现的用于对视频信号进行处理的各个元件的数量、类型以及对相关处理的先后顺序不是对本公开原理的限制，而仅仅是为了便于理解本公开的原理所引入的示例。实际上，根据本公开的原理，本领域技术人员完全可以增加或者减少有关元件的数量，将某些类型的元件替换为其他类型的元件，改变相关处理的之间的先后顺序，或者使之并行执行，而不脱离实现本公开的原理。可选地，可以将本公开中的一个或者多个元件集成在一起，或者将单独的一个元件分立为若干元件来实现同样的功能。这些变型也应属于本公开的范围。
图7A-7B图示了根据本公开的实施例的显示系统的示意性结构。如图7A所示，该视频信号转换装置连接在播放器和高清显示面板之间，其中，该视频信号转换装置采用DVI端口作为视频信号接收端口。如上所述，为了将视频播放设备(其包括但不限于个人电脑、电视机、DVR、机顶盒等)播放的低分辨率视频图像(例如5K2K@60Hz)转换为高清显示面板显示的高分辨率视频图像(例如10K2K@60Hz)，该视频信号转换装置接收视频播放设备输出 的低分辨率视频信号。考虑到DVI端口的有限数据传输率并且为了降低硬件成本，在本实施例中，采用8个DVI端口接收视频播放设备输出的一帧图像，其中两个DVI端口组成一组，接收由低分辨率图像分割而成的2562x1080@60Hz的子帧。
可选地，在播放设备支持以5K2K@60Hz播放视频图像的情况下，为将一帧视频图像分割为多个子帧而进行分区域输出，可以通过修改与播放设备连接的视频信号转换装置上的FPGA板上的扩充显示识别数据(Extend Display Identification Data,EDID)信息，并且将其写入播放设备的显示输出系统，从而使得播放设备输出的视频图像被分割为多个子帧而输出。可选地，如图2A所示，将播放设备输出的5K2K@60Hz的低分辨率图像分割为四个子帧，每个子帧由两个DVI端口传输。另外，视频信号转换装置用于接收播放设备输出的视频图像的视频信号接收端口不限于DVI端口，而是可以采用其它各种端口，例如，可以采用HMDI端口，在此不作限制。在这种情况下，可以根据HMDI端口的数据传输率来确定播放设备输出的视频图像所分割成的子帧的数量。
如图7A所示，采用4对DVI端口接收来自视频播放设备输出的5K2K@60Hz视频信号，其中一对DVI端口对应于两个DVI通道，接收2562x1080@60Hz的子帧。为了提高系统处理效率，减少信号处理所引起的显示延迟，在根据本公开实施例的视频信号转换装置中，采用并行的四路通道来分别同时对由5K2K@60Hz视频信号所分割的四个子帧进行图像处理。以下以DVI-A/B端口为例，首先，将接收到的子帧输入到图像处理芯片620中，由其中的图像解码部件6250对其进行解码(当然，取决于实际应用，解码可能不是必须的)；然后，色彩空间转换部件6210对解码后的子帧进行色彩空间转换。作为示例，可以对子帧进行RGB色彩空间到YUV色彩空间的转换，将子帧中每个像素点的红色(R)、绿色(G)和蓝色(B)分量值转换为YUV值，其中Y表示像素点的亮度分量，而U和V分别表示像素点的色差分量，从而将像素点的亮度信息从色度信息中分离出去，便于更有效地表示彩色图像。进行色彩空间转换的目的还在于可以降低数据处理量，提高数据处理效率。当然，如上所述，上述对子帧进行从RGB到YUV的色彩空间转换仅仅是本公开的示例，对于本领域技术人员而言，根据需要，完全可以采用其它各种形式的色彩空间转换，例如RGB到HSV色彩空间转换，而不限于进行RGB到YUV色彩 空间转换。
在色彩空间转换部件6210对子帧进行了色彩空间转换之后，色彩增强部件622对子帧进行色彩增强处理，从而改善子帧图像的视觉效果，突出图像的特征。实际上，如本领域技术人员所熟知的，可以采用各种色彩增强算法来进行色彩增强，从而提高子帧色彩的视觉效果，具体细节不在此赘述。
在色彩空间增强部件6220对子帧完成了色彩增强处理之后，帧率转换部件6230对子帧进行帧率转换。帧率转换的目的在于，为了在将低分辨率的子帧拼接为高分辨率的图像之后保持图像的刷新频率不变，需要将子帧进行倍频处理。
可选地，在一对DVI端口DVI-A/B接收到2562x1080@60Hz子帧时，可以将两路1281x1080@60Hz的视频信号同时进行并行图像处理，其中每一路在时间的维度上可分为4路1281x1080@15Hz的视频信号进行处理。通过帧率转换部件6230对1281x1080@15Hz的视频信号进行倍频，例如，可以通过帧率转换部件6230与DDR芯片进行交互处理，即可完成简单的4倍帧复制而实现。可选地，可以将15Hz的视频信号写入DDR芯片，并且以60Hz从DDR芯片读出视频信号，从而实现帧率转换。
以上以两路DVI信号组成的一个子帧为例，说明了对其进行包括色彩空间转换、色彩增强处理以及帧率转换的具体过程。可选地，由于在时间维度上，如图3A所示，一对DVI端口DVI-A和DVI-B顺序接收2562x1080@60Hz的四个子帧1，2，3和4，为了最终在高清显示面板上显示10248x4320的视频图像，需要将四对DVI端口接收的16个子帧进行拼接，例如可以按照图3C的排布方式来进行拼接，其中子帧1、2、3和4顺序来自于DVI-A/B,子帧5、6、7和8顺序来自于DVI-C/D，子帧9、10、11和12顺序来自于DVI-E/F,子帧13、14、15和16顺序来自于DVI-G/H。如果将这种2562x1080@60Hz的子帧直接拼接为10248x4320的高分辨率图像，则会降低视频图像在高清显示面板上的刷新频率。因此，在拼接之前，利用帧率转换部件分别对各个子帧进行4倍频复制，以便与显示面板10248x4320@60Hz的性能相匹配。
在帧率转换部件对子帧完成了帧率转换之后，需要进行像素格式转换，以便可以将最终被拼接为10K4K@60Hz高分辨率图像的各个子帧从视频信号转换装置发送到高清显示面板。进行了帧率转换后的四个子帧，例如， 2562x1080@60Hz子帧1、子帧2、子帧3和子帧4在列方向拼接成2562x4320@60Hz的子图像。为了提高处理速度，降低对处理硬件的要求，可选地，如图4B所示可以将该子图像分割为6路进行并行处理，其中每一路代表424x4320@60Hz。将这6路信号送入像素格式转换部件6240进行并行处理，转换为低压差分信号(Low Voltage Differential Signal,LVDS)信号输出。当然以上仅仅是对一对DVI端口接收的子帧的处理，其它三对DVI端口接收的子帧经过各自的处理后，也被输出给像素格式转换部件6240；由此，四对DVI端口接收到的16个子帧在经过色彩空间转换部件、色彩增强部件以及帧率转换部件的处理之后，由像素格式转换部件转换为LVDS图像信号。
为了提高数据传输率、减少信号电缆和连接器的数量，从而减少成本和节省空间，并且考虑到增加信号传输的抗干扰能力，可选地，可以通过转换芯片将LVDS信号转换为V-BY-ONE信号，并且通过视频信号转换装置的V-BY-ONE端口将其传输给高清显示面板的时序控制器。具体地，可以通过信号转换芯片将像素格式转换部件输出的LVDS信号转换为V-BY-ONE信号，并且例如通过16信道的V-BY-ONE端口将5K2K@60Hz的子图像输出给高清显示面板的时序控制器(T-CON)，T-CON将接收的V-BY-ONE数字信号转换为RGB数据驱动信号及扫描驱动信号，从而驱动高清显示面板显示图像。考虑到最终在显示器上显示例如分辨率为10K4K@60Hz的图像，因此，如图5所示，需要4路16信道的V-BY-ONE端口来并行传输四帧子图像，从而能够在高清显示面板上利用该四帧子图像拼接成一帧完整的10K4K@60Hz的高清图像。
可选地，考虑到相邻边界的处理情况，由DVI端口所输入的子帧可以适当增加几列或者几行，例如不限于2562x 1080中的2562行或者1080列，而是可以稍多于2562行或者1080列。
最终，实现了在高清显示面板上显示10K4K@60Hz的图像。
如上所述，可以通过FPGA来实现本公开中的视频信号转换装置中的图像处理芯片。在具体实施时，如图7A所示，可以利用一片FPGA来实现对所有视频信号接收端口接收的子帧的图像处理，其中对每一对DVI端口设置单独的图像处理通道，从而实现对各个子帧的色彩空间转换、色彩增强以及帧率转换，最后对所有子帧进行像素格式转换，并且将像素格式转换部件输出的 LVDS信号转换为V-BY-ONE信号且通过视频信号输出端口输出给显示面板。
可选地，如图7B所示，可以针对每一对DVI端口设置单独的一片FPGA，完成对该对DVI端口接收的各个子帧的图像处理，即，每一片FPGA单独地对一对DVI端口接收的子帧进行色彩空间转换、色彩增强、帧率转换，像素格式转换，并且将像素格式转换部件输出的LVDS信号转换为V-BY-ONE信号且通过视频信号输出端口输出给显示面板。换句话说，对每一对DVI端口接收的子帧分别利用各自的FPGA来进行视频信号转换。
此外，尽管在图7A和7B中示出了高清显示面板包括四个时序控制器(T-CON)，其中每一个用于一路16通道V-BY-ONE端口传输来的视频信号，即5K2K@60Hz的信号，然而，这仅仅是一种示例。实际上，完全可以采用一个时序控制器来实现对四路16通道V-BY-ONE端口传输来的视频信号进行处理，从而驱动高清显示面板显示10K4K@60Hz的视频图像。因此，在本公开中，对高清显示面板中的时序控制器的数量不作限制。
根据本公开的视频信号转换方法、视频信号转换装置以及相应的显示系统，可以将相对较低分辨率的视频图像在超高清显示屏上进行重新拼接而形成高分辨率视频图像进行显示，这使得可以利用播放低分辨率视频图像的播放设备来与显示高分辨率视频图像的超高清显示屏进行匹配，从而显示高分辨率图像，增强了二者的兼容性，降低了显示系统的成本，便于高清显示系统的普及。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开实施例公开的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应该以权利要求的保护范围为准。
本申请要求于2015年9月24日递交的中国专利申请第201510617475.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种视频信号转换方法，包括：
    并行地接收由视频信号的低分辨率图像分割而成的多个子帧；
    对接收到的每个子帧进行图像处理；以及
    将图像处理后的多个子帧合成为一帧高分辨率图像从而在显示设备上进行显示。
  2. 根据权利要求1所述的视频信号转换方法，其中，在多个处理通道上对由一帧低分辨率图像分割而成的多个子帧并行地进行图像处理。
  3. 根据权利要求1或2所述的视频信号转换方法，其中，所述图像处理包括：色彩空间转换、色彩增强处理、帧率转换和像素格式转换中的至少一个。
  4. 根据权利要求1-3任一项所述的视频信号转换方法，其中，基于低分辨率图像的图像分辨率和接收低分辨率率图像的数据端口的传输率中的至少一个来确定低分辨率图像将分割成的多个子帧的数量。
  5. 根据权利要求3所述的视频信号转换方法，其中色彩空间转换包括将子帧的色彩空间从RGB转换到YUV。
  6. 根据权利要求3和5任一项所述的视频信号转换方法，其中基于高分辨率图像和低分辨率图像的图像分辨率的比例来确定帧率转换的倍数。
  7. 根据权利要求3、5和6任一项所述的视频信号转换方法，其中，通过像素格式转换将帧率转换后的多个子帧转换为LVDS信号，并且通过信号格式转换将LVDS信号转换为V-BY-ONE信号输出给显示设备。
  8. 一种视频信号转换装置，包括：
    视频信号接收端口，并行地接收由低分辨率图像分割而成的多个子帧；
    图像处理器，对接收到的每个子帧进行图像处理；以及
    视频信号输出端口，将图像处理后的多个子帧输出给显示设备以便合成为一帧高分辨率图像进行显示。
  9. 根据权利要求8所述的视频信号转换装置，其中，图像处理器在多个通道上对由一帧低分辨率图像分割而成的多个子帧并行地进行图像处理。
  10. 根据权利要求8或9所述的视频信号转换装置，其中，图像处理器包括：
    色彩空间转换部件，对接收到的子帧进行色彩空间转换；
    色彩增强处理部件，对经过色彩空间转换的子帧进行色彩增强处理；
    帧率转换部件，对经过色彩增强处理的子帧进行帧率转换；以及
    像素格式转换部件，对帧率转换后的子帧进行像素格式转换，以便输出给视频信号输出端口。
  11. 根据权利要求8-10任一项所述的视频信号转换装置，其中，基于低分辨率图像的图像分辨率和接收低分辨率图像的视频信号接收端口的传输率中的至少一个来确定低分辨率图像所分割成的多个子帧的数量。
  12. 根据权利要求10所述的视频信号转换装置，其中色彩空间转换部件将接收到的子帧的色彩空间从RGB转换到YUV。
  13. 根据权利要求10和12任一项所述的视频信号转换装置，其中基于高分辨率图像和低分辨率图像的图像分辨率的比例来确定帧率转换的倍数。
  14. 根据权利要求10、12和13任一项所述的视频信号转换装置，还包括信号格式转换部件，其中，通过像素格式转换部件将帧率转换后的多个子帧转换为LVDS信号，并且通过信号格式转换部件将LVDS信号转换为V-BY-ONE信号输出给显示设备。
  15. 一种显示系统，包括播放设备、高清显示器以及如上权利要求8-14任一项所述的视频信号转换装置。
PCT/CN2016/074030 2015-09-24 2016-02-18 视频信号转换方法、视频信号转换装置以及显示系统 WO2017049858A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/541,923 US20180013978A1 (en) 2015-09-24 2016-02-18 Video signal conversion method, video signal conversion device and display system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510617475.XA CN105141876B (zh) 2015-09-24 2015-09-24 视频信号转换方法、视频信号转换装置以及显示系统
CN201510617475.X 2015-09-24

Publications (1)

Publication Number Publication Date
WO2017049858A1 true WO2017049858A1 (zh) 2017-03-30

Family

ID=54727072

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/074030 WO2017049858A1 (zh) 2015-09-24 2016-02-18 视频信号转换方法、视频信号转换装置以及显示系统

Country Status (3)

Country Link
US (1) US20180013978A1 (zh)
CN (1) CN105141876B (zh)
WO (1) WO2017049858A1 (zh)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10192088B2 (en) * 2015-03-26 2019-01-29 Nec Display Solutions, Ltd. Video signal monitoring method, video signal monitoring device, and display device
CN105141876B (zh) * 2015-09-24 2019-02-22 京东方科技集团股份有限公司 视频信号转换方法、视频信号转换装置以及显示系统
CN105611213A (zh) 2016-01-04 2016-05-25 京东方科技集团股份有限公司 一种图像处理方法、播放方法及相关的装置和系统
CN105704508A (zh) * 2016-01-06 2016-06-22 无锡天脉聚源传媒科技有限公司 一种视频合并方法及装置
CN105704407B (zh) * 2016-01-29 2017-12-22 京东方科技集团股份有限公司 一种显示处理装置、设备及方法
CN105744202B9 (zh) * 2016-02-05 2024-03-22 武汉精测电子技术股份有限公司 一种v-by-one信号处理方法及装置
CN107155131A (zh) * 2016-03-02 2017-09-12 王进洪 一种视频图像分辨率处理系统及方法
CN105721818B (zh) * 2016-03-18 2018-10-09 武汉精测电子集团股份有限公司 一种信号转换方法及装置
CN113347374A (zh) * 2016-08-25 2021-09-03 上海交通大学 基于多分辨率的多视角媒体呈现方法
CN106341696A (zh) * 2016-09-28 2017-01-18 北京奇虎科技有限公司 一种直播视频流处理方法和装置
KR102568911B1 (ko) * 2016-11-25 2023-08-22 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
CN106993150B (zh) * 2017-04-14 2024-02-06 深圳市唯奥视讯技术有限公司 一种兼容超高清视频输入的视频图像处理系统及方法
JP7184488B2 (ja) 2017-04-21 2022-12-06 株式会社半導体エネルギー研究所 画像処理方法および受像装置
CN107205176B (zh) * 2017-07-17 2020-12-29 深圳创维－Rgb电子有限公司 一种信号转换装置及转换方法
WO2019038651A1 (ja) * 2017-08-24 2019-02-28 株式会社半導体エネルギー研究所 画像処理方法
CN107483914A (zh) * 2017-09-20 2017-12-15 歌尔科技有限公司 在vr一体机显示高清图像的方法及vr一体机
CN109801586B (zh) * 2019-03-26 2021-01-26 京东方科技集团股份有限公司 显示控制器、显示控制方法及系统、显示装置
CN112055159A (zh) * 2019-06-06 2020-12-08 海信视像科技股份有限公司 画质处理装置和显示设备
CN110232870A (zh) * 2019-06-12 2019-09-13 深圳市福瑞达显示技术有限公司 一种风扇屏拼接显示系统及其显示方法
US11250763B2 (en) * 2019-06-21 2022-02-15 Boe Technology Group Co., Ltd. Picture frame display apparatus and a display method
CN110475149B (zh) * 2019-08-30 2020-04-03 广州波视信息科技股份有限公司 一种超高清视频的处理方法及系统
WO2021042661A1 (zh) * 2019-09-06 2021-03-11 海信视像科技股份有限公司 一种显示设备及图像输出方法
CN112748834B (zh) 2019-10-31 2022-11-01 京东方科技集团股份有限公司 一种显示方法、显示装置、电子设备及存储介质
CN112929588B (zh) * 2019-12-06 2023-08-15 海信视像科技股份有限公司 显示设备和图像数据处理方法
KR20210078218A (ko) * 2019-12-18 2021-06-28 삼성전자주식회사 전자장치 및 그 제어방법
CN113424487B (zh) * 2019-12-19 2023-05-30 上海飞来信息科技有限公司 用于视频显示的方法、装置及计算机存储介质
CN112423109B (zh) * 2020-05-19 2023-03-03 上海哔哩哔哩科技有限公司 互动视频的生成方法、系统、电子设备和存储介质
CN113747099B (zh) * 2020-05-29 2022-12-06 华为技术有限公司 视频传输方法和设备
CN113946301B (zh) * 2020-07-16 2024-02-09 京东方科技集团股份有限公司 拼接显示系统及其图像处理方法
CN114173054B (zh) * 2020-09-10 2024-03-15 西安诺瓦星云科技股份有限公司 多帧频拼接视频源显示控制方法及其系统和led显示系统
CN112153453B (zh) * 2020-09-22 2023-11-28 王鹏 一种用于信息安全防护的显示系统
CN112486440B (zh) * 2020-11-05 2024-03-19 Tcl华星光电技术有限公司 一种算法验证方法和算法验证系统
CN112689111B (zh) * 2020-12-21 2023-04-07 峰米(北京)科技有限公司 一种视频处理方法、装置、终端和存储介质
CN113286100B (zh) * 2021-05-17 2022-12-13 西安诺瓦星云科技股份有限公司 视频输出接口的配置方法及装置、视频输出设备
CN113409719B (zh) * 2021-08-19 2021-11-16 南京芯视元电子有限公司 视频源显示方法、系统、微显示芯片和存储介质
CN114245201A (zh) * 2021-11-25 2022-03-25 湖南翰博薇微电子科技有限公司 视频扩屏显示方法、装置、系统、计算机设备及存储介质
WO2023154109A1 (en) * 2022-02-10 2023-08-17 Innopeak Technology, Inc. Methods and systems for upscaling video graphics
CN114760401A (zh) * 2022-04-14 2022-07-15 上海富瀚微电子股份有限公司 直接扩展图像处理芯片并行接口的输出视频分辨率的方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102047287A (zh) * 2008-06-17 2011-05-04 株式会社Ntt都科摩 利用稀疏变换的图像/视频质量增强和超分辨率
CN103414893A (zh) * 2013-07-26 2013-11-27 香港应用科技研究院有限公司 利用不可分级视频codec的空间可分级视频编码
CN104077103A (zh) * 2014-07-09 2014-10-01 上海天奕达电子科技有限公司 一种低分辨率平台支持高分辨率显示装置的方法和装置
US20150264291A1 (en) * 2014-03-17 2015-09-17 Panasonic intellectual property Management co., Ltd Projection video display apparatus
CN105141876A (zh) * 2015-09-24 2015-12-09 京东方科技集团股份有限公司 视频信号转换方法、视频信号转换装置以及显示系统
CN204906556U (zh) * 2015-09-24 2015-12-23 京东方科技集团股份有限公司 视频信号转换装置以及显示系统

Family Cites Families (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029326A (en) * 1989-08-08 1991-07-02 Pioneer Electronic Corporation Picture display system
US5768533A (en) * 1995-09-01 1998-06-16 National Semiconductor Corporation Video coding using segmented frames and retransmission to overcome channel errors
US5818419A (en) * 1995-10-31 1998-10-06 Fujitsu Limited Display device and method for driving the same
JP4192371B2 (ja) * 1999-12-09 2008-12-10 ソニー株式会社 データ受信装置及びデータ送信装置、データ送受信システム
KR100327377B1 (ko) * 2000-03-06 2002-03-06 구자홍 디지털 영상 수신기와 디지털 디스플레이 장치 사이에서디지털 영상 신호를 디스플레이 하는 방법
KR100351816B1 (ko) * 2000-03-24 2002-09-11 엘지전자 주식회사 포맷 변환 장치
US7043745B2 (en) * 2000-12-29 2006-05-09 Etalk Corporation System and method for reproducing a video session using accelerated frame recording
US7224404B2 (en) * 2001-07-30 2007-05-29 Samsung Electronics Co., Ltd. Remote display control of video/graphics data
AU2002332645A1 (en) * 2001-08-22 2003-03-10 Gary Alfred Demos Method and apparatus for providing computer-compatible fully synchronized audio/video information
US20040218269A1 (en) * 2002-01-14 2004-11-04 Divelbiss Adam W. General purpose stereoscopic 3D format conversion system and method
JP4061907B2 (ja) * 2002-01-15 2008-03-19 セイコーエプソン株式会社 画像処理済み画像データの出力および保存
US7136042B2 (en) * 2002-10-29 2006-11-14 Microsoft Corporation Display controller permitting connection of multiple displays with a single video cable
US20040090556A1 (en) * 2002-11-12 2004-05-13 John Kamieniecki Video output signal format determination in a television receiver
KR100465173B1 (ko) * 2002-11-18 2005-01-13 삼성전자주식회사 화면분할 기능을 갖는 영상디스플레이장치
US20040222941A1 (en) * 2002-12-30 2004-11-11 Wong Mark Yuk-Lun Multi-display architecture using single video controller
WO2004086748A2 (en) * 2003-03-20 2004-10-07 Covi Technologies Inc. Systems and methods for multi-resolution image processing
US7034776B1 (en) * 2003-04-08 2006-04-25 Microsoft Corporation Video division detection methods and systems
KR20050000956A (ko) * 2003-06-25 2005-01-06 엘지전자 주식회사 비디오 포맷 변환 장치
US7239355B2 (en) * 2004-05-17 2007-07-03 Mstar Semiconductor, Inc. Method of frame synchronization when scaling video and video scaling apparatus thereof
US7516255B1 (en) * 2005-03-30 2009-04-07 Teradici Corporation Method and apparatus for providing a low-latency connection between a data processor and a remote graphical user interface over a network
US20060238647A1 (en) * 2005-04-26 2006-10-26 Vihonor Opto-Electronics Co., Ltd. Video data processing method and device for amplified dynamic videos
US8019883B1 (en) * 2005-05-05 2011-09-13 Digital Display Innovations, Llc WiFi peripheral mode display system
KR101005094B1 (ko) * 2006-09-06 2010-12-30 노키아 코포레이션 향상된 비디오 디스플레이 인터페이스를 가지는 이동 단말 기기, 동글 및 외부 디스플레이 기기
WO2008068456A2 (en) * 2006-12-06 2008-06-12 Sony United Kingdom Limited A method and an apparatus for generating image content
TWI466547B (zh) * 2007-01-05 2014-12-21 Marvell World Trade Ltd 用於改善低解析度視訊之方法與系統
CN101669361B (zh) * 2007-02-16 2013-09-25 马维尔国际贸易有限公司 用于改善低分辨率和低帧速率视频的方法和系统
CN101031062B (zh) * 2007-03-21 2010-05-26 中兴通讯股份有限公司 一种移动多媒体广播电子业务指南的传输方法
US8863187B2 (en) * 2007-04-02 2014-10-14 Tp Lab, Inc. System and method for presenting multiple pictures on a television
JP5000395B2 (ja) * 2007-06-26 2012-08-15 オリンパス株式会社 撮像表示方法および撮像表示装置
US9280397B2 (en) * 2007-06-27 2016-03-08 Intel Corporation Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata
KR101394926B1 (ko) * 2007-07-10 2014-05-15 엘지디스플레이 주식회사 확장 가능한 멀티 모듈 디스플레이 장치
TWI352317B (en) * 2007-09-20 2011-11-11 Nuvoton Technology Corp Image processing methods and systems
WO2009157221A1 (ja) * 2008-06-27 2009-12-30 シャープ株式会社 液晶表示装置の制御装置、液晶表示装置、液晶表示装置の制御方法、プログラムおよびその記録媒体
US9204086B2 (en) * 2008-07-17 2015-12-01 Broadcom Corporation Method and apparatus for transmitting and using picture descriptive information in a frame rate conversion processor
US8385422B2 (en) * 2008-08-04 2013-02-26 Kabushiki Kaisha Toshiba Image processing apparatus and image processing method
US8797233B2 (en) * 2008-08-20 2014-08-05 The Regents Of The University Of California Systems, methods, and devices for dynamic management of data streams updating displays
US9179122B2 (en) * 2008-12-04 2015-11-03 Nec Corporation Image transmission system, image transmission apparatus and image transmission method
KR102553787B1 (ko) * 2008-12-19 2023-07-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 헤드 마운트 표시장치
JP5448981B2 (ja) * 2009-04-08 2014-03-19 株式会社半導体エネルギー研究所 液晶表示装置の駆動方法
WO2010138128A1 (en) * 2009-05-29 2010-12-02 Hewlett-Packard Development Company, Lp Multi-projector system and method
JP5195666B2 (ja) * 2009-06-23 2013-05-08 船井電機株式会社 映像信号処理装置
US20110069225A1 (en) * 2009-09-24 2011-03-24 Sensio Technologies Inc. Method and system for transmitting and processing high definition digital video signals
US8692937B2 (en) * 2010-02-25 2014-04-08 Silicon Image, Inc. Video frame synchronization
US20110310070A1 (en) * 2010-06-17 2011-12-22 Henry Zeng Image splitting in a multi-monitor system
US8639053B2 (en) * 2011-01-18 2014-01-28 Dimension, Inc. Methods and systems for up-scaling a standard definition (SD) video to high definition (HD) quality
KR20120090472A (ko) * 2011-02-08 2012-08-17 삼성전자주식회사 전기 영동 표시 장치의 구동 방법
US20130271650A1 (en) * 2012-04-17 2013-10-17 Yasuhiko Muto Video display apparatus and video processing method
KR101920264B1 (ko) * 2012-08-02 2019-02-08 삼성전자주식회사 디스플레이장치 및 그 제어방법과, 디스플레이 시스템
KR20140054518A (ko) * 2012-10-29 2014-05-09 삼성전자주식회사 영상처리장치 및 그 제어방법
WO2014122821A1 (ja) * 2013-02-06 2014-08-14 シャープ株式会社 表示装置及び表示装置の駆動方法
US8982277B2 (en) * 2013-04-25 2015-03-17 Broadcom Corporation System and method for processing video data
CN103347163B (zh) * 2013-06-28 2017-02-08 冠捷显示科技（厦门）有限公司 一种超高清视频图像处理和传送的系统及其方法
US9607574B2 (en) * 2013-08-09 2017-03-28 Apple Inc. Video data compression format
US10089962B2 (en) * 2013-09-27 2018-10-02 Intel Corporation Display interface partitioning
GB2526773B (en) * 2014-04-04 2020-09-30 Adder Tech Ltd Video signal transmission
US20160171916A1 (en) * 2014-04-09 2016-06-16 Pixtronix, Inc. Field sequential color (fsc) display apparatus and method employing different subframe temporal spreading
US9582852B2 (en) * 2014-04-11 2017-02-28 Vixs Systems, Inc. Video scaling using multiple video paths
KR102189726B1 (ko) * 2014-05-12 2020-12-11 삼성전자주식회사 영상처리장치 및 영상처리방법
CN104052978B (zh) * 2014-05-30 2017-02-15 京东方科技集团股份有限公司 信号处理方法、信号处理系统和显示设备
US9471955B2 (en) * 2014-06-19 2016-10-18 Apple Inc. Multiple display pipelines driving a divided display
US9880649B2 (en) * 2014-09-29 2018-01-30 Apple Inc. Touch, pen and force sensor operation with variable refresh displays
US9930423B1 (en) * 2014-10-02 2018-03-27 Sprint Spectrum L.P. Dynamic transmission time interval bundling for multicast video
US9798689B2 (en) * 2014-11-03 2017-10-24 Icron Technologies Corporation Systems and methods for enabling communication between USB type-C connections and legacy connections over an extension medium
CN104809977B (zh) * 2015-05-21 2018-04-06 京东方科技集团股份有限公司 显示面板的驱动方法、驱动装置和显示设备
CN105120187B (zh) * 2015-08-20 2018-06-19 深圳创维－Rgb电子有限公司 一种激光电视的图像处理方法、系统及激光电视
US10191709B2 (en) * 2015-09-04 2019-01-29 Samsung Electronics Co., Ltd. Display apparatus configured to determine a processing mode to transfer image contents to another display apparatus
HK1205426A2 (zh) * 2015-09-24 2015-12-11 Tfi Digital Media Ltd 種分佈式視頻編碼方法
JP2017072644A (ja) * 2015-10-05 2017-04-13 キヤノン株式会社 表示制御装置
CN105611213A (zh) * 2016-01-04 2016-05-25 京东方科技集团股份有限公司 一种图像处理方法、播放方法及相关的装置和系统
US10120187B2 (en) * 2016-02-18 2018-11-06 Nvidia Corporation Sub-frame scanout for latency reduction in virtual reality applications
JP6742816B2 (ja) * 2016-05-26 2020-08-19 キヤノン株式会社 電子機器、表示装置及び表示制御方法
US9787937B1 (en) * 2016-06-01 2017-10-10 Novatek Microelectronics Corp. Display apparatus for video wall and operation method thereof
TWI649864B (zh) * 2017-06-30 2019-02-01 香港商京鷹科技股份有限公司 影像感測裝置及影像感測方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102047287A (zh) * 2008-06-17 2011-05-04 株式会社Ntt都科摩 利用稀疏变换的图像/视频质量增强和超分辨率
CN103414893A (zh) * 2013-07-26 2013-11-27 香港应用科技研究院有限公司 利用不可分级视频codec的空间可分级视频编码
US20150264291A1 (en) * 2014-03-17 2015-09-17 Panasonic intellectual property Management co., Ltd Projection video display apparatus
CN104077103A (zh) * 2014-07-09 2014-10-01 上海天奕达电子科技有限公司 一种低分辨率平台支持高分辨率显示装置的方法和装置
CN105141876A (zh) * 2015-09-24 2015-12-09 京东方科技集团股份有限公司 视频信号转换方法、视频信号转换装置以及显示系统
CN204906556U (zh) * 2015-09-24 2015-12-23 京东方科技集团股份有限公司 视频信号转换装置以及显示系统

Also Published As

Publication number Publication date
CN105141876B (zh) 2019-02-22
US20180013978A1 (en) 2018-01-11
CN105141876A (zh) 2015-12-09

Similar Documents

Publication Publication Date Title
WO2017049858A1 (zh) 视频信号转换方法、视频信号转换装置以及显示系统
WO2017113951A1 (zh) 拼接显示系统及其显示方法
US9398245B2 (en) Display device
CN204906556U (zh) 视频信号转换装置以及显示系统
US20110210975A1 (en) Multi-screen signal processing device and multi-screen system
US9374534B2 (en) Display and method for displaying multiple frames thereof
US8401339B1 (en) Apparatus for partitioning and processing a digital image using two or more defined regions
US10482847B2 (en) Driving method and driving apparatus for display panel, and display device
TW200521941A (en) Display device and driving method thereof
KR101493905B1 (ko) 영상처리장치 및 영상처리방법
JP6782335B2 (ja) 電子装置及びその制御方法
WO2015161574A1 (zh) 用于led电视的数据处理方法、装置及led电视
TWI354981B (en) Method and related device of increasing efficiency
CN101778199A (zh) 一种合成多路高清视频图像画面的实现方法
KR100709141B1 (ko) 입체 엘씨디 멀티 디스플레이 장치
US8290339B2 (en) Video processing apparatus
CN210606585U (zh) 车机显示演示装置
TWI677245B (zh) 投影顯示設備及顯示方法
CN102244739B (zh) 图像处理装置、图像处理方法以及图像处理系统
TW201142696A (en) Image processing device and image signal processing system
JP3096562B2 (ja) 立体画像再生装置
US20240106977A1 (en) Video processor, video processing method, display control system, and electronic device
US10885871B2 (en) Scalable driving architecture for large size displays
TWI406567B (zh) 電子裝置
JP2008242209A (ja) Ｌｃｄデータ転送システム

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16847746

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 15541923

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16847746

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 23.08.2018)

122 Ep: pct application non-entry in european phase

Ref document number: 16847746

Country of ref document: EP

Kind code of ref document: A1