WO2021042661A1 - 一种显示设备及图像输出方法 - Google Patents

一种显示设备及图像输出方法 Download PDF

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Publication number
WO2021042661A1
WO2021042661A1 PCT/CN2020/072382 CN2020072382W WO2021042661A1 WO 2021042661 A1 WO2021042661 A1 WO 2021042661A1 CN 2020072382 W CN2020072382 W CN 2020072382W WO 2021042661 A1 WO2021042661 A1 WO 2021042661A1
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Prior art keywords
circuit
signal
frc
output
equal
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PCT/CN2020/072382
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English (en)
French (fr)
Inventor
李慧娟
陈俊宁
左剑
Original Assignee
海信视像科技股份有限公司
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Priority claimed from CN201910842641.4A external-priority patent/CN112468878B/zh
Priority claimed from CN201910842638.2A external-priority patent/CN112468756B/zh
Application filed by 海信视像科技股份有限公司 filed Critical 海信视像科技股份有限公司
Publication of WO2021042661A1 publication Critical patent/WO2021042661A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems

Definitions

  • This application relates to the field of display technology, and in particular to a display device and an image output method.
  • the 8k screens can display video signals with a resolution of 8k*4k (7680*4320) and a refresh rate of 120HZ.
  • 8k film sources with a resolution of 7680*4320 and a refresh rate of 120HZ are relatively scarce.
  • the video signals currently provided for screen display are mostly video signals with a resolution of 3840*2160 and a refresh rate of 60HZ, as well as lower resolution and refresh. Frequency low-quality video signal.
  • the display device in the related art includes a main control circuit 1 and a screen 2. Due to technical limitations, the main control circuit 1 can convert a low-quality video signal into a video signal with a resolution of 3840*2160 and a refresh rate of 60HZ. Although the resolution and refresh rate of the low-quality video signal can be increased, the main control When the video signal output by the circuit is transmitted to the 8K screen for display, it will be found that the video signal only occupies a quarter of the 8k screen, as shown in Figure 2. In addition, there are obvious graininess and film source jams when displayed on the 8k screen. The problem is that users cannot fully enjoy the ultimate experience of watching 8k screens.
  • the purpose of the application of this application is to provide a display device and an image output method of a display device.
  • the embodiment of the present application shows a display device
  • It includes a main control circuit, a first processing circuit, a second processing circuit, a screen, and an I2C line; the first processing circuit and the second processing circuit are connected in parallel between the main control circuit and the screen, and the main control circuit is also Connected to the first processing circuit through an I2C line;
  • the main control circuit is used to determine the first signal and the first output mode, send the first signal to the first processing circuit and the second processing circuit, and send the first output mode to the first processing circuit via the I2C line ;
  • the first processing circuit is used to process the first signal according to the first output mode to obtain the first field signal and send it to the screen, and used to determine the direction of the second field signal according to the first output mode , And notify the second processing circuit of the direction of the second field signal;
  • the second processing circuit is configured to determine a second output mode according to the direction of the second field signal, process the first signal to obtain the second field signal, and send it to the screen;
  • the screen is used to display the first field signal and the second field signal, wherein the first field signal and the second field signal form a frame of picture.
  • the first processing circuit includes:
  • the first signal processing circuit is used to perform amplification and frequency multiplication operations on the first signal to obtain the second signal;
  • the first generating circuit is configured to generate the first field signal of each frame of the second signal according to the first output mode and determine the direction of the second field signal;
  • the first sending circuit is used to send the first field signal to the screen, and to notify the second processing circuit of the direction of the second field signal.
  • the second processing circuit includes:
  • the second signal processing circuit is used to perform amplification and frequency multiplication operations on the first signal to obtain the second signal;
  • a second generating circuit configured to determine a second output mode according to the direction of the second field signal, and generate a second field signal of each frame of the second signal
  • the second sending circuit is used to send the second field signal to the screen.
  • the first signal processing circuit includes:
  • An amplifying circuit for performing an amplifying operation on the first signal to obtain a fourth signal
  • the frequency multiplication circuit is used to perform a frequency multiplication operation on the fourth signal to generate a second signal.
  • the first generation circuit includes:
  • the first determining circuit is configured to determine the direction of the first field signal according to the first output mode
  • the second determining circuit is configured to determine the direction of the second field signal according to the direction of the first field signal
  • the third generating circuit is used to generate the first field signal of each frame of the second signal according to the first output mode.
  • the first determining circuit includes:
  • Acquisition circuit used to acquire the resolution of the screen m3*n3;
  • the first output mode includes the abscissa x, the ordinate y of the output coordinates, the width w and the height h of the output width and height;
  • the first judgment circuit is used to judge whether x is equal to 0 and whether y is equal to 0;
  • the second judgment circuit is used to judge whether w is equal to 1/2m3 if x is equal to 0 and y is equal to 0;
  • the third judgment circuit is used to judge whether w is equal to m3 if w is not equal to 1/2m3;
  • the fourth judgment circuit is used for judging whether x is equal to 1/2m3 and whether w is equal to 1/2m3 if x is not equal to 0 and y is equal to 0;
  • x is not equal to 1/2m3, and/or w is not equal to 1/2m3, it is abnormal, and the direction of the first field signal is the default direction;
  • the fifth judgment circuit is used to judge whether y is equal to 1/2n3 and whether w is equal to m3 if x is equal to 0 and y is not equal to 0;
  • the main control circuit includes:
  • the conversion circuit is used to convert the third signal into the first signal according to the preset format.
  • the embodiment of the present application also shows an image output method for the main control circuit, and the method includes:
  • the first signal is determined, and the first signal is sent to the first processing circuit and the second processing circuit.
  • the embodiment of the present application also shows an image output method for a screen.
  • the method includes: displaying a first field signal and a second field signal, wherein the first field signal and the second field signal form a frame Picture.
  • the embodiment of the present application also shows an image output method used in the first processing circuit, and the method includes:
  • the first signal is processed to obtain the first field signal and sent to the screen, and used to determine the direction of the second field signal according to the first output mode, and notify the second processing circuit of the The direction of the second field signal.
  • the present application provides a display device.
  • the display device includes an SOC circuit, a first FRC circuit, a second FRC circuit, and a display screen; the SOC circuit is connected to the first FRC circuit and the second FRC circuit, respectively. FRC circuit connection;
  • the SOC circuit is configured to receive a video source signal, and determine according to the resolution and refresh frequency of the video source signal, and according to the upper limit input amount of the first FRC circuit and the upper limit input amount of the second FRC circuit SOC output signal, and input the SOC output signal to the first FRC circuit and the second FRC circuit respectively; wherein, the upper limit input amount is the maximum amount of data allowed to be input;
  • the first FRC circuit is configured to perform frequency multiplication processing on the SOC output signal to obtain a first FRC output signal, where the first FRC output signal corresponds to a left image frame;
  • the second FRC circuit is configured to perform frequency multiplication processing on the SOC output signal to obtain a second FRC output signal, where the second FRC output signal corresponds to the right picture frame;
  • the first FRC circuit is further configured to input the left side picture frame to the display screen according to the resolution and refresh frequency of the first FRC output signal;
  • the second FRC circuit is further configured to input the right side picture frame to the display screen according to the resolution and refresh frequency of the second FRC output signal;
  • the sum of the resolutions of the first FRC output signal and the second FRC output signal is equal to the target resolution, and the target resolution is the preset resolution of the display screen output signal;
  • the first FRC output The refresh frequency of the signal and the second FRC output signal is equal to the first target refresh frequency, and the first target refresh frequency is a preset refresh frequency of the display screen output signal.
  • the SOC circuit is also used for:
  • the SOC output signal is made the video source signal.
  • the SOC circuit is also used for:
  • the refresh frequency of the video source signal is less than or equal to the second target refresh frequency; the second target refresh frequency is before the frequency multiplication process, so The maximum refresh frequency that the SOC output signal can reach;
  • the refresh frequency of the video source signal is less than or equal to the second target refresh frequency
  • the resolution of the SOC output signal is made equal to the resolution of the video source signal
  • the refresh frequency of the SOC output signal is equal to the first 2.
  • the SOC circuit is also used for:
  • the resolution of the video source signal is equal to the target resolution
  • the resolution of the SOC output signal is equal to half of the target resolution
  • the refresh frequency of the SOC output signal is equal to the second target refresh frequency
  • the second target refresh frequency is the maximum refresh frequency that the SOC output signal can reach before the frequency multiplication process
  • the SOC output signal input to the first FRC circuit corresponds to the left picture frame
  • the SOC output signal input to the second FRC circuit corresponds to the right picture frame
  • the first FRC circuit is further used to determine if the resolution of the first FRC output signal is equal to the target resolution, and the refresh frequency of the first FRC output signal is equal to the first FRC output signal. At a target refresh frequency, whether the data amount of the first FRC output signal exceeds the upper limit output of the first FRC circuit; if the data amount of the first FRC output signal exceeds the upper limit output of the first FRC circuit The left side frame in the SOC output signal is subjected to frequency multiplication processing;
  • the second FRC circuit is also used to determine if the resolution of the second FRC output signal is equal to the target resolution, and the refresh frequency of the second FRC output signal is equal to the first target refresh frequency, Whether the data amount of the second FRC output signal exceeds the upper limit output amount of the second FRC circuit; if the data amount of the second FRC output signal exceeds the upper limit output amount of the second FRC circuit, the The right frame of the SOC output signal is subjected to frequency multiplication processing;
  • the upper limit output amount is the maximum amount of data allowed to be output.
  • the first general-purpose I/O interface set is preset in the first FRC circuit
  • the second general-purpose I/O interface set is preset in the second FRC circuit
  • the first general-purpose I/O interface set and the first general-purpose I/O interface set are preset in the second FRC circuit.
  • the general I/O interface set includes N general I/O interfaces respectively;
  • the first universal I/O interface set and the second universal I/O interface set are used to perform synchronization processing on the left-side picture frame and the right-side picture frame.
  • the second FRC circuit is also used for:
  • the n1 frame data in the left picture frame is discarded.
  • the first FRC circuit is also used for:
  • the n2 frames of data in the right frame are discarded.
  • the cycle is performed in the order of (0,0), (0,1), (1,0), and (1,1), which is the first general I/O interface set Write the interface value with two general I/O interfaces in the second general I/O interface set; among them, (0, 0) corresponds to the state value of 0, (0, 1) corresponds to the state value of 1, (1 , 0) corresponds to a state value of 2, and (1, 1) corresponds to a state value of 3.
  • the present application also provides another display device, including an SOC circuit, a display screen, a first FRC circuit, and a second FRC circuit.
  • the SOC circuit includes a video receiver configured to receive a video source. Signal; the SOC circuit also includes a controller configured to: according to the resolution and refresh frequency of the video source signal, and according to the upper limit input of the first FRC circuit and the second FRC The upper limit input quantity of the circuit determines the SOC output signal; wherein the upper limit input quantity is the maximum allowable input data quantity; the controller is respectively connected to the first FRC circuit and the second FRC circuit;
  • the first FRC circuit is configured to perform frequency multiplication processing on the SOC output signal to obtain a first FRC output signal, where the first FRC output signal corresponds to a left image frame;
  • the second FRC circuit is configured to perform frequency multiplication processing on the SOC output signal to obtain a second FRC output signal, where the second FRC output signal corresponds to the right picture frame;
  • the display screen is configured to receive the left picture frame and the right picture frame, and display an integrated image of the left picture frame and the right picture frame;
  • the refresh frequency of the first FRC output signal and the second FRC output signal is equal to the preset refresh frequency of the display screen output signal.
  • the present application provides an image output method for the display device according to any one of the first aspect to the eighth possible implementation manner of the first aspect, and the method includes:
  • the SOC circuit receives the video source signal, determines the SOC output signal according to the resolution and refresh frequency of the video source signal, and according to the upper limit input amount of the first FRC circuit and the upper limit input amount of the second FRC circuit, and Input the SOC output signal to the first FRC circuit and the second FRC circuit respectively; wherein the upper limit input amount is the maximum amount of data allowed to be input;
  • the first FRC circuit performs frequency multiplication processing on the SOC output signal to obtain a first FRC output signal, where the first FRC output signal corresponds to the left picture frame;
  • the second FRC circuit performs frequency multiplication processing on the SOC output signal to obtain a second FRC output signal, where the second FRC output signal corresponds to the right picture frame;
  • the first FRC circuit inputs the left side picture frame to the display screen according to the resolution and refresh frequency of the first FRC output signal
  • the second FRC circuit inputs the right side picture frame to the display screen according to the resolution and refresh frequency of the second FRC output signal
  • the sum of the resolutions of the first FRC output signal and the second FRC output signal is equal to the target resolution, and the target resolution is the preset resolution of the display screen output signal;
  • the first FRC output The refresh frequency of the signal and the second FRC output signal is equal to the first target refresh frequency, and the first target refresh frequency is a preset refresh frequency of the display screen output signal.
  • an embodiment of the present application shows a display device and an image output method.
  • the display device includes: a main control circuit, a first processing circuit, a second processing circuit, a screen, and an I2C line; A processing circuit and a second processing circuit are connected in parallel between the main control circuit and the screen.
  • the main control circuit is also connected to the first processing circuit through an I2C line; the main control circuit is used to determine the first Signal and first output mode, sending the first signal to the first processing circuit and the second processing circuit, and sending the first output mode to the first processing circuit through the I2C line; the first processing circuit is used for The first output mode is used to process the first signal to obtain the first field signal and send it to the screen, and to determine the direction of the second field signal according to the first output mode and notify the second processing circuit of the first field signal The direction of the second field signal; the second processing circuit is used to determine the second output mode according to the direction of the second field signal, process the first signal to obtain the second field signal, and send it to the screen; The screen is used to display the first field signal and the second field signal, wherein the first field signal and the second field signal form a frame of picture.
  • the first processing circuit and the second processing circuit respectively amplify and multiply the frequency of the first signal output by the main control circuit to obtain the second signal.
  • the first processing circuit and the second processing circuit The circuit performs different processing on the second signal to obtain the first field signal and the second field signal, and sends the first field signal and the second field signal to the screen respectively.
  • the first field signal and the second field signal are sent to the screen.
  • the second half-frame signal is displayed on the screen, and there will be no problems with obvious graininess, film source jams, and the picture occupying part of the screen.
  • This application can output a video signal that meets the requirements of an 8k screen when the performance of the main control circuit is imperfect.
  • two parallel FRC circuits are arranged between the SOC circuit and the display screen.
  • the first FRC circuit is used to output the right frame after the frequency multiplication process
  • the second FRC circuit is used to output the right side image frame after the frequency multiplication process. Picture frame, thereby increasing the refresh frequency of the screen output signal.
  • the format of the output signal of the SOC circuit is no longer limited to the hardware performance of a single FRC circuit.
  • the SOC circuit can be based on the resolution and refresh frequency of the video source signal, as well as the upper limit input of the two FRC circuits.
  • the video source signal is subsequently divided into left and right picture frames to be processed separately.
  • the display screen integrates the resolution of the left picture frame and the right picture frame to achieve more High-resolution display, so this application can realize high-resolution, high-refresh frequency signal display without drop-frame, thereby improving the TV picture quality and display effect.
  • Figure 1 is a schematic diagram of the structure of a display device in the related art
  • Figure 2 is a display effect diagram of a video signal with a resolution of 3840*2160 and a refresh rate of 60HZ on an 8k screen;
  • Fig. 3 is a schematic structural diagram of a display device according to an optional embodiment
  • Fig. 4 is a schematic diagram showing data processing of a display device according to an optional embodiment
  • Fig. 5 is a schematic structural diagram of a main control circuit according to an alternative embodiment
  • Fig. 6 is a schematic structural diagram of a first processing circuit according to an alternative embodiment
  • FIG. 7 is a schematic diagram of a frame of pictures in an embodiment of the application.
  • FIG. 8 is a schematic diagram of another frame of pictures in an embodiment of the application.
  • FIG. 9 is a schematic diagram of a compensation screen in an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of a first generating circuit according to an optional embodiment
  • Figure 11 is the coordinate axis of the screen with a resolution of 7680*4320;
  • FIG. 12 is a schematic diagram showing the direction of determining the first field signal according to an optional embodiment
  • FIG. 13 is a schematic diagram showing a picture in which the direction of the first field signal is the left side according to an optional embodiment
  • FIG. 14 is a schematic diagram showing a picture in which the direction of the first field signal is the upper side according to an optional embodiment
  • FIG. 15 is a schematic diagram showing a picture in which the direction of the first field signal is the right side according to an optional embodiment
  • Fig. 16 is a schematic diagram showing a picture in which the direction of the first field signal is the lower side according to an optional embodiment
  • Fig. 17 is a schematic structural diagram of a second processing circuit according to an alternative embodiment
  • Fig. 18 is a schematic structural diagram of a first signal processing circuit according to an alternative embodiment
  • Fig. 19 is a schematic structural diagram of a second signal processing circuit according to an alternative embodiment
  • FIG. 20 is a schematic diagram of a system architecture adopted when a related art display device realizes a high refresh frequency
  • FIG. 21 is a schematic diagram of a system architecture of a display device according to an embodiment of the application.
  • FIG. 22 is a flowchart of an image output method shown in another embodiment of this application.
  • FIG. 23 is a flowchart of a method for determining an SOC output signal shown in an embodiment of the application.
  • 24 is a schematic diagram of signal processing in each link of the display device architecture when the video source signal is 8K ⁇ 4K@30Hz according to an embodiment of the application;
  • FIG. 25 is a schematic diagram of signal processing in each link of the display device architecture when the video source signal is less than or equal to 4K ⁇ 2K@60Hz according to an embodiment of the application;
  • FIG. 26 is a schematic diagram of signal processing in each link of the display device architecture when the video source signal shown in an embodiment of the application is 8K ⁇ 4K@60Hz;
  • FIG. 27 is a schematic diagram of GPIOs of the first FRC circuit and the second FRC circuit shown in an embodiment of the present application;
  • FIG. 28 shows a schematic diagram of the principle of synchronization of the left side picture output by the first FRC circuit and the right side picture output by the second FRC circuit according to an embodiment of the present application;
  • FIG. 29 is a schematic diagram of a system architecture of another display device provided by another embodiment of this application.
  • an embodiment of the present application shows a display device.
  • a display device includes a main control circuit 1, a first processing circuit 3, a second processing circuit 4, a screen 2 and an I2C line 5;
  • the first processing circuit 3 and the second processing circuit 4 are connected in parallel between the main control circuit 1 and the screen 2, and the main control circuit is also connected to the first processing circuit through an I2C line.
  • the main control circuit 1 is used to determine the first signal and the first output mode, send the first signal to the first processing circuit 3 and the second processing circuit 4, and send the first signal through the I2C line 5.
  • the first processing circuit 3 and the second processing circuit 4 are initialized, so that the first processing circuit 3 and the second processing circuit 4 are in a state that can receive video signals.
  • the first output mode is sent to the first processing circuit 3 through the I2C line 5 (Inter-Integrated Circuit, integrated circuit bus), and the first processing circuit 3 receives the first Output mode.
  • the main control circuit 1 includes:
  • the obtaining circuit 11 is used to obtain the third signal
  • the conversion circuit 12 is used to convert the third signal into the first signal according to a preset format.
  • the third signal is a low-quality video signal. Since in the related art, the video signal provided for screen display also includes low-quality video signals, the embodiment of the present application first converts all the low-quality video signals into the first signal, and then sends the first signal to the first processing circuit 3 at the same time. And second processing circuit 4. The preset format is initialized through the boot phase of the system.
  • the preset format of the first signal may include a resolution of 3840*2160 and a refresh rate of 60Hz, or may include a resolution of 1920*1080, a refresh rate of 60HZ, or a preset format of the first signal.
  • the format can include a resolution of 7680*4320 and a refresh rate of 60HZ.
  • the preset format of the first signal is set to include a resolution of 3840*2160, and the refresh frequency is 60 Hz.
  • the resolution of the low-quality video signal may be 1920*1080, and the refresh rate may be 25HZ, 30HZ or 50HZ.
  • the first processing circuit 3 is used for processing the first signal according to the first output mode to obtain the first field signal and sending it to the screen 2, and for determining the second field signal according to the first output mode And notify the second processing circuit 4 of the direction of the second field signal;
  • the second processing circuit 4 is configured to determine a second output mode according to the direction of the second field signal, process the first signal to obtain the second field signal, and send it to the screen 2;
  • the main control circuit 1 may be an SOC chip (System on Chip, system on chip), and the first processing circuit 3 and the second processing circuit 4 may be FRC chips (Frame Rate Conversion, frame rate conversion),
  • the screen 2 may be a liquid crystal screen.
  • chips or displays that can meet the functions of the main control circuit 1, the first processing circuit 3, the second processing circuit 4, and the screen 2 can also be selected as the embodiment of the present application.
  • the first signal output by the main control circuit 1 cannot meet the format requirements of the video signal that needs to be played on the screen 2. Therefore, the first processing circuit 3 and the second processing circuit 4 are provided in this application to convert the first signal to obtain It can not only meet the output requirements of the first processing circuit 3 and the second processing circuit 4, but also meet the first field signal and the second field signal that enable the screen 2 to display a complete picture. It should be noted that since the pictures corresponding to the first field signal and the second field signal need to be displayed on the screen at the same time, the first field signal and the second field signal need to be sent to the screen at the same time.
  • the first field signal and the second field signal are signals on opposite sides of the picture, and the first field signal and the second field signal may be any form of dividing the picture into two video signals with the same number of pixels .
  • the direction of the first half of the frame signal can be up, down, left, and right.
  • the picture converted from the first field signal and the picture converted from the second field signal are output. Through diagonal combination, the directions of the first field signal obtained are upper left, lower left, upper right, and lower right, which is also an implementation manner of the embodiment of the present application.
  • the format of the first signal output by the main control circuit is It does not meet the format requirements for fully displaying the screen effect.
  • the first signal is displayed on the screen, there may be problems such as obvious granularity, film source freezes, and inability to fill the screen.
  • the first processing circuit 3 and the second processing circuit 4 respectively amplify and multiply the frequency of the first signal output by the main control circuit 1 to obtain the second signal, and then the first processing circuit 3 and the second processing circuit 4 then The second signal is processed differently, and finally the first signal output by the main control circuit 1 that does not meet the format requirements is converted into not only meeting the output requirements of the first processing circuit 3 and the second processing circuit 4, but also meeting the screen 2. Display the first field signal and the second field signal of the complete picture.
  • the first processing circuit 3 includes:
  • the first signal processing circuit 31 is configured to perform an amplification operation and a frequency multiplication operation on the first signal to obtain a second signal;
  • the first generating circuit 32 is configured to generate the first field signal of each frame of the second signal according to the first output mode and determine the direction of the second field signal;
  • the first sending circuit 33 is configured to send the first field signal to the screen and notify the second processing circuit 4 of the direction of the second field signal.
  • the first signal is first subjected to a frequency multiplication operation, and then the first processing circuit 3 and the second processing circuit 4 are used to transmit the two sides of the screen separately.
  • the reason is that the frequency multiplication operation is the motion estimation compensation operation.
  • motion estimation compensation is to calculate the compensated frame information based on the motion vector between the frame information. If, in order to reduce the amount of data processed by the first processing circuit 3 and the second processing circuit 4, the pictures are divided first and then the motion estimation compensation is performed, it may happen that the motion vectors of the left picture and the right picture are quite different.
  • Figures 7 and 8 are schematic diagrams of two adjacent frames of pictures.
  • the motion vector of the left picture is almost 0.
  • the compensated picture is almost the same as the original two frames. .
  • the motion vector of the picture on the right is larger, and the compensated picture is different from the original two frames.
  • Fig. 9 for the synthesized compensation picture.
  • the joint of the left picture and the right picture in Fig. 9 will be caused by the failure to connect.
  • the fracture phenomenon of the middle picture shows the phenomenon that the docking is not smooth.
  • the embodiment of the application adopts motion estimation compensation first, and then uses the first processing circuit 3 and the second processing circuit 4 to separate the two sides of the picture to ensure the combination There will be no breakage in the subsequent picture.
  • the frequency doubling operation may be a motion estimation and compensation operation, but is not limited to the motion estimation and compensation operation.
  • the first generating circuit 32 includes:
  • the first determining circuit 321 is configured to determine the direction of the first field signal according to the first output mode
  • the second determining circuit 322 is configured to determine the direction of the second field signal according to the direction of the first field signal
  • the third generating circuit 323 is configured to generate the first field signal of each frame of the second signal according to the first output mode.
  • the picture displayed on the screen 2 is composed of pictures converted from the first field signal and the second field signal.
  • the direction of the first half frame signal is opposite to the direction of the second field signal.
  • the direction of the first field signal is the left side
  • the direction of the second field signal is the right side
  • the direction of the first field signal is the upper side
  • the direction of the second field signal is the down side.
  • the first output mode can be arbitrarily set.
  • the left side and the right side of the screen may be separated, or the upper side and the lower side may be separated.
  • the first output mode includes output coordinates and output width and height.
  • the output coordinates refer to the initial coordinates of each frame of picture, including abscissa x and ordinate y; and the output width and height refer to the width w of each frame of picture. And high h.
  • the origin of the coordinate axis of the output coordinate can be set at the upper left corner of the screen. As shown in Fig. 11, Fig. 11 is the coordinate axis of the screen with a resolution of 7680*4320.
  • FIG. 12 is a schematic diagram of determining the direction of the first field signal.
  • the first determining circuit includes:
  • the acquisition circuit is used to acquire the resolution m 3 *n 3 of the screen
  • the first output mode includes the abscissa x, the ordinate y of the output coordinates, the width w and the height h of the output width and height;
  • the first judgment circuit is used to judge whether x is equal to 0 and whether y is equal to 0;
  • the second judgment circuit is used to judge whether w is equal to 1/2m 3 if x is equal to 0 and y is equal to 0;
  • the output coordinates of the first output mode are (0, 0).
  • the output coordinate is (0,0)
  • Third determination circuit for, if w is not equal to 1 / 2m 3, it is determined whether w equals m 3;
  • the direction of the first field signal is defined as the default direction. This embodiment The default direction in the middle can be left.
  • the fourth judgment circuit is used to judge whether x is equal to 1/2m 3 and whether w is equal to 1/2m 3 if x is not equal to 0 and y is equal to 0;
  • the direction of the first field signal may be the right side, and then it is determined whether x is equal to 1/2m 3 and w is equal to 1/ 2m 3 ;
  • the fifth judgment circuit 3216 is used for judging whether y is equal to 1/2n 3 and whether w is equal to m 3 if x is equal to 0 and y is not equal to 0;
  • the direction of the first field signal may be down, and then it is judged whether y is equal to 1/2n 3 , and w Is it equal to m 3 ;
  • the output coordinates of the first output mode are (0,0), the output width and height are (7680,2160), and the screen resolution is (7680,4320), then the direction of the first field signal is the upper side .
  • the output coordinates of the first output mode are (3840, 0), the output width and height (3840, 4320), and the screen resolution is (7680, 4320), then the direction of the first field signal is to the right .
  • the output coordinates of the first output mode are (0,2160), the output width and height are (7680,2160), and the screen resolution is (7680,4320), and the direction of the first field signal is the lower side .
  • the method of diagonally dividing the screen can also reduce the processing data of the first output mode and the second output mode.
  • the specific method for determining the direction of the first field signal does not deviate from the spirit and protection scope of the application, and will not be repeated again.
  • the height h of the first output mode is used to determine the direction of the first field signal.
  • the first determining circuit 321 includes:
  • the acquisition circuit is used to acquire the resolution m 3 *n 3 of the screen
  • the first judgment circuit is used to judge whether x is equal to 0 and whether y is equal to 0;
  • the second judgment circuit is used to judge whether h is equal to 1/2n 3 if x is equal to 0 and y is equal to 0;
  • the second processing circuit 4 includes:
  • the second signal processing circuit 41 is configured to perform an amplification operation and a frequency multiplication operation on the first signal to obtain a second signal;
  • the second generating circuit 42 is configured to determine a second output mode according to the direction of the second field signal, and generate a second field signal of each frame of the second signal;
  • the second sending circuit 43 is configured to send the second field signal to the screen.
  • the second output mode corresponding to the direction of the second field signal is preset.
  • the direction of the second field signal and the corresponding second output mode can be preset as follows: when the screen resolution is (7680, 4320), the direction of the second field signal is the right side, and the second output mode includes output coordinates (3840,0), the width of the output width and height is 3840, and the height of the output width and height is 4320; the direction of the second field signal is the down side, the second output mode includes the output coordinate (0,2160), the output width and height The width is 7680, and the output width and height are 2160.
  • the first signal processing circuit 31 includes:
  • the first amplifying circuit 311 is configured to perform an amplifying operation on the first signal to obtain a fourth signal
  • the first frequency multiplication circuit 312 is configured to perform a frequency multiplication operation on the fourth signal to generate a second signal.
  • the second signal processing circuit 41 includes:
  • the second amplifying circuit 411 is configured to perform an amplifying operation on the first signal to obtain a fourth signal
  • the second frequency multiplication circuit 412 is configured to perform a frequency multiplication operation on the fourth signal to generate a second signal.
  • the first signal needs to be amplified first, and then the frequency doubled. Because if the frequency of the first signal is multiplied first, and then amplified, the computational complexity of the amplifying operation will be aggravated.
  • scaling up (amplification) technology may be used.
  • the scaling up technology amplifies the first signal into a fourth signal according to a certain ratio. For example, the first signal with a resolution of 3840*2160 can be enlarged to a fourth signal with a resolution of 7680*4320.
  • the scaling up technology only changes the resolution of the first signal, and has no effect on the refresh rate.
  • the motion estimation compensation only changes the refresh frequency of the fourth signal, and has no effect on the resolution.
  • the scaling up operation is performed on the first signal, and the resolution of the obtained fourth signal is 7680*4320, and the refresh frequency is 60HZ. .
  • the resolution of the generated second signal is 7680*4320, and the refresh frequency is 120HZ.
  • the second signal has met the format requirements of the 8k screen 2 for the video signal, for example, when the resolution of the first signal is 3840*2160 and the refresh frequency is 60Hz, according to the above operations, the second signal can be obtained.
  • the resolution is 7680*4320
  • the refresh frequency is 120HZ.
  • the first processing circuit 3 and the second processing circuit 4 cannot output 7680*4320, the refresh frequency is 120HZ video Signal, that is, the hardware limitation of the first processing circuit 3 and the second processing circuit 4, so the first processing circuit 3 and the second processing circuit 4 are selected in parallel to output the field signals of different sides to reduce the amount of output data. , It can not only meet the output requirements of the first processing circuit 3 and the second processing circuit 4, but also meet the requirements of the screen 2 to display a complete picture.
  • multiple processing circuits may be used to process the first signal separately, each processing circuit obtains a partial video signal, and the partial video signals obtained by the multiple processing circuits are combined into one frame of picture.
  • the first processing circuit 3 and the second processing circuit 4 are connected in parallel to process the first signal respectively to obtain the first field signal and the second field signal.
  • the embodiment of the present application also shows an image output method for the main control circuit, and the method includes:
  • the first signal and the first output mode are determined, the first signal is sent to the first processing circuit and the second processing circuit, and the first output mode is sent to the first processing circuit through the I2C line.
  • the embodiment of the present application also shows an image output method for a screen, and the method includes:
  • the embodiment of the present application also shows an image output method used in the first processing circuit, and the method includes:
  • the first signal is processed to obtain the first field signal and sent to the screen, and used to determine the direction of the second field signal according to the first output mode, and notify the second processing circuit of the The direction of the second field signal.
  • the embodiments of the present application show a display device and an image output method.
  • the first processing circuit and the second processing circuit respectively amplify and multiply the frequency of the first signal output by the main control circuit to obtain the second signal.
  • the first processing circuit and the second processing circuit The circuit performs different processing on the second signal to obtain the first field signal and the second field signal, and sends the first field signal and the second field signal to the screen respectively.
  • the first field signal and the second field signal are sent to the screen.
  • the second half-frame signal is displayed on the screen, and there will be no problems with obvious graininess, film source jams, and the picture occupying part of the screen.
  • This application can output a video signal that meets the requirements of an 8k screen when the performance of the main control circuit is imperfect.
  • this field is committed to high-resolution and high-refresh screen display.
  • 8K ⁇ 4K@120Hz is realized on display devices.
  • the resolution of 8K ⁇ 4K can make the screen display more pixels, and the screen will be more refined.
  • the more information can be displayed in the display area.
  • the 120Hz refresh frequency TV adopts intelligent frequency multiplication drive technology on the basis of the existing 60Hz, which doubles the screen scanning and liquid crystal molecule flipping speed, which can effectively eliminate the residual image , Solve the problem of smearing of ordinary LCD screen motion pictures, reduce visual fatigue, and make the picture quality healthier.
  • the SOC circuit After the video source signal output by the signal device enters the SOC (System On Chip) circuit for processing, the SOC circuit then outputs a fixed format signal to drive the screen.
  • high-level resolution signals such as 8K-level high-resolution signals
  • the highest is currently It can only support 8K ⁇ 4K@60Hz screen display.
  • you need to use an external FRC (Frame Rate Conversion, frame Rate conversion) circuit the signal output by the SOC circuit is input into the FRC circuit, the FRC circuit multiplies the frequency of the signal, and then the FRC circuit drives the 8K ⁇ 4K@120Hz screen.
  • FRC Full Rate Conversion, frame Rate conversion
  • the system architecture of the display device includes a signal device 100, an SOC circuit 200, a first FRC circuit 300, a second FRC circuit 400, and a display device.
  • the upper limit input amount is the maximum amount of data allowed to be input
  • the output terminals of the SOC circuit 200 are respectively connected to the input terminals of the first FRC circuit 300 and the second FRC circuit 400 to input the SOC output signals to the first FRC respectively.
  • Circuit and a second FRC circuit; the first FRC circuit 300 and the second FRC circuit 400 are processed in parallel, the first FRC circuit 300 performs frequency multiplication processing on the left side picture frame to obtain the first FRC output signal, and the second FRC circuit 400 performs right The side picture frame is subjected to frequency multiplication processing to obtain the second FRC output signal;
  • the first FRC circuit is used to input the left picture frame to the display screen according to the resolution and refresh frequency of the first FRC output signal
  • the second FRC circuit is used to input the right picture frame according to the resolution and refresh of the second FRC output signal.
  • the frequency is input to the display screen, and the two FRC circuits respectively receive the SOC output signal, and simultaneously and independently perform frequency multiplication processing on the SOC output signal, so that the refresh frequency of the first FRC output signal and the second FRC output signal is equal to the first target Refresh frequency
  • the first target refresh frequency is a preset refresh frequency of the output signal of the display screen
  • the first target refresh frequency is used to indicate the desired refresh frequency of the output signal of the display screen, such as a high refresh frequency of 120 Hz.
  • the target resolution can be preset, and the resolution of the output signals of the two FRC circuits can be adjusted so that the sum of the resolution of the first FRC output signal and the second FRC output signal is equal to the target resolution
  • the target resolution is the preset resolution of the output signal of the display screen, for example, the resolution of the first FRC output signal and the second FRC output signal is equal to half of the target resolution, for example, the target resolution is 8K ⁇ 4K
  • the display screen can display the 8K ⁇ 4K resolution after integrating the left frame and the right frame.
  • the first FRC circuit 300 and the first FRC circuit can display the resolution of 8K ⁇ 4K.
  • the output ends of the two FRC circuits 400 are respectively connected to the display screen; the display screen processes the output signals of the first FRC circuit 300 and the second FRC circuit 400, thereby integrating and simultaneously displaying the left and right pictures, so that the display is output Meet the requirements of the target resolution and the first target refresh rate, and realize the display of the video signal without dropping frames.
  • Lanes can be understood as data transmission channels. The more lanes there are, the more data is input to the two FRC circuits per unit time. Therefore, lanes The number is used to characterize the amount of data that the FRC circuit can support. For example, 8lane can support a signal with a maximum input resolution of 3840 ⁇ 2160 (ie 4K ⁇ 2K) and a refresh frequency of 60Hz, while 16lane can transmit data twice as much as 8lane .
  • both the first FRC circuit 300 and the second FRC circuit 400 in this embodiment can support 16lane data input, and the two parallel FRC circuits support 32lane signal output, so that the display screen can display higher resolution
  • the number of lanes of the FRC circuit is not limited to that described in this embodiment.
  • the SOC circuit 200 can also be connected to the first FRC circuit 300 or the second FRC circuit 400 through I2C (Inter-Integrated Circuit, integrated circuit bus).
  • I2C Inter-Integrated Circuit, integrated circuit bus
  • the SOC circuit 200 is connected to the first FRC circuit 300 through I2C.
  • the SOC circuit 200 instructs the first FRC circuit 300 to process the left frame or the right frame through I2C. If the SOC circuit 200 instructs the first FRC circuit 300 to process the left frame through I2C, the second FRC circuit 400 processes Picture frame on the right.
  • the format mentioned in this embodiment refers to the resolution and refresh frequency of the signal.
  • the format of 8K ⁇ 4K@60Hz means that the resolution of the signal is 8K ⁇ 4K and the refresh frequency is 60 Hz.
  • the resolution is the precision of the screen image, which refers to the number of pixels that the display screen can display. Since the points, lines, and surfaces on the screen are composed of pixels, the more pixels the display screen can display, The finer the picture, the more information can be displayed in the screen area.
  • the 8K ⁇ 4K resolution is 7680 ⁇ 4320, which is about 33 million pixel images per frame.
  • the refresh rate refers to the number of times the screen is refreshed per second, that is, how many images can be displayed per second.
  • the unit of refresh rate is Hertz (Hz).
  • the 60Hz refresh rate of ordinary LCD TVs will show comet drag when displaying moving pictures.
  • the tail phenomenon is more suitable for watching static images because of the retention of liquid crystal molecules and the persistence of human vision.
  • the 120Hz refresh frequency LCD TV adopts intelligent double-speed driving technology to increase the screen scanning and the flipping speed of liquid crystal molecules. It realizes the leap of screen refresh frequency from 60Hz to 120Hz, effectively eliminates the residual image, solves the problem of smearing of ordinary LCD screen motion pictures, reduces visual fatigue, and makes the picture quality healthier.
  • another embodiment of the present application provides an image output method for the display device as described above, and the method includes the following steps:
  • Step S10 the SOC circuit receives the video source signal, and determines the SOC output according to the resolution and refresh frequency of the video source signal, and according to the upper limit input amount of the first FRC circuit and the upper limit input amount of the second FRC circuit Signal, and input the SOC output signal to the first FRC circuit and the second FRC circuit, respectively.
  • the refresh frequency of the SOC output signal is greater than or equal to the refresh frequency of the video source signal.
  • the upper limit input amount is the maximum amount of data allowed to be input;
  • the second FRC circuit and the first FRC circuit have the same upper limit input amount, and the upper limit input amount depends on the number of lanes at the input terminal of the FRC circuit.
  • the video source signal can be generated by the signal device 100. After the video source signal generated by the signal device 100 is input to the SOC circuit 200, the SOC circuit 200 can detect whether the video source signal is stable. If it is a stable video source signal, the SOC circuit 200 can The signal analysis terminal obtains the resolution and refresh frequency of the video source signal; if it is not a stable video source signal, it does not process and display the video source signal.
  • the video source signal includes frame data and clock. When the SOC circuit receives the video source signal, it will detect the clock information of the video source signal. For example, when the clock information is detected as 1, it will automatically control a specific register in the display device.
  • the method for determining whether the video source signal is stable is not limited to that described in this embodiment.
  • step S10 shows three ways to determine the SOC output signal.
  • the first way is step S101 to step S103
  • the second way is S101, Step S102, step S104 and step S105
  • the third way is step S101, step S102 and step S106.
  • the first way to determine the SOC output signal is specifically as follows:
  • Step S101 Determine whether the data amount of the video source signal exceeds the upper limit input amount of the first FRC circuit. Through the resolution and refresh frequency of the video source signal, the data amount of the video source signal can be determined, and the upper limit input amount can be determined according to the number of lanes of the first FRC circuit.
  • step S102 it is determined whether the resolution of the video source signal is equal to the standard resolution.
  • step S103 the SOC output signal is made the video source signal.
  • Figure 24 shows that the video source signal is 8K ⁇ 4K@30Hz, the target resolution is 8K ⁇ 4K, and the first target refresh frequency is 120Hz, that is, the display needs to output 8K ⁇ 4K@120Hz high resolution and high refresh frequency signals as an example.
  • the video source signal is 8K ⁇ 4K@30Hz
  • the corresponding data volume does not exceed the upper limit input volume of the first FRC circuit.
  • the resolution of the video source signal is equal to the target resolution, both 8K ⁇ 4K. Therefore, the SOC output signal is directly used as the video source signal.
  • the resolution of the SOC output signal is 8K ⁇ 4K
  • the refresh frequency of the SOC output signal is 30Hz.
  • the format of the signal output from the SOC circuit to the first FRC circuit is 8K ⁇ 4K@30Hz, corresponding to the signal lane 0-15;
  • the format of the output signal of the second FRC circuit is also 8K ⁇ 4K@30Hz, corresponding to signal lane16 ⁇ 31.
  • the second way to determine the SOC output signal is specifically as follows:
  • Step S101 Determine whether the data amount of the video source signal exceeds the upper limit input amount of the first FRC circuit. Through the resolution and refresh frequency of the video source signal, the data amount of the video source signal can be determined, and the upper limit input amount can be determined according to the number of lanes of the first FRC circuit.
  • step S102 it is determined whether the resolution of the video source signal is equal to the target resolution.
  • step S104 it is determined whether the refresh frequency of the video source signal is less than or equal to the second target refresh frequency; the second target refresh frequency is frequency multiplication processing Previously, the maximum refresh frequency that the SOC output signal can reach, and the second target refresh frequency is generally 60 Hz.
  • step S105 the resolution of the SOC output signal is made equal to the resolution of the video source signal, and the refresh frequency of the SOC output signal is equal to The second target refresh frequency.
  • Figure 25 shows that the video source signal is 4K ⁇ 2K@ less than or equal to 60Hz, the target resolution is 8K ⁇ 4K, and the first target The refresh frequency is 120Hz, which means that the display needs to output a high-resolution, high-refresh frequency signal of 8K ⁇ 4K@120Hz as an example.
  • the video source signal resolution is 4K ⁇ 2K (the default output signal of the TV signal device), and the refresh frequency of the video source signal is less than or equal to 60Hz (The second target refresh frequency), for example, the video source signal is 4K ⁇ 2K@25Hz or 4K ⁇ 2K@30Hz, and the data amount corresponding to the video source signal obviously does not exceed the upper limit input amount of the first FRC circuit.
  • the resolution of the SOC output signal is equal to the resolution of the video source signal
  • the refresh frequency of the SOC output signal is equal to the second target refresh frequency
  • the format of the SOC circuit output signal to the first FRC circuit is 4K ⁇ 2K@ 60Hz corresponds to signal lane0 ⁇ 7
  • the format of the signal output from the SOC circuit to the second FRC circuit is also 4K ⁇ 2K@60Hz, which corresponds to signal lane16 ⁇ 23.
  • the third way to determine the SOC output signal is specifically as follows:
  • Step S101 Determine whether the data amount of the video source signal exceeds the upper limit input amount of the first FRC circuit. Through the resolution and refresh frequency of the video source signal, the data amount of the video source signal can be determined, and the upper limit input amount can be determined according to the number of lanes of the first FRC circuit.
  • step S102 it is determined whether the resolution of the video source signal is equal to the target resolution.
  • step S106 the resolution of the SOC output signal is made equal to half of the target resolution, and the refresh frequency of the SOC output signal is equal to the second target refresh frequency .
  • the second target refresh frequency is the maximum refresh frequency that the SOC output signal can reach before the frequency multiplication process, and the second target refresh frequency is generally 60 Hz.
  • Figure 26 shows that the video source signal is 8K ⁇ 4K@60Hz, the target resolution is 8K ⁇ 4K, and the first target refresh frequency is 120Hz, that is, the display needs to output 8K ⁇ 4K@120Hz high-resolution, high-refresh frequency signals as an example.
  • the data volume corresponding to the video source signal 8K ⁇ 4K@60Hz will exceed the upper limit input of the first FRC circuit, and the resolution of the video source signal is less than that of the first FRC circuit.
  • the target resolutions are equal, 8K ⁇ 4K.
  • the SOC circuit separates the left and right picture frames from the video source signal.
  • the SOC output signal input to the first FRC circuit corresponds to the left picture frame, so the resolution of the SOC output signal corresponding to the left picture frame is reduced.
  • the SOC output signal input to the second FRC circuit corresponds to the right picture frame, so the resolution of the SOC output signal corresponding to the right picture frame is reduced to video
  • Half the resolution of the source signal that is, 4K ⁇ 4K.
  • the format of the signal output from the SOC circuit to the first FRC circuit is 4K ⁇ 4K@60Hz, corresponding to signal lane 0-15; the format of the signal output from the SOC circuit to the second FRC circuit is 4K ⁇ 4K@60Hz, corresponding to the signal lane 16-31.
  • the first FRC circuit directly multiplies the signal of the left picture frame Processing, the left picture frame is input to the display screen according to the resolution and refresh frequency of the first FRC output signal; the second FRC circuit directly multiplies the signal of the right picture frame, and the right picture frame is according to the second The resolution and refresh frequency of the FRC output signal are input to the display screen.
  • the display screen integrates the signals output by the first FRC circuit and the second FRC circuit, thereby displaying a complete picture matching the target resolution and the first target refresh frequency.
  • the SOC circuit can be flexibly set to the two FRC circuits according to the resolution and refresh frequency of the video source signal, and the upper limit input of the two FRC circuits.
  • the output signal format, and, according to the upper limit output of the two FRC circuits, the target resolution, and the first target refresh frequency, the format of the two FRC circuits output signal to the display screen is set, and finally the display screen Displays a complete picture matching the target resolution and the first target refresh rate, realizing high-resolution, high-refresh rate video signal display without missing frames.
  • the refresh rate of the video source signal may not be limited to 30Hz, 60Hz, but may also be 25Hz, 50Hz, 120Hz, etc., and the high refresh rate required for the display can be greater than or equal to 120Hz;
  • the resolution of the video source signal is not limited to It is limited to 4K ⁇ 2K and 8K ⁇ 4K, and the high resolution that the display needs to achieve is not limited to 8K ⁇ 4K, and can also be a higher level of resolution.
  • the display device needs to display a signal with high resolution and high refresh rate, such as 8K ⁇ 4K@120Hz, due to the limitation of the hardware performance of a single FRC circuit, for example, FRC supports 16lane signal input.
  • the output signal of the SOC circuit generally has two fixed formats to adapt to the input of the FRC signal. One is to halve the refresh frequency, that is, the SOC circuit outputs 8K ⁇ 4K@30Hz, but the halving of the refresh frequency will cause loss of signal transmission. Frame problem; the other is to halve the resolution, that is, the SOC circuit outputs 4K ⁇ 4K@60Hz. This method will cause the resolution of the FRC output signal to not reach the 8K level, and it will not be able to display high-resolution signals.
  • the first FRC circuit outputs the left picture frame
  • the second FRC circuit outputs the right picture frame.
  • the display can be driven. Screen, due to the use of two FRC circuits for parallel processing, so the hardware performance restrictions and requirements for a single FRC circuit are reduced.
  • the SOC circuit Based on the refresh frequency and resolution of the video source signal and the number of lanes supported by the FRC circuit, the SOC circuit can output signals.
  • the refresh frequency is greater than or equal to the refresh frequency of the video source signal, so that the signal will not lose frames due to the reduction of the refresh frequency during signal transmission, and the resolution of the output signals of the two FRC circuits is integrated, which can also ensure the resolution of the display screen.
  • the rate meets the requirements, so as to realize the high-resolution, high-refresh frequency signal without drop-frame display.
  • the format of the SOC circuit to output the signal to the two FRC circuits is 4K ⁇ 4K@60Hz, 4K ⁇ 4K@60Hz can be
  • 4K ⁇ 4K@60Hz is multiplied by the FRC circuit, the FRC circuit output is 4K ⁇ 4K@120Hz, that is, the refresh frequency is increased from 60Hz to 120Hz.
  • the resolution of each output signal of the FRC circuit is 4K ⁇ 4K.
  • the screen display resolution can be converted to 8K ⁇ 4K, thus achieving 8K ⁇ 4K@120Hz display, and in the process of signal processing and transmission, the refresh frequency of the SOC circuit output signal is equal to the refresh frequency of the video source signal (ie 60Hz), so there is no signal frame loss problem.
  • the display screen needs to achieve the target display effect of 8K ⁇ 4K@120Hz as an example.
  • the signal processing mode of each link in the display device architecture is not limited to the examples listed in Figure 21 and Figure 24 to Figure 26. Based on the display device shown in Figure 20, it can be configured differently according to the processing performance of each circuit, component and device in the architecture, the resolution and refresh frequency of the video source signal, and the target display effect to be achieved by the display screen.
  • Step S20 The first FRC circuit performs frequency multiplication processing on the SOC output signal to obtain a first FRC output signal, and the first FRC output signal corresponds to the left picture frame.
  • Step S30 the second FRC circuit performs frequency multiplication processing on the SOC output signal to obtain a second FRC output signal, the second FRC output signal corresponding to the right frame.
  • Step S20 and step S30 are executed simultaneously.
  • the SOC output signal is processed to obtain a second FRC output signal.
  • Step S20 and step S30 are executed simultaneously.
  • step S40 the first FRC circuit inputs the left side picture frame to the display screen according to the resolution and refresh frequency of the first FRC output signal.
  • step S50 the second FRC circuit inputs the right side picture frame to the display screen according to the resolution and refresh frequency of the second FRC output signal. Step S40 and step S50 are executed simultaneously.
  • the SOC output signal can be processed through MEMC (Motion Estimate and Motion Compensation), which is a motion image quality compensation technology used in LCD TVs.
  • MEMC Motion Estimate and Motion Compensation
  • the principle is to use a dynamic imaging system to calculate the compensated frame information according to the motion vector between the frame information, and add a motion compensation frame between the traditional two frames of images.
  • the refresh frequency is 60Hz
  • the frame sequence becomes "1, 1C, 2, 2C, 3, 3C, 4, 4C, 5, 5C, 6"
  • the original 60Hz refresh rate is not enough to display all the frames in the compensated frame sequence, so the refresh rate will be doubled adaptively, that is, from 60Hz to 120Hz, so as to achieve the frequency multiplication effect.
  • MEMC can increase the number of frames displayed per unit time, shorten the interval for the human eye to receive image frames, reduce the residence time of the displayed image in the retina, so it can reduce the tailing phenomenon, make the moving image clearer, and improve the display effect of the screen. At the same time, it can achieve frequency multiplication and increase the refresh rate of the display output screen. It should be noted that the manner in which the first FRC circuit and the second FRC circuit perform frequency multiplication processing is not limited to MEMC.
  • Figure 26 shows the separation processing of the left and right pictures on the video source signal in the SOC circuit.
  • the first FRC circuit receives the signal corresponding to the left picture frame directly, and the second FRC circuit directly receives the signal corresponding to the left picture frame. It is the signal corresponding to the frame on the right, so that the amount of data input to the FRC circuit is halved.
  • the signal output from the SOC circuit to the two FRC circuits in Figure 24 and Figure 25 is a complete picture signal. Since the maximum amount of data that the FRC circuit allows to output is also restricted by the number of lanes, a single FRC may not be able to output to meet the target resolution. Rate and the amount of data corresponding to the first target refresh frequency signal.
  • the format of the SOC output signal is 8K ⁇ 4K@30Hz
  • the first FRC circuit performs frequency multiplication processing to increase the refresh frequency from 30Hz to 120Hz. If the resolution of the first FRC output signal remains 8K ⁇ If 4K remains unchanged, because the FRC circuit is limited by its ability to output data, the first FRC circuit cannot output a signal of 8K ⁇ 4K@120Hz.
  • the first FRC circuit is further configured to: determine if the resolution of the first FRC output signal is equal to the target resolution, and the first FRC output When the signal refresh frequency is equal to the first target refresh frequency, whether the data amount of the first FRC output signal exceeds the upper limit output amount of the first FRC circuit; if the data amount of the first FRC output signal exceeds the first FRC circuit For an upper limit output of the FRC circuit, frequency multiplication processing is performed on the left frame of the SOC output signal;
  • the second FRC circuit is also used to determine if the resolution of the second FRC output signal is equal to the target resolution, and the refresh frequency of the second FRC output signal is equal to the first target refresh frequency, Whether the data amount of the second FRC output signal exceeds the upper limit output amount of the second FRC circuit; if the data amount of the second FRC output signal exceeds the upper limit output amount of the second FRC circuit, the The right frame of the SOC output signal is subjected to frequency multiplication processing;
  • the upper limit output amount is the maximum amount of data allowed to be output.
  • the second FRC circuit and the first FRC circuit have the same upper limit output amount, and the upper limit output amount depends on the number of lanes at the output terminal of the FRC circuit. .
  • both the first FRC output signal and the second FRC output signal can be processed into a unified target format, assuming that the target resolution is S and the first target refresh frequency is F, Then the resolution of the first FRC output signal and the second FRC output signal is S/2, and the refresh frequency of the first FRC output signal and the second FRC output signal is F.
  • the display needs to output a high resolution and high refresh rate signal of 8K ⁇ 4K@120Hz as an example, because the current FRC circuit is affected by its own hardware performance Limitation, if the format of the first FRC output signal is 8K ⁇ 4K@120Hz, the data volume of the first FRC output signal will exceed the upper limit output of the first FRC circuit, so a single FRC circuit cannot output 8K ⁇ 4K@120Hz In this case, since the signals output by the SOC circuit in Figure 24 and Figure 25 to the two FRC circuits are complete picture signals, the received SOC output signal can be output in the first FRC circuit and the second FRC circuit Separate the left and right pictures, make the first FRC circuit multiply the left picture frame in the SOC output signal, and make the second FRC circuit multiply the right picture frame in the SOC output signal, so The data volume output by a single FRC circuit will be halved, which is less than the upper limit output volume of the
  • the resolution of the first FRC output signal is halved to 4K ⁇ 4K, so the data volume corresponding to the 4K ⁇ 4K@120Hz signal output by the first FRC circuit is less than the upper limit output of the first FRC circuit, so that the first FRC output signal Smoothly transferred to the display.
  • the processing mode of the second FRC circuit is the same as that of the first FRC circuit.
  • the 4K ⁇ 4K@120Hz left picture output by the first FRC circuit and the 4K ⁇ 4K@120Hz right picture output by the second FRC circuit are integrated in the display screen. , And finally display a complete picture of 8K ⁇ 4K@120Hz on the display.
  • the SOC circuit correspondingly selects the format of the SOC circuit output signal to the two FRC circuits according to the resolution and refresh frequency of the video source signal, the upper limit input of the two FRC circuits, and, according to the two The upper limit output of the FRC circuit, the target resolution, and the first target refresh frequency are used to set the output signal format of the two FRC circuits to the display screen, so as to select the SOC output signal format to avoid signal loss.
  • the refresh frequency of the SOC output signal is greater than or equal to the refresh frequency of the video source signal, so as to avoid frame loss during signal processing, and can also adapt to the FRC circuit's requirements for signal data input and output.
  • the left picture frame and the right picture frame are respectively output and integrated in the display screen to display the completed video picture and make the video picture meet the target resolution and the first target refresh rate. Claim. It can be seen that the present application can not only realize the display of high-resolution and high-refresh frequency signals, but also prevent the problem of frame loss during the display of video signals, thereby improving the TV picture quality and display effect.
  • a first GPIO set A is preset in the first FRC circuit
  • a second GPIO set B is preset in the second FRC circuit.
  • the first GPIO set A and the second GPIO set B respectively include N GPIO.
  • N is equal to 2
  • the first GPIO set A includes 2 GPIOs, which are respectively denoted as GPIO-A1 and GPIO-A2
  • the second GPIO set B includes 2 GPIOs, denoted as GPIO-B1 and GPIO-B2 respectively. Then, the first GPIO set A and the second GPIO set B are used to perform synchronization processing on the left picture frame and the right picture frame.
  • the left side picture output by the first FRC circuit is synchronized with the right side picture output by the second FRC circuit.
  • the synchronization process is performed on the left side picture frame and the right side picture frame.
  • the second FRC circuit including:
  • the GPIO in the first GPIO set A is denoted as GPIO-A i
  • the value of X i is determined by the first FRC circuit Perform assignment (ie, write in the first FRC circuit in FIG. 27).
  • the value of X i in this embodiment is 0 or 1, thereby forming The state set (X N ,..., X 2 , X 1 ) of the first GPIO set A.
  • the state value of the first GPIO set A can be calculated as:
  • (b) Set the synchronization check value of the second FRC circuit in real time.
  • the number of state sets that can be set for the first GPIO set A is 2 N.
  • the first GPIO set A changes dynamically, and the state value of the first GPIO set A also changes dynamically.
  • the synchronization check value of the second FRC circuit should be less than or equal to the maximum value of the state value of the first GPIO set A.
  • the first FRC circuit can write the interface value for the GPIO-A i in the first GPIO set A by looping in the order of the state value from small to large.
  • the state set (X 2 , X 1 ) of the first GPIO set A can be (0, 0), (0, 1), (1, 0) and (1, 1). Then the state value corresponding to (0, 0) is 0, the state value corresponding to (0, 1) is 1, the state value corresponding to (1, 0) is 2, and the state value corresponding to (1, 1) is 3.
  • the synchronization processing of the left-side picture frame and the right-side picture frame for the first FRC circuit includes:
  • the GPIO in the second GPIO set B is denoted as GPIO-B j
  • the interface value of GPIO-B j is Y j
  • the value of Y j is determined by the second FRC circuit Perform the assignment (that is, write in the second FRC circuit in FIG. 27), in order to facilitate the calculation of the state value of the second GPIO set B according to the following formula
  • the value of Y j in this embodiment is 0 or 1, thereby forming The state set (Y N ,..., Y 2 , Y 1 ) of the second GPIO set B.
  • the state value of the second GPIO set B can be calculated as:
  • (g) Set the synchronization check value of the first FRC circuit in real time.
  • the number of state sets that can be set for the second GPIO set B is 2 N.
  • the second GPIO set B changes dynamically, and the state value of the second GPIO set B also changes dynamically.
  • the synchronization check value of the first FRC circuit should be less than or equal to the maximum value of the state value of the second GPIO set B.
  • the second FRC circuit can write the interface value for GPIO-B j in the second GPIO set B according to the cycle of the state value from small to large.
  • the state sets (Y 2 , Y 1 ) of the second GPIO set B can be (0, 0), (0, 1), (1, 0) and (1, 1). Then the state value corresponding to (0, 0) is 0, the state value corresponding to (0, 1) is 1, the state value corresponding to (1, 0) is 2, and the state value corresponding to (1, 1) is 3.
  • (j) Discard the n2 frame data in the right picture frame. If the synchronization check value of the first FRC circuit is less than the state value of the second GPIO set B, it means that the left screen output by the first FRC circuit is not synchronized with the right screen output by the second FRC circuit, and the right screen will be more than the left If the screen plays more than n2 frames, the corresponding n2 frames are discarded, so that the left screen and the right screen are adjusted and synchronized, and then the first FRC circuit and the second FRC circuit send the data to the display screen to display the synchronized left and right sides. Picture.
  • Steps (a) to (j) are based on the GPIO state set method, so that the first FRC circuit and the second FRC circuit are mutually verified to adjust the synchronization of the left and right screens, so that the display screen
  • the screen can realize 8K ⁇ 4K@120Hz signal screen without dropping frame display under the state of picture synchronization, thereby improving the picture display effect and picture quality of the smart TV.
  • the present application also provides another embodiment of a display device, including an SOC circuit 200, a first FRC circuit 300, a second FRC circuit 400, and a display screen 500.
  • the SOC circuit 200 includes a video receiver 200-1
  • the video receiver 200-1 can be connected to the signal device 100, and the video receiver 200-1 is configured to receive the video source signal generated by the signal device 100;
  • the SOC circuit 200 also includes a controller 200-2, and the controller 200-2 is It is configured to determine the SOC output signal according to the resolution and refresh frequency of the video source signal, and according to the upper limit input amount of the first FRC circuit and the upper limit input amount of the second FRC circuit; wherein, the upper limit The input amount is the maximum amount of data allowed to be input;
  • the controller 200-2 can be connected to the first FRC circuit 300 and the second FRC circuit 400, respectively, for inputting the SOC to the first FRC circuit 300 and the second FRC circuit 400, respectively output signal;
  • the first FRC circuit 300 is configured to perform frequency multiplication processing on the SOC output signal to obtain a first FRC output signal, where the first FRC output signal corresponds to the left picture frame;
  • the second FRC circuit 400 is configured to perform frequency multiplication processing on the SOC output signal to obtain a second FRC output signal, where the second FRC output signal corresponds to the right frame;
  • the display screen 500 is configured to receive the left picture frame and the right picture frame, and display an integrated image of the left picture frame and the right picture frame;
  • the refresh frequency of the first FRC output signal and the second FRC output signal is equal to the preset refresh frequency of the display screen output signal.
  • the display device provided in this embodiment adopts the frequency multiplication process performed by two FRC circuits, and the integration of the left-side picture frame and the right-side picture frame by the display screen (the discrimination between the first FRC output signal and the second FRC output signal) Rate can be superimposed), so that the display screen can display video images that meet the preset resolution and refresh rate.
  • the preset resolution and refresh rate are set according to the expected high resolution and high refresh rate in the actual application.
  • the SOC output signal can be set more flexibly
  • the format can make the SOC circuit output a signal to avoid signal loss of frame.
  • the number of lanes that the first FRC circuit 300 and the second FRC circuit 400 can support signal input is not limited to 16 lanes;
  • the display screen 500 may be a smart TV, an outdoor display screen, a liquid crystal display screen, a computer display screen, or a projection screen. Display screen or other device with video image display function.
  • the SOC circuit 200, the first FRC circuit 300, and the second FRC circuit 400 in the display device can also be configured to execute other related program steps in the foregoing method embodiments, and the various embodiments in this specification are the same. Similar parts can be referred to each other.
  • the main control circuit is the SOC circuit
  • the first processing circuit is the first FRC circuit
  • the second processing circuit is the second FRC circuit
  • the screen is the display screen.

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Abstract

本申请实施例示出一种显示设备及图像输出方法。其中，第一处理电路和第二处理电路分别将主控电路输出的第一信号，放大倍频得到第二信号，在后续过程中第一处理电路和第二处理电路对第二信号进行不同的处理，得到第一半帧信号和第二半帧信号，并分别发送到屏幕，此方案不会出现颗粒度明显、片源卡顿，以及画面占据部分屏幕的问题。

Description

一种显示设备及图像输出方法
本专利申请要求于2019年9月6日提交的、申请号为201910842641.4；于2019年9月6日提交的、申请号为201910842638.2的中国专利申请的优先权，该申请的全文以引用的方式并入本文中。
技术领域
本申请涉及显示技术领域，特别涉及一种显示设备及图像输出方法。
背景技术
随着显示技术的迅速发展，8k屏幕已推出市场，8k屏幕可以显示分辨率为8k*4k(7680*4320)、刷新频率为120HZ的视频信号。但是分辨率为7680*4320、刷新频率为120HZ的8k片源相对匮乏，目前提供给屏幕显示的视频信号，多数为分辨率3840*2160，刷新频率60HZ的视频信号，以及更低分辨率和刷新频率的低质量视频信号。
相关技术中的显示设备，如图1所示，包括主控电路1和屏幕2。由于技术限制，主控电路1可以将低质量视频信号，转换为分辨率为3840*2160、刷新频率为60HZ的视频信号，虽然可以将低质量视频信号的分辨率和刷新频率提高，但是主控电路输出的视频信号传输到8K屏幕上显示时，会发现视频信号只会占据8k屏幕的四分之一，具体见图2，另外在8k屏幕上显示时存在颗粒度明显以及片源卡顿的问题，无法充分使用户享受到观看8k屏幕的极致体验。
申请内容
基于上述技术问题，本申请的申请目的在于提供一种显示设备显示设备及图像输出方法。
本申请实施例示出一种显示设备，
包括主控电路、第一处理电路、第二处理电路、屏幕和I2C线；所述第一处理电路和第二处理电路并联连接在所述主控电路和屏幕之间，所述主控电路还通过I2C线与所述第一处理电路连接；
所述主控电路，用于确定第一信号和第一输出模式，发送第一信号到第一处理电路和第二处理电路，以及，通过I2C线发送所述第一输出模式到第一处理电路；
所述第一处理电路，用于根据第一输出模式，处理第一信号，得到第一半 帧信号，并发送到屏幕，以及，用于根据第一输出模式，确定第二半帧信号的方向，并通知第二处理电路所述第二半帧信号的方向；
所述第二处理电路，用于根据第二半帧信号的方向，确定第二输出模式，处理第一信号，得到第二半帧信号，并发送到屏幕；
所述屏幕，用于显示第一半帧信号和第二半帧信号，其中，第一半帧信号和第二半帧信号组成一帧画面。
在一些实施例中，
所述第一处理电路包括：
第一信号处理电路，用于对第一信号执行放大操作和倍频操作，得到第二信号；
第一生成电路，用于根据第一输出模式，生成第二信号中每帧画面的第一半帧信号并确定第二半帧信号的方向；
第一发送电路，用于发送所述第一半帧信号到屏幕，以及，通知第二处理电路所述第二半帧信号的方向。
在一些实施例中，
所述第二处理电路包括：
第二信号处理电路，用于对第一信号执行放大操作和倍频操作，得到第二信号；
第二生成电路，用于根据所述第二半帧信号的方向，确定第二输出模式，生成第二信号中每帧画面的第二半帧信号；
第二发送电路，用于发送所述第二半帧信号到屏幕。
在一些实施例中，
所述第一信号处理电路包括：
放大电路，用于对第一信号执行放大操作，得到第四信号；
倍频电路，用于对所述第四信号执行倍频操作，生成第二信号。
结合第一方面的第一种可能的实现方式，在第一方面的第四种可能的实现方式中，所述第一生成电路包括，
第一确定电路，用于根据第一输出模式，确定第一半帧信号的方向；
第二确定电路，用于根据第一半帧信号的方向，确定第二半帧信号的方向；
第三生成电路，用于根据第一输出模式，生成第二信号中每帧画面的第一 半帧信号。
在一些实施例中，所述第一确定电路包括：
获取电路，用于获取屏幕的分辨率m3*n3；
所述第一输出模式包括输出坐标的横坐标x、纵坐标y、输出宽高的宽度w和高度h；
第一判断电路，用于判断x是否等于0，以及y是否等于0；
第二判断电路，用于如果x等于0，且y等于0，判断w是否等于1/2m3；
如果w等于1/2m3，则第一半帧信号的方向为左侧；
第三判断电路，用于如果w不等于1/2m3，则判断w是否等于m3；
如果w等于m3，则第一半帧信号的方向为上侧；
如果w不等于m3，则为异常，第一半帧信号的方向为默认方向；
第四判断电路，用于如果x不等于0，y等于0，判断x是否等于1/2m3，以及w是否等于1/2m3；
如果x等于1/2m3，且w等于1/2m3，则第一半帧信号的方向为右侧；
如果x不等于1/2m3，和/或w不等于1/2m3，则为异常，第一半帧信号的方向为默认方向；
第五判断电路，用于如果x等于0，y不等于0，判断y是否等于1/2n3，以及w是否等于m3；
如果y等于1/2n3，且w等于m3，则第一半帧信号的方向为下侧；
如果y不等于1/2n3，和/或w不等于m3，则为异常，第一半帧信号的方向为默认方向。
结合第一方面，在第一方面的第六种可能的实现方式中，所述主控电路包括：
获取电路，用于获取第三信号；
转化电路，用于根据预设格式，将第三信号转化为第一信号。
本申请实施例还示出一种图像输出方法，用于主控电路，所述方法包括：
确定第一信号，发送第一信号到第一处理电路和第二处理电路。
本申请实施例还示出一种图像输出方法，用于屏幕，所述方法包括：显示第一半帧信号和第二半帧信号，其中第一半帧信号和第二半帧信号组成一帧画面。
本申请实施例还示出一种图像输出方法，用于第一处理电路，所述方法包括：
根据第一输出模式，处理第一信号，得到第一半帧信号，并发送到屏幕，以及，用于根据第一输出模式，确定第二半帧信号的方向，并通知第二处理电路所述第二半帧信号的方向。
在一些实施例中，本申请提供一种显示设备，显示设备包括SOC电路、第一FRC电路、第二FRC电路和显示屏；所述SOC电路分别与所述第一FRC电路和所述第二FRC电路连接；
所述SOC电路，用于接收视频源信号，根据所述视频源信号的分辨率和刷新频率，以及根据所述第一FRC电路的上限输入量和所述第二FRC电路的上限输入量，确定SOC输出信号，并将所述SOC输出信号分别输入至所述第一FRC电路和所述第二FRC电路；其中，所述上限输入量为允许输入的最大数据量；
所述第一FRC电路，用于对所述SOC输出信号进行倍频处理，得到第一FRC输出信号，所述第一FRC输出信号对应于左侧画面帧；
所述第二FRC电路，用于对所述SOC输出信号进行倍频处理，得到第二FRC输出信号，所述第二FRC输出信号对应于右侧画面帧；
所述第一FRC电路，还用于将所述左侧画面帧按照所述第一FRC输出信号的分辨率和刷新频率输入至所述显示屏；
所述第二FRC电路，还用于将所述右侧画面帧按照所述第二FRC输出信号的分辨率和刷新频率输入至所述显示屏；
其中，所述第一FRC输出信号与所述第二FRC输出信号的分辨率之和等于目标分辨率，所述目标分辨率为预设的显示屏输出信号的分辨率；所述第一FRC输出信号和所述第二FRC输出信号的刷新频率等于第一目标刷新频率，所述第一目标刷新频率为预设的显示屏输出信号的刷新频率。
在一些实施例中，所述SOC电路还用于：
判断所述视频源信号的数据量是否超过所述第一FRC电路的上限输入量；
如果所述视频源信号的数据量未超过所述第一FRC电路的上限输入量，则判断所述视频源信号的分辨率是否等于所述目标分辨率；
如果所述视频源信号的分辨率等于所述目标分辨率，则使所述SOC输出信 号为所述视频源信号。
在一些实施例中，所述SOC电路还用于：
如果所述视频源信号的分辨率小于所述目标分辨率，则判断所述视频源信号的刷新频率是否小于或等于第二目标刷新频率；所述第二目标刷新频率为倍频处理前，所述SOC输出信号所能达到的最大刷新频率；
如果所述视频源信号的刷新频率小于或等于第二目标刷新频率，则使所述SOC输出信号的分辨率等于所述视频源信号的分辨率，所述SOC输出信号的刷新频率等于所述第二目标刷新频率。
在一些实施例中，所述SOC电路还用于：
如果所述视频源信号的数据量超过所述第一FRC电路的上限输入量，则判断所述视频源信号的分辨率是否等于所述目标分辨率；
如果所述视频源信号的分辨率等于所述目标分辨率，则使所述SOC输出信号的分辨率等于所述目标分辨率的一半，所述SOC输出信号的刷新频率等于第二目标刷新频率；其中，所述第二目标刷新频率为倍频处理前，所述SOC输出信号所能达到的最大刷新频率；
其中，输入至所述第一FRC电路的SOC输出信号对应于左侧画面帧，输入至所述第二FRC电路的SOC输出信号对应于右侧画面帧。
在一些实施例中，所述第一FRC电路还用于：判断如果所述第一FRC输出信号的分辨率等于所述目标分辨率，并且所述第一FRC输出信号的刷新频率等于所述第一目标刷新频率时，所述第一FRC输出信号的数据量是否超过所述第一FRC电路的上限输出量；如果所述第一FRC输出信号的数据量超过所述第一FRC电路的上限输出量，则对所述SOC输出信号中的左侧画面帧进行倍频处理；
所述第二FRC电路还用于：判断如果所述第二FRC输出信号的分辨率等于所述目标分辨率，并且所述第二FRC输出信号的刷新频率等于所述第一目标刷新频率时，所述第二FRC输出信号的数据量是否超过所述第二FRC电路的上限输出量；如果所述第二FRC输出信号的数据量超过所述第二FRC电路的上限输出量，则对所述SOC输出信号的右侧画面帧进行倍频处理；
其中，所述上限输出量为允许输出的最大数据量。
在一些实施例中，在第一FRC电路内预置第一通用I/O接口集合，在第二 FRC电路内预置第二通用I/O接口集合，第一通用I/O接口集合和第二通用I/O接口集合内分别包括N个通用I/O接口；
利用第一通用I/O接口集合和第二通用I/O接口集合，对所述左侧画面帧和所述右侧画面帧进行同步处理。
在一些实施例中，所述第二FRC电路还用于：
读取第一FRC电路为第一通用I/O接口集合中N个通用I/O接口实时写入的接口值，计算第一通用I/O接口集合的状态值；
实时设置第二FRC电路的同步校验值；
判断第二FRC电路的同步校验值是否小于第一通用I/O接口集合的状态值；
如果第二FRC电路的同步校验值小于第一通用I/O接口集合的状态值，则计算第二FRC电路的同步校验值与第一通用I/O接口集合的状态值之间的差值n1；
丢弃左侧画面帧中的n1帧数据。
在一些实施例中，所述第一FRC电路还用于：
读取第二FRC电路为第二通用I/O接口集合中N个通用I/O接口实时写入的接口值，计算第二通用I/O接口集合的状态值；
实时设置第一FRC电路的同步校验值；
判断第一FRC电路的同步校验值是否小于第二通用I/O接口集合的状态值；
如果第一FRC电路的同步校验值小于第二通用I/O接口集合的状态值，则计算第一FRC电路的同步校验值与第二通用I/O接口集合的状态值之间的差值n2；
丢弃右侧画面帧中的n2帧数据。
在一些实施例中，当N等于2时，以(0，0)、(0，1)、(1，0)和(1，1)的顺序进行循环，为第一通用I/O接口集合和第二通用I/O接口集合中2个通用I/O接口写入接口值；其中，(0，0)对应的状态值为0，(0，1)对应的状态值为1，(1，0)对应的状态值为2，(1，1)对应的状态值为3。
在一些实施例中本申请还提供另一种显示设备，包括SOC电路、显示屏、第一FRC电路和第二FRC电路，SOC电路包括视频接收器，所述视频接收器被配置为接收视频源信号；所述SOC电路还包括控制器，所述控制器被配置为：根据所述视频源信号的分辨率和刷新频率，以及根据所述第一FRC电路的上限 输入量和所述第二FRC电路的上限输入量，确定SOC输出信号；其中，所述上限输入量为允许输入的最大数据量；所述控制器分别与所述第一FRC电路和所述第二FRC电路连接；
所述第一FRC电路，用于对所述SOC输出信号进行倍频处理，得到第一FRC输出信号，所述第一FRC输出信号对应于左侧画面帧；
所述第二FRC电路，用于对所述SOC输出信号进行倍频处理，得到第二FRC输出信号，所述第二FRC输出信号对应于右侧画面帧；
所述显示屏，用于接收所述左侧画面帧和所述右侧画面帧，并显示所述左侧画面帧和所述右侧画面帧整合后的图像；
其中，所述第一FRC输出信号和所述第二FRC输出信号的刷新频率等于预设的显示屏输出信号的刷新频率。
在一些实施例中，本申请提供一种图像输出方法，用于如第一方面至第一方面第八种可能的实现方式中任一项所述的显示设备，所述方法包括：
SOC电路接收视频源信号，根据所述视频源信号的分辨率和刷新频率，以及根据所述第一FRC电路的上限输入量和所述第二FRC电路的上限输入量，确定SOC输出信号，并将所述SOC输出信号分别输入至所述第一FRC电路和所述第二FRC电路；其中，所述上限输入量为允许输入的最大数据量；
第一FRC电路对所述SOC输出信号进行倍频处理，得到第一FRC输出信号，所述第一FRC输出信号对应于左侧画面帧；
第二FRC电路对所述SOC输出信号进行倍频处理，得到第二FRC输出信号，所述第二FRC输出信号对应于右侧画面帧；
所述第一FRC电路将所述左侧画面帧按照所述第一FRC输出信号的分辨率和刷新频率输入至所述显示屏；
所述第二FRC电路将所述右侧画面帧按照所述第二FRC输出信号的分辨率和刷新频率输入至所述显示屏；
其中，所述第一FRC输出信号与所述第二FRC输出信号的分辨率之和等于目标分辨率，所述目标分辨率为预设的显示屏输出信号的分辨率；所述第一FRC输出信号和所述第二FRC输出信号的刷新频率等于第一目标刷新频率，所述第一目标刷新频率为预设的显示屏输出信号的刷新频率。
由以上技术方案可以看出，本申请实施例示出一种显示设备及图像输出方 法，所述显示设备包括：主控电路、第一处理电路、第二处理电路、屏幕和I2C线；所述第一处理电路和第二处理电路并联连接在所述主控电路和屏幕之间，所述主控电路还通过I2C线与所述第一处理电路连接；所述主控电路，用于确定第一信号和第一输出模式，发送第一信号到第一处理电路和第二处理电路，以及，通过I2C线发送所述第一输出模式到第一处理电路；所述第一处理电路，用于根据第一输出模式，处理第一信号，得到第一半帧信号，并发送到屏幕，以及，用于根据第一输出模式，确定第二半帧信号的方向，并通知第二处理电路所述第二半帧信号的方向；所述第二处理电路，用于根据第二半帧信号的方向，确定第二输出模式，处理第一信号，得到第二半帧信号，并发送到屏幕；所述屏幕，用于显示第一半帧信号和第二半帧信号，其中，第一半帧信号和第二半帧信号组成一帧画面。
本申请实施例示出的技术方案中，第一处理电路和第二处理电路分别将主控电路输出的第一信号，放大倍频得到第二信号，在后续过程中第一处理电路和第二处理电路对第二信号进行不同的处理，得到第一半帧信号和第二半帧信号，并将第一半帧信号和第二半帧信号分别发送到屏幕，此时第一半帧信号和第二半帧信号在屏幕显示，不会出现颗粒度明显、片源卡顿，以及画面占据部分屏幕的问题。本申请在主控电路性能不完善的情况下，可以输出满足8k屏幕需求的视频信号。
本申请在SOC电路与显示屏之间，设置两个并行的FRC电路，第一FRC电路用于输出倍频处理后的右侧画面帧，第二FRC电路用于输出倍频处理后的右侧画面帧，从而提高屏幕输出信号的刷新频率。通过该显示设备的系统架构，使得SOC电路输出信号的格式不再局限于单一FRC电路的硬件性能，SOC电路能根据视频源信号的分辨率和刷新频率，以及根据两个FRC电路的上限输入量，对应选择SOC电路向两个FRC电路输出的信号的分辨率和刷新频率，以选出避免信号失帧的SOC输出信号的格式，例如，使SOC输出信号的刷新频率大于或等于视频源信号的刷新频率，避免视频信号显示时产生的失帧问题，还可适应FRC电路对信号数据量输入、输出的要求。
并且，通过两个并行的FRC电路，将视频源信号后续划分为左侧画面帧和右侧画面帧分别处理，显示屏将左侧画面帧与右侧画面帧的分辨率整合，即可实现更高分辨率的显示，因此本申请可以实现高分辨率、高刷新频率信号的无 失帧显示，从而提高电视画质和展示效果。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中显示设备的结构示意图；
图2为分辨率为3840*2160、刷新频率为60HZ的视频信号在8k屏幕上的显示效果图；
图3为根据一可选实施例示出的显示设备的结构示意图；
图4为根据一可选实施例示出的显示设备的数据处理示意图；
图5为根据一可选实施例示出的主控电路的结构示意图；
图6为根据一可选实施例示出的第一处理电路的结构示意图；
图7为本申请实施例中的一帧画面的示意图；
图8为本申请实施例中的又一帧画面的示意图；
图9为本申请实施例中的补偿画面的示意图；
图10为根据一可选实施例示出的第一生成电路的结构示意图；
图11为分辨率为7680*4320的画面的坐标轴；
图12为根据一可选实施例示出的确定第一半帧信号的方向的示意图；
图13为根据一可选实施例示出的第一半帧信号的方向为左侧的画面示意图；
图14为根据一可选实施例示出的第一半帧信号的方向为上侧的画面示意图；
图15为根据一可选实施例示出的第一半帧信号的方向为右侧的画面示意图；
图16为根据一可选实施例示出的第一半帧信号的方向为下侧的画面示意图；
图17为根据一可选实施例示出的第二处理电路的结构示意图；
图18为根据一可选实施例示出的第一信号处理电路的结构示意图；
图19为根据一可选实施例示出的第二信号处理电路的结构示意图；
图20为相关技术显示设备实现高刷新频率时采用的系统架构示意图；
图21为本申请一实施例示出的一种显示设备的系统架构示意图；
图22为本申请又一实施例示出的一种图像输出方法流程图；
图23为本申请实施例示出的确定SOC输出信号的方法流程图；
图24为本申请实施例示出的视频源信号为8K×4K@30Hz时，显示设备架构中各环节信号处理示意图；
图25为本申请实施例示出的视频源信号小于或等于4K×2K@60Hz时，显示设备架构中各环节信号处理示意图；
图26为本申请实施例示出的视频源信号为8K×4K@60Hz时，显示设备架构中各环节信号处理示意图；
图27本申请实施例示出的第一FRC电路和第二FRC电路的GPIO示意图；
图28本申请实施例示出的第一FRC电路输出的左侧画面与第二FRC电路输出的右侧画面同步的原理示意图；
图29为本申请又一实施例提供的另一种显示设备的系统架构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为了解决相关技术存在的技术问题，本申请实施例示出一种显示设备，具体参阅图3，包括主控电路1、第一处理电路3、第二处理电路4、屏幕2和I2C线5；所述第一处理电路3和第二处理电路4并联连接在所述主控电路1和屏幕2之间，所述主控电路还通过I2C线与所述第一处理电路连接。
参阅图4，所述主控电路1，用于确定第一信号和第一输出模式，发送第一信号到第一处理电路3和第二处理电路4，以及，通过I2C线5发送所述第一输出模式到第一处理电路3；
在开机boot阶段，对第一处理电路3和第二处理电路4进行初始化，使第一处理电路3和第二处理电路4处于可接收视频信号的状态。完成第一处理电路3和第二处理电路4初始化后，通过I2C线5(Inter－Integrated Circuit，集成电路总线)，发送第一输出模式到第一处理电路3，第一处理电路3接收第一输出模式。
在一种可能的实现方式中，如图5所示，所述主控电路1包括：
获取电路11，用于获取第三信号；
转化电路12，用于根据预设格式，将第三信号转化为第一信号。
需要说明的是，所述第三信号为低质量视频信号。由于相关技术中，提供给屏幕显示的视频信号还包括低质量视频信号，所以本申请实施例首先将低质量视频信号全部转换为第一信号，随后将第一信号同时发送到第一处理电路3和第二处理电路4。所述预置格式通过系统开机boot阶段初始化设置。
在一些实施例中，所述第一信号的预置格式可以包括分辨率为3840*2160，刷新频率为60Hz，也可以包括分辨率为1920*1080，刷新频率为60HZ，或者第一信号的预设格式可以包括分辨率为7680*4320，刷新频率为60HZ。
针对8k的屏幕2，所述第一信号的预设格式设定为包括分辨率3840*2160，刷新频率为60Hz。所述低质量视频信号的分辨率可以为1920*1080，刷新频率可以为25HZ、30HZ或50HZ。
所述第一处理电路3，用于根据第一输出模式，处理第一信号，得到第一半帧信号，并发送到屏幕2，以及，用于根据第一输出模式，确定第二半帧信号的方向，并通知第二处理电路4所述第二半帧信号的方向；
所述第二处理电路4，用于根据第二半帧信号的方向，确定第二输出模式，处理第一信号，得到第二半帧信号，并发送到屏幕2；
本申请中，所述主控电路1可以为SOC芯片(System on Chip，片上系统)，所述第一处理电路3和第二处理电路4可以为FRC芯片(Frame Rate Conversion，帧速率转换)，所述屏幕2可以为液晶屏幕。当然，其他可以满足主控电路1、第一处理电路3、第二处理电路4和屏幕2功能的芯片或者显示器也可以作为本申请实施例的选择。
本申请中，所述主控电路1输出的第一信号不能满足屏幕2需要播放的视频信号的格式要求，所以本申请设置第一处理电路3和第二处理电路4，转化第一信号，得到既能满足第一处理电路3和第二处理电路4输出要求，又能满足使屏幕2显示完整画面的第一半帧信号和第二半帧信号。值得注意的是，由于第一半帧信号和第二半帧信号对应的画面需要同时在屏幕上显示，所以所述第一半帧信号和第二半帧信号需要同时发送到屏幕。
所述第一半帧信号和第二半帧信号是画面对立一侧的信号，第一半帧信号和第二半帧信号可以为任一形式的将画面分成像素个数相等的两份视频信号。第一半帧信号的方向可以为上侧、下侧、左侧和右侧，另外，如果将画面斜分，即输出第一半帧信号转化成的画面与第二半帧信号转化成的画面通过对角线结 合，得到第一半帧信号的方向为左上、左下、右上、右下，也是本申请实施例的实现方式。
由以上技术方案可知，在本申请实施例中，如果直接将主控电路输出的第一信号发送到屏幕2中显示，由于主控电路的技术限制，主控电路输出的第一信号的格式，达不到完全展示屏幕效果的格式需求。第一信号在屏幕上显示时，可能存在颗粒度明显、片源卡顿以及不能占满屏幕的问题。
本申请实施例中，第一处理电路3和第二处理电路4分别将主控电路1输出的第一信号，放大倍频得到第二信号，随后第一处理电路3和第二处理电路4再对第二信号进行不同的处理，最终使主控电路1输出的不满足格式需求的第一信号，转换为既能满足第一处理电路3和第二处理电路4输出要求，又能满足屏幕2显示完整画面的第一半帧信号和第二半帧信号。
在一种可能的实现方式中，如图6所示，所述第一处理电路3包括：
第一信号处理电路31，用于对第一信号执行放大操作和倍频操作，得到第二信号；
第一生成电路32，用于根据第一输出模式，生成第二信号中每帧画面的第一半帧信号并确定第二半帧信号的方向；
第一发送电路33，用于发送所述第一半帧信号到屏幕，以及，通知第二处理电路4所述第二半帧信号的方向。
本申请实施例中，采取先将第一信号执行倍频操作，再利用第一处理电路3和第二处理电路4将画面两侧分开发送的理由是：以倍频操作为运动估计补偿操作为例，运动估计补偿是根据帧信息之间的运动矢量去计算补偿的帧信息。如果为了降低第一处理电路3和第二处理电路4处理数据量，而采用先将画面分开，然后进行运动估计补偿，就可能出现当左侧画面和右侧画面的运动矢量相差较大。
如图7、8所示，图7和图8是相邻两帧画面的示意图，左侧画面的运动矢量几乎为0，在做运动估计补偿时，补偿的画面几乎与原始的两帧画面相同。而右侧画面的运动矢量较大，补偿的画面与原始的两帧画面都存在差异，合成的补偿画面参阅图9，图9中左侧画面和右侧画面结合处会因为对接不上，造成中间画面的断裂现象，出现对接不顺畅的现象，基于以上理由，本申请实施例采用先做运动估计补偿，然后利用第一处理电路3和第二处理电路4将画面两侧 分开，可以保证结合后的画面不会出现断裂现象。
本申请实施例中，所述倍频操作可以为运动估计补偿操作，但是不限制于运动估计补偿操作。
在一种可能的实现方式中，如图10所示，所述第一生成电路32包括，
第一确定电路321，用于根据第一输出模式，确定第一半帧信号的方向；
第二确定电路322，用于根据第一半帧信号的方向，确定第二半帧信号的方向；
第三生成电路323，用于根据第一输出模式，生成第二信号中每帧画面的第一半帧信号。
本申请实施例中，屏幕2上显示的画面通过第一半帧信号和第二半帧信号转化成的画面组成。第一半帧信号的方向和第二半帧信号的方向相反，当第一半帧信号的方向为左侧，第二半帧信号的方向为右侧；第一半帧信号的方向为上侧，第二半帧信号的方向为下侧。
在一种可能的实现方式中，所述第一输出模式可任意设定，本实施例按照画面有可能左侧和右侧分开，或者上侧和下侧分开，存在以上两种可能展开：本申请实施例中，第一输出模式包括输出坐标和输出宽高，所述输出坐标是指每帧画面的初始坐标，包括横坐标x和纵坐标y；输出宽高是指每帧画面的宽w和高h。所述输出坐标的坐标轴原点可以设置在画面的左上角。如图11所示，图11为分辨率为7680*4320的画面的坐标轴。图12为确定第一半帧信号的方向的示意图。
所述第一确定电路包括：
获取电路，用于获取屏幕的分辨率m 3*n 3；
所述第一输出模式包括输出坐标的横坐标x、纵坐标y、输出宽高的宽度w和高度h；
第一判断电路，用于判断x是否等于0，以及y是否等于0；
第二判断电路，用于如果x等于0，且y等于0，判断w是否等于1/2m 3；
如果w等于1/2m 3，则第一半帧信号的方向为左侧；
具体的，判断第一输出模式的输出坐标是否为(0,0)。当输出坐标为(0,0)，此时可能是第一半帧信号和第二半帧信号可能是按照左侧和右侧分开，也可能是按照上侧和下侧分开，进而继续判断输出宽高的宽度w是否等于1/2m 3，如 果w等于1/2m 3，则第一半帧信号的方向为左侧，此时，第二半帧信号的方向为右侧。
第三判断电路，用于如果w不等于1/2m 3，则判断w是否等于m 3；
如果w等于m 3，则第一半帧信号的方向为上侧；
如果w不等于m 3，此时，得到的结论是第一半帧信号的方向既不是左侧，又不是上侧，则存在异常，第一半帧信号的方向定义为默认方向，本实施例中默认方向可以为左侧。
第四判断电路，用于如果x不等于0，y等于0，判断x是否等于1/2m 3，以及w是否等于1/2m 3；
具体的，如果第一输出模式的输出坐标的x不等于0，y等于0，则第一半帧信号的方向可能为右侧，进而判断x是否等于1/2m 3，以及w是否等于1/2m 3；
如果x等于1/2m 3，且w等于1/2m 3，则第一半帧信号的方向为右侧；
如果x不等于1/2m 3，和/或w不等于1/2m 3，则为异常，第一半帧信号的方向为默认方向；
第五判断电路3216，用于如果x等于0，y不等于0，判断y是否等于1/2n 3，以及w是否等于m 3；
具体的，如果第一输出模式的输出坐标的横坐标x等于0，纵坐标不等于0，则第一半帧信号的方向可能为下侧，进而判断判断y是否等于1/2n 3，以及w是否等于m 3；
如果y等于1/2n 3，且w等于m 3，则第一半帧信号的方向为下侧；
如果y不等于1/2n 3，和/或w不等于m 3，则为异常，第一半帧信号的方向为默认方向。
举实例:如图13所示，第一输出模式的输出坐标为(0,0)，输出宽高(3840,4320)，屏幕分辨率为(7680,4320)，则第一半帧信号的方向为左侧。
如图14所示，第一输出模式的输出坐标为(0,0)，输出宽高(7680,2160)，屏幕分辨率为(7680,4320)，则第一半帧信号的方向为上侧。
如图15所示，第一输出模式的输出坐标为(3840,0)，输出宽高(3840,4320)，屏幕分辨率为(7680,4320)，则第一半帧信号的方向为右侧。
如图16所示，第一输出模式的输出坐标为(0,2160)，输出宽高(7680,2160)，屏幕分辨率为(7680,4320)，则第一半帧信号的方向为下侧。
画面斜分的方式也可以使第一输出模式和第二输出模式的处理数据减少。当加入存在画面斜分的方式时，确定第一半帧信号的方向的具体方法，只要没有背离本申请的精神和保护范围即可，再次不再赘述。
在一种可能的实现方式中，利用第一输出模式的高度h，确定第一半帧信号的方向。
所述第一确定电路321包括：
获取电路，用于获取屏幕的分辨率m 3*n 3；
第一判断电路，用于判断x是否等于0，以及y是否等于0；
第二判断电路，用于如果x等于0，且y等于0，判断h是否等于1/2n 3；
如果h等于1/2n 3，则第一半帧信号的方向为上侧；
如果h不等于1/2n 3，则判断h是否等于n 3；
如果h等于n 3，则第一半帧信号的方向为左侧；
如果h不等于n 3，则为异常，第一半帧信号的方向为默认方向；
如果x不等于0，y等于0，判断x是否等于1/2m 3，以及h是否等于n 3；
如果x等于1/2m 3，且h等于n 3，则第一半帧信号的方向为右侧；
如果x不等于1/2m 3，和/或h不等于n 3，则为异常，第一半帧信号的方向为默认方向；
如果x等于0，y不等于0，判断y是否等于1/2n 3，以及h是否等于1/2n 3；
如果y等于1/2n 3，且h等于1/2n 3，则第一半帧信号的方向为上侧；
如果y不等于1/2n 3，和/或h等于1/2n 3，则为异常，第一半帧信号的方向为默认方向。
在一种可能的实现方式中，如图17所示，所述第二处理电路4包括：
第二信号处理电路41，用于对第一信号执行放大操作和倍频操作，得到第二信号；
第二生成电路42，用于根据所述第二半帧信号的方向，确定第二输出模式，生成第二信号中每帧画面的第二半帧信号；
第二发送电路43，用于发送所述第二半帧信号到屏幕。
具体的，预先设置第二半帧信号的方向对应的第二输出模式。例如，可预先设置第二半帧信号的方向和对应的第二输出模式为：当屏幕分辨率为(7680,4320)，第二半帧信号的方向为右侧，第二输出模式包括输出坐标 (3840,0)，输出宽高的宽度为3840，输出宽高的高度为4320；第二半帧信号的方向为下侧，第二输出模式包括输出坐标(0,2160)，输出宽高的宽度为7680，输出宽高的高度为2160。
在一种可能的实现方式中，如图18所示，所述第一信号处理电路31包括：
第一放大电路311，用于对第一信号执行放大操作，得到第四信号；
第一倍频电路312，用于对所述第四信号执行倍频操作，生成第二信号。
在一种可能的实现方式中，如图19所示，所述第二信号处理电路41包括：
第二放大电路411，用于对第一信号执行放大操作，得到第四信号；
第二倍频电路412，用于对所述第四信号执行倍频操作，生成第二信号。
需要说明的是，在本申请实施例中需要将第一信号先做放大操作，随后进行倍频。因为如果先对第一信号倍频，再进行放大，将会加剧放大操作的运算量。
对第一信号执行放大操作，可以采用scaling up(放大)技术。Scaling up技术将第一信号按照一定比例放大成第四信号。例如，可以将分辨率为3840*2160的第一信号，放大为分辨率为7680*4320的第四信号。Scaling up技术仅改变第一信号的分辨率，对刷新频率没有影响。所述运动估计补偿，仅改变第四信号的刷新频率，对分辨率没有影响。
在一具体实例中，当第一信号的分辨率为3840*2160，刷新频率为60Hz时，对第一信号执行scaling up操作，得到的第四信号的分辨率为7680*4320，刷新频率为60HZ。对第四信号进行运动估计补偿，生成的第二信号的分辨率为7680*4320，刷新频率为120HZ。
需要说明的是，虽然第二信号已经满足8k屏幕2对视频信号的格式要求，例如，当第一信号的分辨率为3840*2160，刷新频率为60Hz，根据以上操作，可以得到第二信号的分辨率为7680*4320，刷新频率为120HZ，此时满足8k屏幕2对视频信号的格式要求，但是由于第一处理电路3和第二处理电路4不能输出7680*4320，刷新频率为120HZ的视频信号，即第一处理电路3和第二处理电路4本身的硬件限制，所以选择第一处理电路3和第二处理电路4并联设置，分别输出不同侧的半帧信号，减少输出数据量，这样，既能满足第一处理电路3和第二处理电路4输出要求，又能满足屏幕2显示完整画面的要求。
本申请中，可以采用多个处理电路，分别处理第一信号，每个处理电路得到部分视频信号，多个处理电路得到的部分视频信号组合成一帧画面。本申请实施例中，采用第一处理电路3和第二处理电路4并联，分别处理第一信号，得到第一半帧信号和第二半帧信号。
本申请实施例还示出一种图像输出方法，用于主控电路，所述方法包括：
确定第一信号和第一输出模式，发送第一信号到第一处理电路和第二处理电路，以及，通过I2C线发送所述第一输出模式到第一处理电路。
本申请实施例还示出一种图像输出方法，用于屏幕，所述方法包括：
显示第一半帧信号和第二半帧信号，其中第一半帧信号和第二半帧信号组成一帧画面。
本申请实施例还示出一种图像输出方法，用于第一处理电路，所述方法包括：
根据第一输出模式，处理第一信号，得到第一半帧信号，并发送到屏幕，以及，用于根据第一输出模式，确定第二半帧信号的方向，并通知第二处理电路所述第二半帧信号的方向。
由以上技术方案可知，本申请实施例示出一种显示设备及图像输出方法。本申请实施例示出的技术方案中，第一处理电路和第二处理电路分别将主控电路输出的第一信号，放大倍频得到第二信号，在后续过程中第一处理电路和第二处理电路对第二信号进行不同的处理，得到第一半帧信号和第二半帧信号，并将第一半帧信号和第二半帧信号分别发送到屏幕，此时第一半帧信号和第二半帧信号在屏幕显示，不会出现颗粒度明显、片源卡顿，以及画面占据部分屏幕的问题。本申请在主控电路性能不完善的情况下，可以输出满足8k屏幕需求的视频信号。
目前本领域致力于高分辨率、高刷新频率的画面显示，比如在显示设备上实现8K×4K@120Hz，8K×4K的分辨率可以使屏幕显示图像的像素更多，画面就更精细，屏幕显示区域内能显示的信息也就越多，120Hz刷新频率的电视是在现有60Hz的基础上采用智能倍频驱动技术，使屏幕扫描和液晶分子的翻转速度提高一倍，能有效消除残影，解决普通液晶屏运动画面拖尾问题，减少视觉疲劳，画质更健康。
信号设备输出的视频源信号进入SOC(System On Chip，片上系统)电 路进行处理后，SOC电路再输出固定格式的信号来驱动屏幕，对于高级别分辨率信号，比如8K级高分辨率信号目前最高只可支持8K×4K@60Hz的画面显示，如果要实现如8K×4K@120Hz的高分辨率、高刷新频率显示，如图1所示，需借助一个外置的FRC(Frame Rate Conversion，帧率转换)电路，将SOC电路输出的信号输入FRC电路，由FRC电路对信号进行倍频处理，再由FRC电路驱动8K×4K@120Hz屏幕。
以信号设备输出8K×4K@60Hz视频源信号，并实现8K×4K@120Hz的高分辨率、高刷新频率的画面显示为例，由于目前FRC电路存在硬件性能上的局限性，最高只可支持16lane数据量的输入，导致SOC电路向FRC电路输出信号的分辨率和刷新频率受到限制，一般固定为8K×4K@30Hz或者4K×4K@60Hz。如果SOC电路固定输出8K×4K@30Hz格式的信号给FRC电路，会存在信号失帧的问题；如果SOC电路固定输出4K×4K@60Hz的信号输出给FRC，虽然不会失帧，但却无法实现8K×4K分辨率的显示。因此如何实现高分辨率、高刷新频率视频信号的无失帧显示是本领域亟待解决的技术问题。
如图21所示，为本申请一实施例提供的一种显示设备示意图，该显示设备的系统架构中，包括信号设备100、SOC电路200、第一FRC电路300、第二FRC电路400和显示屏500；信号设备100用于生成视频源信号，信号设备100的输出端与SOC电路的输入端连接；SOC电路200用于接收视频源信号，解析视频源信号的分辨率和刷新频率，以及根据第一FRC电路300的上限输入量和第二FRC电路400的上限输入量，来确定SOC输出信号；
其中，所述上限输入量为允许输入的最大数据量，SOC电路200的输出端分别与第一FRC电路300和第二FRC电路400的输入端连接，以将SOC输出信号分别输入至第一FRC电路和第二FRC电路；第一FRC电路300与第二FRC电路400并行处理，第一FRC电路300对左侧画面帧进行倍频处理，得到第一FRC输出信号，第二FRC电路400对右侧画面帧进行倍频处理，得到第二FRC输出信号；
第一FRC电路用于将左侧画面帧按照第一FRC输出信号的分辨率和刷新频率输入至显示屏，第二FRC电路用于将右侧画面帧按照第二FRC输出信号的分辨率和刷新频率输入至所述显示屏，两个FRC电路分别接收SOC输出信号，同时且独立地对SOC输出信号进行倍频处理，使第一FRC输出信号和第 二FRC输出信号的刷新频率等于第一目标刷新频率，第一目标刷新频率为预设的显示屏输出信号的刷新频率，第一目标刷新频率用于表示期望显示屏输出信号的刷新频率，比如120Hz的高刷新频率。
同时根据期望显示屏输出信号的分辨率，可以预先设置目标分辨率，调节两个FRC电路输出信号的分辨率，使第一FRC输出信号与第二FRC输出信号的分辨率之和等于目标分辨率，所述目标分辨率为预设的显示屏输出信号的分辨率，例如，使第一FRC输出信号和第二FRC输出信号的分辨率等于目标分辨率的一半，比如目标分辨率为8K×4K时，则使两个FRC电路分别输出信号的分辨率为4K×4K，这样显示屏整合左侧画面帧和右侧画面帧后，即可显示8K×4K分辨率，第一FRC电路300和第二FRC电路400的输出端分别与显示屏连接；显示屏对第一FRC电路300和第二FRC电路400的输出信号进行处理，从而整合并同步显示左侧画面和右侧画面，使显示屏输出达到目标分辨率和第一目标刷新频率的要求，并且实现视频信号的无失帧显示。
第一FRC电路300和第二FRC电路400中分别设置有多条lane，lane可以理解为数据传输通道，lane数量越多，单位时间内输入两个FRC电路中的数据量就越多，因此lane数量用于表征FRC电路可支持传输的数据量大小，例如8lane最高可支持输入分辨率为3840×2160(即4K×2K)，刷新频率为60Hz的信号，而16lane可传输数据是8lane的两倍。在硬件性能上，本实施例中的第一FRC电路300和第二FRC电路400均可以支持16lane数据量的输入，两个并行FRC电路支持32lane信号的输出，从而使显示屏能显示更高分辨率和更高的刷新频率，在实际应用中，FRC电路的lane数量不限于本实施例所述。
SOC电路200还可与第一FRC电路300或第二FRC电路400通过I2C(Inter－Integrated Circuit，集成电路总线)进行连接，比如图21中，SOC电路200是与第一FRC电路300通过I2C连接，SOC电路200通过I2C指示第一FRC电路300是处理左侧画面帧或是右侧画面帧，如果SOC电路200通过I2C指示第一FRC电路300处理左侧画面帧，则第二FRC电路400处理右侧画面帧。下面将具体说明如何基于该显示设备的系统架构实现高分辨率、高刷新频率视频信号的无失帧显示。需要说明的是，本实施例中提到的格式是指信号的分辨率和刷新频率，比如8K×4K@60Hz这种格式即是指信号的分辨率为8K×4K，刷新频率为60Hz。
本实施例中，分辨率是屏幕图像的精密度，是指显示屏所能显示的像素有多少，由于屏幕上的点、线和面都是由像素组成，显示屏可显示的像素越多，画面就越精细，屏幕区域内能显示的信息也越多，比如8K×4K分辨率为7680×4320，约每帧3300万像素图像。刷新频率是指屏幕每秒钟画面被刷新的次数，也就是每秒能显示多少幅图像，刷新频率的单位是赫兹(Hz)，普通液晶电视60Hz的刷新频率在显示运动画面时会出现彗星拖尾的现象，更适合看静态画面，原因就在于液晶分子的保持型显示以及人眼视觉暂留特性，120Hz刷新频率的液晶电视采用智能倍速驱动技术，使屏幕扫描和液晶分子的翻转速度提高一倍，实现屏幕刷新频率从60Hz到120Hz的飞跃，有效消除残影，解决普通液晶屏运动画面拖尾问题，减少视觉疲劳，画质更健康。
如图22所示，本申请又一实施例提供一种图像输出方法，用于如上所述的显示设备，所述方法包括如下步骤：
步骤S10，SOC电路接收视频源信号，根据所述视频源信号的分辨率和刷新频率，以及根据所述第一FRC电路的上限输入量和所述第二FRC电路的上限输入量，确定SOC输出信号，并将所述SOC输出信号分别输入至所述第一FRC电路和所述第二FRC电路。
在一些实施例中，所述SOC输出信号的刷新频率大于或等于所述视频源信号的刷新频率。所述上限输入量为允许输入的最大数据量；
在一些实施例中，所述第二FRC电路和所述第一FRC电路具有相同的上限输入量，上限输入量取决于FRC电路输入端的lane数量。
视频源信号可以通过信号设备100生成的，信号设备100生成的视频源信号输入SOC电路200后，SOC电路200可以检测视频源信号是否稳定，如果是稳定的视频源信号，则SOC电路200可以从信号解析端获取视频源信号的分辨率及刷新频率；如果不是稳定的视频源信号，则不对视频源信号进行处理和显示。视频源信号中包括画面帧数据和时钟，SOC电路在接收视频源信号时，会检测视频源信号的时钟信息，例如当检测到时钟信息为1时，会自动控制显示设备中某个特定的寄存器置位，这样SOC电路中配置的软件程序在读取该寄存器时，如果该寄存器处于置位状态，则认为视频源信号是稳定的；如果该寄存器未被置位，则认为视频源信号是不稳定的。需要说明的是，判定视频源信号是否稳定的方法不限于本实施例所述。
在一些实施例中，在步骤S10中，如图23所示，本实施例中示出三种确定SOC输出信号的方式，第一种方式为步骤S101～步骤S103，第二种方式为S101、步骤S102、步骤S104和步骤S105，第三种方式为步骤S101、步骤S102和步骤S106。
其中，第一种确定SOC输出信号的方式具体为：
步骤S101，判断视频源信号的数据量是否超过第一FRC电路的上限输入量。通过视频源信号的分辨率和刷新频率，可以确定视频源信号的数据量，根据第一FRC电路的lane数量可以确定上限输入量。
如果视频源信号的数据量未超过第一FRC电路的上限输入量，则在步骤S102中，判断视频源信号的分辨率是否等于标分辨率。
如果视频源信号的分辨率等于目标分辨率，则在步骤S103中，使所述SOC输出信号为所述视频源信号。
与第一种确定SOC输出信号的方式对应地，如图24所示，图24是以视频源信号为8K×4K@30Hz，所述目标分辨率8K×4K，所述第一目标刷新频率为120Hz，即需要显示器输出8K×4K@120Hz的高分辨率、高刷新频率信号为例，在第一FRC电路和第二FRC电路都支持16lane数据量的输入时，视频源信号8K×4K@30Hz对应的数据量未超过第一FRC电路的上限输入量，这种情况下，视频源信号的分辨率与目标分辨率相等，都为8K×4K，因此，直接使SOC输出信号为视频源信号，即SOC输出信号的分辨率为8K×4K，SOC输出信号的刷新频率为30Hz，即SOC电路向第一FRC电路输出信号的格式为8K×4K@30Hz，对应信号lane0～15；SOC电路向第二FRC电路输出信号的格式同样为8K×4K@30Hz，对应信号lane16～31。
第二种确定SOC输出信号的方式具体为：
步骤S101，判断视频源信号的数据量是否超过第一FRC电路的上限输入量。通过视频源信号的分辨率和刷新频率，可以确定视频源信号的数据量，根据第一FRC电路的lane数量可以确定上限输入量。
如果视频源信号的数据量未超过第一FRC电路的上限输入量，则在步骤S102中，判断视频源信号的分辨率是否等于目标分辨率。
如果所述视频源信号的分辨率小于所述目标分辨率，则在步骤S104中，判断视频源信号的刷新频率是否小于或等于第二目标刷新频率；所述第二目标刷 新频率为倍频处理前，所述SOC输出信号所能达到的最大刷新频率，第二目标刷新频率一般为60Hz。
如果视频源信号的刷新频率小于或等于第二目标刷新频率，则在步骤S105中，使所述SOC输出信号的分辨率等于所述视频源信号的分辨率，所述SOC输出信号的刷新频率等于所述第二目标刷新频率。
与第二种确定SOC输出信号的方式对应地，如图25所示，图25是以视频源信号为4K×2K@小于或等于60Hz，所述目标分辨率8K×4K，所述第一目标刷新频率为120Hz，即需要显示器输出8K×4K@120Hz的高分辨率、高刷新频率信号为例。在第一FRC电路和第二FRC电路都支持16lane数据量的输入时，视频源信号分辨率为4K×2K(电视信号设备默认的输出信号)，并且视频源信号的刷新频率小于或等于60Hz(第二目标刷新频率)，比如视频源信号为4K×2K@25Hz或者4K×2K@30Hz，视频源信号对应的数据量很显然不会超过第一FRC电路的上限输入量。
这种情况下，使SOC输出信号的分辨率等于视频源信号的分辨率，SOC输出信号的刷新频率等于第二目标刷新频率，即SOC电路向第一FRC电路输出信号的格式为4K×2K@60Hz，对应信号lane0～7；SOC电路向第二FRC电路输出信号的格式同样为4K×2K@60Hz，对应信号lane16～23。这种方式下，对于低于8K级高分辨率的视频源信号，SOC电路输出信号的刷新频率始终为60Hz，SOC电路输出信号的刷新频率大于或等于视频源信号的刷新频率。
第三种确定SOC输出信号的方式具体为：
步骤S101，判断视频源信号的数据量是否超过第一FRC电路的上限输入量。通过视频源信号的分辨率和刷新频率，可以确定视频源信号的数据量，根据第一FRC电路的lane数量可以确定上限输入量。
如果视频源信号的数据量超过第一FRC电路的上限输入量，则在步骤S102中，判断视频源信号的分辨率是否等于目标分辨率。
如果视频源信号的分辨率等于目标分辨率，则在步骤S106中，使所述SOC输出信号的分辨率等于所述目标分辨率的一半，所述SOC输出信号的刷新频率等于第二目标刷新频率。其中，所述第二目标刷新频率为倍频处理前，所述SOC输出信号所能达到的最大刷新频率，第二目标刷新频率一般为60Hz。
与第二种确定SOC输出信号的方式对应地，如图26所示，图26是以视频 源信号为8K×4K@60Hz，所述目标分辨率8K×4K，所述第一目标刷新频率为120Hz，即需要显示器输出8K×4K@120Hz的高分辨率、高刷新频率信号为例。
在第一FRC电路和第二FRC电路都支持16lane数据量的输入时，视频源信号8K×4K@60Hz对应的数据量会超过第一FRC电路的上限输入量，并且视频源信号的分辨率与目标分辨率相等，都为8K×4K，这种情况下，使SOC输出信号的刷新频率保持在60Hz，并在SOC电路中将视频源信号划分为左侧画面帧和右侧画面帧，由于在SOC电路中对视频源信号进行了左、右侧画面帧的分离，输入至第一FRC电路的SOC输出信号对应于左侧画面帧，所以与左侧画面帧对应的SOC输出信号的分辨率减小为视频源信号分辨率的一半，即4K×4K；输入至第二FRC电路的SOC输出信号对应于右侧画面帧，所以与右侧画面帧对应的SOC输出信号的分辨率减小为视频源信号分辨率的一半，即4K×4K。
即SOC电路向第一FRC电路输出信号的格式为4K×4K@60Hz，对应信号lane0～15；SOC电路向第二FRC电路输出信号的格式为4K×4K@60Hz，对应信号lane16～31。
对于第三种确定SOC输出信号的方式，由于在SOC电路中已经将视频源信号划分为左侧画面帧和右侧画面帧，所以第一FRC电路是直接对左侧画面帧的信号进行倍频处理，将左侧画面帧按照第一FRC输出信号的分辨率和刷新频率输入至显示屏；第二FRC电路是直接对右侧画面帧的信号进行倍频处理，将右侧画面帧按照第二FRC输出信号的分辨率和刷新频率输入至所述显示屏。显示屏将第一FRC电路和第二FRC电路输出的信号进行整合，从而显示匹配目标分辨率和第一目标刷新频率的完整画面。
本实施例不限于图24～图26提供的示例，在实际应用中，可以根据视频源信号的分辨率和刷新频率、两个FRC电路的上限输入量，灵活设定SOC电路向两个FRC电路输出的信号格式，以及，根据两个FRC电路的上限输出量、所述目标分辨率和所述第一目标刷新频率，来设定两个FRC电路向显示屏输出信号的格式，最终使显示屏显示匹配目标分辨率和第一目标刷新频率的完整画面，实现高分辨率、高刷新频率视频信号的无失帧显示。
本实施例中，视频源信号的刷新频率可以不限于30Hz、60Hz，还可以是25Hz、50Hz以及120Hz等，而需要显示器达到的高刷新频率可以是大于或等 于120Hz；视频源信号的分辨率不限于4K×2K和8K×4K，并且需要显示器达到的高分辨率也不限于8K×4K，还可以是更高级别的分辨率。
图20中的系统结构中，如需显示设备显示高分辨率、高刷新频率的信号时，比如8K×4K@120Hz，由于受单独一个FRC电路硬件性能的限制，例如FRC支持16lane信号的输入，SOC电路的输出信号一般具有两种固定格式，以适应FRC信号的输入，一种是将刷新频率减半，即SOC电路输出8K×4K@30Hz，但刷新频率减半会导致信号传输时产生失帧问题；另一种是将分辨率减半，即SOC电路输出4K×4K@60Hz，这种方式将导致FRC输出信号的分辨率无法达到8K级别，也就无法显示高分辨率信号。
对此，本申请中，第一FRC电路输出左侧画面帧，第二FRC电路输出右侧画面帧，两个FRC电路输出信号整合后达到所需的分辨率和刷新频率要求，即可驱动显示屏，由于采用两个FRC电路并行处理，所以对单独一个FRC电路硬件性能的限制和要求降低，基于视频源信号的刷新频率、分辨率和FRC电路支持输入的lane数量，可以使SOC电路输出信号的刷新频率大于或等于视频源信号的刷新频率，这样信号的传输过程中不会因刷新频率的降低而失帧，并且两个FRC电路输出信号的分辨率整合，还能保证显示屏显示的分辨率达到要求，从而实现高分辨率、高刷新频率信号的无失帧显示。
例如，当视频源信号为8K×4K@60Hz，并且需要屏幕输出8K×4K@120Hz时，使SOC电路向两个FRC电路分别输出信号的格式为4K×4K@60Hz，4K×4K@60Hz可以满足单独一个FRC电路数据量输入水平的要求，4K×4K@60Hz经过FRC电路进行倍频处理后，FRC电路输出为4K×4K@120Hz，即刷新频率从60Hz提升至120Hz高刷新频率，两个FRC电路每个输出信号的分辨率都是4K×4K，左侧画面的4K×4K和右侧画面的4K×4K整合后，即可将屏幕显示的分辨率转换为8K×4K，从而实现了8K×4K@120Hz的显示，并且信号处理和传输过程中，SOC电路输出信号的刷新频率等于视频源信号的刷新频率(即60Hz)，因此不存在信号失帧的问题。
需要说明的是，本实施例是以显示屏需要实现8K×4K@120Hz的目标显示效果为例，显示设备架构中各环节信号处理模式不限于图21、图24～图26所列举的示例，在图20所示显示设备的基础上，可根据架构中各电路、元件和设备的处理性能，视频源信号的分辨率和刷新频率，以及显示屏所要实现的目标 显示效果等因素，来配置不同视频源信号所对应的SOC电路输出信号的格式，以及两个FRC电路输出信号的格式。
步骤S20，第一FRC电路对对所述SOC输出信号进行倍频处理，得到第一FRC输出信号，所述第一FRC输出信号对应于左侧画面帧。
步骤S30，第二FRC电路对所述SOC输出信号进行倍频处理，得到第二FRC输出信号，所述第二FRC输出信号对应于右侧画面帧。步骤S20和步骤S30同时执行。所述SOC输出信号进行处理，得到第二FRC输出信号。步骤S20和步骤S30同时执行。
步骤S40，第一FRC电路将所述左侧画面帧按照所述第一FRC输出信号的分辨率和刷新频率输入至所述显示屏。
步骤S50，第二FRC电路将所述右侧画面帧按照所述第二FRC输出信号的分辨率和刷新频率输入至所述显示屏。步骤S40和步骤S50同时执行。
对于第一FRC电路和第二FRC电路，可以通过MEMC(Motion Estimate and Motion Compensation，运动估计和运动补偿)对SOC输出信号进行处理，这是一种液晶电视中用到的运动画质补偿技术，原理是采用动态映像系统，根据帧信息之间的运动矢量去计算补偿的帧信息，并在传统的两帧图像之间加插一帧运动补偿帧，比如假设原来的运动画面的帧序列是“1、2、3、4、5、6”，刷新频率为60Hz，则采用MEMC插入运动补偿帧后，帧序列变为“1、1C、2、2C、3、3C、4、4C、5、5C、6”，这样原来60Hz刷新频率就不足以显示补偿后帧序列中所有的帧，所以就会适应地将刷新频率提升一倍，即从60Hz提高至120Hz，从而实现倍频效果。
采用MEMC可以增加单位时间内显示的帧数，人眼接收图像帧的间隔缩短，减少了显示图像在视网膜的停留时间，所以可以降低拖尾现象，使得运动图像更加清晰，提高画面的显示效果，同时还能实现倍频，提高显示器输出画面的刷新频率。需要说明的是，第一FRC电路和第二FRC电路进行倍频处理的方式不限于MEMC。
图26中示出的是在SOC电路中对视频源信号进行左、右侧画面的分离处理，第一FRC电路接收到的直接就是左侧画面帧对应的信号，第二FRC电路接收到的直接就是右侧画面帧对应的信号，这样输入FRC电路的数据量减半。而图24和图25中SOC电路向两个FRC电路输出的信号是完整的画面信号， 由于FRC电路允许输出的最大数据量也受到lane数量的制约，因此，单独的FRC可能无法输出满足目标分辨率和第一目标刷新频率信号对应的数据量。
比如，对于图24的示例，SOC输出信号的格式为8K×4K@30Hz，第一FRC电路进行倍频处理，将刷新频率由30Hz提升至120Hz，如果第一FRC输出信号的分辨率保持8K×4K不变，则由于FRC电路受输出数据量能力的限制，第一FRC电路无法输出8K×4K@120Hz的信号。
对此，在本实施例其他可能的实现方案中，所述第一FRC电路还用于：判断如果所述第一FRC输出信号的分辨率等于所述目标分辨率，并且所述第一FRC输出信号的刷新频率等于第一目标刷新频率时，所述第一FRC输出信号的数据量是否超过所述第一FRC电路的上限输出量；如果所述第一FRC输出信号的数据量超过所述第一FRC电路的上限输出量，则对所述SOC输出信号中的左侧画面帧进行倍频处理；
所述第二FRC电路还用于：判断如果所述第二FRC输出信号的分辨率等于所述目标分辨率，并且所述第二FRC输出信号的刷新频率等于所述第一目标刷新频率时，所述第二FRC输出信号的数据量是否超过所述第二FRC电路的上限输出量；如果所述第二FRC输出信号的数据量超过所述第二FRC电路的上限输出量，则对所述SOC输出信号的右侧画面帧进行倍频处理；
其中，所述上限输出量为允许输出的最大数据量，例如，所述第二FRC电路和所述第一FRC电路具有相同的上限输出量，所述上限输出量取决于FRC电路输出端的lane数量。
在一些实施例中，对于不同的视频源信号，所述第一FRC输出信号和第二FRC输出信号都可处理为统一的目标格式，假设目标分辨率为S，第一目标刷新频率为F，则第一FRC输出信号和第二FRC输出信号的分辨率为S/2，第一FRC输出信号和第二FRC输出信号的刷新频率为F。
以所述目标分辨率8K×4K，所述第一目标刷新频率为120Hz，即需要显示器输出8K×4K@120Hz的高分辨率、高刷新频率信号为例，由于目前FRC电路受自身硬件性能的限制，如果第一FRC输出信号的格式为8K×4K@120Hz，则第一FRC输出信号的数据量会超过第一FRC电路的上限输出量，所以单独一个FRC电路无法输出8K×4K@120Hz的信号，这种情况下，由于图24和图25中SOC电路向两个FRC电路输出的信号是完整的画面信号，所以可以在第 一FRC电路和第二FRC电路中将接收到的SOC输出信号进行左、右侧画面的分离，使第一FRC电路对SOC输出信号中的左侧画面帧进行倍频处理，使第二FRC电路对SOC输出信号中的右侧画面帧进行倍频处理，这样单独一个FRC电路输出的数据量就会减半，小于第一FRC电路的上限输出量，所以可以使第一FRC输出信号的刷新频率为倍频处理后的120Hz。
即第一FRC输出信号的分辨率减半，变为4K×4K，这样第一FRC电路输出4K×4K@120Hz信号对应的数据量小于第一FRC电路的上限输出量，使得第一FRC输出信号顺利传输给显示屏。第二FRC电路的处理模式与第一FRC电路相同，第一FRC电路输出的4K×4K@120Hz左侧画面与第二FRC电路输出的4K×4K@120Hz右侧画面，在显示屏中进行整合，最终在显示屏上显示8K×4K@120Hz的完整画面。
通过图21所示的显示设备，SOC电路根据视频源信号的分辨率和刷新频率、两个FRC电路的上限输入量，对应选择SOC电路向两个FRC电路输出信号的格式，以及，根据两个FRC电路的上限输出量、所述目标分辨率和所述第一目标刷新频率，来设定两个FRC电路向显示屏输出信号的格式，以选出避免信号失帧的SOC输出信号的格式。
例如，使SOC输出信号的刷新频率大于或等于视频源信号的刷新频率，从而避免信号处理过程中产生的失帧问题，还可适应FRC电路对信号数据量输入、输出的要求。通过两个并行的FRC电路，分别输出左侧画面帧和右侧画面帧，并在显示屏中进行整合，从而显示完成的视频画面，并且使视频画面满足目标分辨率和第一目标刷新频率的要求。可见，本申请不仅可以实现高分辨率、高刷新频率信号的显示，还能防止视频信号显示过程中出现失帧问题，从而提高电视画质和展示效果。
在本申请中，采用两个并行的FRC电路架构，分别输出左侧画面帧和右侧画面帧，由于120Hz刷新频率使得数据更新更快，为保证屏幕画面展示效果，需要保证第一FRC电路输出的左侧画面帧与第二FRC电路输出的右侧画面帧保持同步，对此本申请采用GPIO(General-purpose input/output，通用输入/输出(I/O)接口)状态集的方式，与其他通信方式相比，GPIO的状态反馈快。
如图27所示，在第一FRC电路内预置第一GPIO集合A，在第二FRC电路内预置第二GPIO集合B，第一GPIO集合A和第二GPIO集合B内分别包 括N个GPIO。图26中，为提高同步校验和同步调节的效率，降低计算的复杂度，可选地，N等于2，即第一GPIO集合A包括2个GPIO，分别记为GPIO-A1和GPIO-A2；第二GPIO集合B包括2个GPIO，分别记为GPIO-B1和GPIO-B2。然后，利用第一GPIO集合A和第二GPIO集合B，对左侧画面帧和右侧画面帧进行同步处理。
具体地，如图28所示的第一FRC电路输出的左侧画面与第二FRC电路输出的右侧画面同步的原理示意图，所述对左侧画面帧和右侧画面帧进行同步处理，用于第二FRC电路，包括：
(a)读取(read)第一FRC电路为第一GPIO集合A中N个GPIO实时写入(write)的接口值，计算第一GPIO集合A的状态值。
第一GPIO集合A中的GPIO记为GPIO-A i，GPIO-A i的接口值为X i，i＝1，2，…，N，N大于1，X i取值是由第一FRC电路进行赋值(即图27中第一FRC电路的write，写入)，为便于按照如下公式计算所述第一GPIO集合A的状态值，本实施例中X i取值为0或1，从而形成第一GPIO集合A的状态集(X N，…，X 2，X 1)。通过第一GPIO集合A的状态集(X N，…，X 2，X 1)可以计算第一GPIO集合A的状态值为：
Figure PCTCN2020072382-appb-000001
(b)实时设置第二FRC电路的同步校验值。第一GPIO集合A的状态集可以设置的数量为2 N个，第一GPIO集合A是动态变化的，则第一GPIO集合A的状态值也是动态变化的。第二FRC电路的同步校验值应小于或等于第一GPIO集合A的状态值的最大值。
可以按照状态值从小到大的顺序循环，使第一FRC电路为第一GPIO集合A中GPIO-A i写入接口值。以N＝2为例，第一GPIO集合A的状态集(X 2，X 1)可以为(0，0)、(0，1)、(1，0)和(1，1)四种，则(0，0)对应的状态值为0，(0，1)对应的状态值为1，(1，0)对应的状态值为2，(1，1)对应的状态值为3，可以按照(0，0)、(0，1)、(1，0)和(1，1)的顺序循环，分别为第一GPIO集合A中的GPIO-A i写入接口值，比如(1，0)，则为GPIO-A2写入的接口值为1，为GPIO-A1写入的接口值为0。
(c)判断第二FRC电路的同步校验值是否小于第一GPIO集合A的状态 值。
(d)如果第二FRC电路的同步校验值小于第一GPIO集合A的状态值，则计算第二FRC电路的同步校验值与第一GPIO集合A的状态值之间的差值n1。
(e)丢弃左侧画面帧中的n1帧数据。如果第二FRC电路的同步校验值小于第一GPIO集合A的状态值，说明第一FRC电路输出的左侧画面与第二FRC电路输出的右侧画面不同步，左侧画面将比右侧画面多播放n1帧，则将对应的n1帧丢弃，从而将左侧画面与右侧画面调节同步，然后第一FRC电路和第二FRC电路再将数据发送给显示屏，以显示左右侧同步的画面。
所述对左侧画面帧和右侧画面帧进行同步处理，用于第一FRC电路，包括：
(f)读取(read)第二FRC电路为第二GPIO集合B中N个GPIO实时写入(write)的接口值，计算第二GPIO集合B的状态值。
第二GPIO集合B中的GPIO记为GPIO-B j，GPIO-B j的接口值为Y j，j＝1，2，…，N，N大于1，Y j取值是由第二FRC电路进行赋值(即图27中第二FRC电路的write，写入)，为便于按照如下公式计算所述第二GPIO集合B的状态值，本实施例中Y j取值为0或1，从而形成第二GPIO集合B的状态集(Y N，…，Y 2，Y 1)。通过第二GPIO集合B的状态集(Y N，…，Y 2，Y 1)可以计算第二GPIO集合B的状态值为：
Figure PCTCN2020072382-appb-000002
(g)实时设置第一FRC电路的同步校验值。第二GPIO集合B的状态集可以设置的数量为2 N个，第二GPIO集合B是动态变化的，则第二GPIO集合B的状态值也是动态变化的。第一FRC电路的同步校验值应小于或等于第二GPIO集合B的状态值的最大值。
可以按照状态值从小到大的顺序循环，使第二FRC电路为第二GPIO集合B中GPIO-B j写入接口值。以N＝2为例，第二GPIO集合B的状态集(Y 2，Y 1)可以为(0，0)、(0，1)、(1，0)和(1，1)四种，则(0，0)对应的状态值为0，(0，1)对应的状态值为1，(1，0)对应的状态值为2，(1，1)对应的状态值为3，可以按照(0，0)、(0，1)、(1，0)和(1，1)的顺序循环，分别为第二GPIO集合B中的GPIO-B j写入接口值，比如(0，1)，则为GPIO-B2 写入的接口值为0，为GPIO-A1写入的接口值为1。
(h)判断第一FRC电路的同步校验值是否小于第二GPIO集合B的状态值。
(i)如果第一FRC电路的同步校验值小于第二GPIO集合B的状态值，则计算第一FRC电路的同步校验值小于第二GPIO集合B的状态值之间的差值n2。
(j)丢弃右侧画面帧中的n2帧数据。如果第一FRC电路的同步校验值小于第二GPIO集合B的状态值，说明第一FRC电路输出的左侧画面与第二FRC电路输出的右侧画面不同步，右侧画面将比左侧画面多播放n2帧，则将对应的n2帧丢弃，从而将左侧画面与右侧画面调节同步，然后第一FRC电路和第二FRC电路再将数据发送给显示屏，以显示左右侧同步的画面。
步骤(a)～步骤(j)，是基于GPIO状态集的方式，使第一FRC电路与第二FRC电路通过相互校验的方式，来调节左侧画面与右侧画面的同步，这样显示屏屏幕可以在画面同步的状态下实现8K×4K@120Hz信号幕的无失帧显示，从而提高智能电视的画面展示效果和画质。
如图29所示，本申请还提供另一种显示设备的实施例，包括SOC电路200、第一FRC电路300、第二FRC电路400和显示屏500，SOC电路200包括视频接收器200-1，视频接收器200-1可与信号设备100连接，视频接收器200-1被配置为接收信号设备100生成的视频源信号；SOC电路200还包括控制器200-2，控制器200-2被配置为：根据所述视频源信号的分辨率和刷新频率，以及根据所述第一FRC电路的上限输入量和所述第二FRC电路的上限输入量，确定SOC输出信号；其中，所述上限输入量为允许输入的最大数据量；控制器200-2可分别与第一FRC电路300和第二FRC电路400连接，用于分别向第一FRC电路300和第二FRC电路400输入所述SOC输出信号；
第一FRC电路300，用于对所述SOC输出信号进行倍频处理，得到第一FRC输出信号，所述第一FRC输出信号对应于左侧画面帧；
第二FRC电路400，用于对所述SOC输出信号进行倍频处理，得到第二FRC输出信号，所述第二FRC输出信号对应于右侧画面帧；
显示屏500，用于接收所述左侧画面帧和所述右侧画面帧，并显示所述左侧画面帧和所述右侧画面帧整合后的图像；
其中，所述第一FRC输出信号和所述第二FRC输出信号的刷新频率等于预设的显示屏输出信号的刷新频率。
本实施例提供的显示设备，通过两个FRC电路执行的倍频处理，以及显示屏对左侧画面帧和所述右侧画面帧的整合(第一FRC输出信号与第二FRC输出信号的分辨率可以叠加)，使显示屏能够显示满足预设分辨率和刷新频率的视频图像，预设分辨率和刷新频率是根据实际应用中期望达到的高分辨率和高刷新频率来设定的，从而使显示设备达到目标显示效果的要求，根据视频源信号的分辨率和刷新频率，以及根据第一FRC电路的上限输入量和第二FRC电路的上限输入量，可以更灵活地设定SOC输出信号的格式，可以使SOC电路输出避免信号失帧的信号。本实施例与前述显示设备的实施例，相同相似的部分可以相互参照，本实施例不再赘述。
本申请各实施例中，第一FRC电路300和第二FRC电路400可支持信号输入的lane数不限于16lane；显示屏500可以为智能电视、户外显示屏、液晶显示屏、电脑显示屏、投影显示屏或者其他具有视频图像显示功能的装置。所述显示设备中的SOC电路200、第一FRC电路300和第二FRC电路400，还可被配置为用于执行上述方法实施例中的其他相关程序步骤，本说明书中各个实施例之间相同相似的部分互相参照即可。
其中，在上述实施例中，主控电路即为SOC电路，第一处理电路即为第一FRC电路，第二处理电路第二FRC电路，屏幕即为显示屏。
本领域技术人员在考虑说明书及实践这里公开的申请后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (20)

  1. 一种显示设备，其特征在于，包括主控电路、第一处理电路、第二处理电路、屏幕和I2C线；所述第一处理电路和第二处理电路并联连接在所述主控电路和所述屏幕之间，所述主控电路还通过I2C线与所述第一处理电路连接；
    所述主控电路，用于确定第一信号和第一输出模式，发送所述第一信号到所述第一处理电路和所述第二处理电路，以及，通过所述I2C线发送所述第一输出模式到所述第一处理电路；
    所述第一处理电路，用于根据所述第一输出模式和所述第一信号，得到第一半帧信号，并发送到所述屏幕，以及，用于根据所述第一输出模式，确定第二半帧信号的方向，并发送给所述第二处理电路；
    所述第二处理电路，用于根据所述第二半帧信号的方向，确定第二输出模式，以及根据所述第二输出模式和所述第一信号，得到所述第二半帧信号，并发送到所述屏幕；
    所述屏幕，用于显示所述第一半帧信号和所述第二半帧信号，其中，所述第一半帧信号和所述第二半帧信号组成一帧画面。
  2. 根据权利要求1所述的显示设备，其特征在于，所述第一处理电路包括：
    第一信号处理电路，用于对所述第一信号执行放大操作和倍频操作，得到第二信号；
    第一生成电路，用于根据所述第一输出模式，生成所述第二信号中每帧画面的所述第一半帧信号并确定所述第二半帧信号的方向；
    第一发送电路，用于发送所述第一半帧信号到所述屏幕，以及，向所述第二处理电路发送所述第二半帧信号的方向。
  3. 根据权利要求1所述的显示设备，其特征在于，所述第二处理电路包括：
    第二信号处理电路，用于对所述第一信号执行放大操作和倍频操作，得到第二信号；
    第二生成电路，用于根据所述第二半帧信号的方向，确定所述第二输出模式，生成所述第二信号中每帧画面的第二半帧信号；
    第二发送电路，用于发送所述第二半帧信号到所述屏幕。
  4. 根据权利要求2所述的显示设备，其特征在于，所述第一信号处理电路包括：
    放大电路，用于对第一信号执行放大操作，得到第四信号；
    倍频电路，用于对所述第四信号执行倍频操作，生成所述第二信号。
  5. 根据权利要求2所述的显示设备，其特征在于，所述第一生成电路包括，
    第一确定电路，用于根据所述第一输出模式，确定所述第一半帧信号的方向；
    第二确定电路，用于根据所述第一半帧信号的方向，确定所述第二半帧信号的方向；
    第三生成电路，用于根据所述第一输出模式，生成所述第二信号中每帧画面的第一半帧信号。
  6. 根据权利要求5所述的显示设备，其特征在于，所述第一确定电路包括：
    获取电路，用于获取所述屏幕的分辨率m3*n3；
    所述第一输出模式包括输出坐标的横坐标x、纵坐标y、输出宽高的宽度w和高度h；
    第一判断电路，用于判断x是否等于0，以及y是否等于0；
    第二判断电路，用于如果x等于0，且y等于0，判断w是否等于1/2m3；
    如果w等于1/2m3，则所述第一半帧信号的方向为左侧；
    第三判断电路，用于如果w不等于1/2m3，则判断w是否等于m3；
    如果w等于m3，则所述第一半帧信号的方向为上侧；
    如果w不等于m3，则为异常，所述第一半帧信号的方向为默认方向；
    第四判断电路，用于如果x不等于0，y等于0，判断x是否等于1/2m3，以及w是否等于1/2m3；
    如果x等于1/2m3，且w等于1/2m3，则所述第一半帧信号的方向为右侧；
    如果x不等于1/2m3，和/或w不等于1/2m3，则为异常，所述第一半帧信号的方向为默认方向；
    第五判断电路，用于如果x等于0，y不等于0，判断y是否等于1/2n3，以及w是否等于m3；
    如果y等于1/2n3，且w等于m3，则所述第一半帧信号的方向为下侧；
    如果y不等于1/2n3，和/或w不等于m3，则为异常，所述第一半帧信号的方向为默认方向。
  7. 根据权利要求1所述的显示设备，其特征在于，所述主控电路包括：
    获取电路，用于获取第三信号；
    转化电路，用于根据预设格式，将所述第三信号转化为所述第一信号。
  8. 一种图像输出方法，其特征在于，用于主控电路，所述方法包括：
    确定第一信号和第一输出模式，发送所述第一信号到第一处理电路和第二处理电路，以及，通过I2C线发送所述第一输出模式到所述第一处理电路。
  9. 一种图像输出方法，其特征在于，用于屏幕，所述方法包括：
    显示第一半帧信号和第二半帧信号，其中所述第一半帧信号和所述第二半帧信号组成一帧画面。
  10. 一种图像输出方法，其特征在于，用于第一处理电路，所述方法包括：
    根据第一输出模式和第一信号，得到第一半帧信号，并发送到屏幕，以及，用于根据所述第一输出模式，确定第二半帧信号的方向，并通知第二处理电路所述第二半帧信号的方向。
  11. 一种显示设备，包括SOC电路和显示屏，其特征在于，还包括第一FRC电路和第二FRC电路，所述SOC电路分别与所述第一FRC电路和所述第二FRC电路连接；
    所述SOC电路，用于接收视频源信号，根据所述视频源信号的分辨率和刷新频率，以及根据所述第一FRC电路的上限输入量和所述第二FRC电路的上限输入量，确定SOC输出信号，并将所述SOC电路输出信号分别输入至所述第一FRC电路和所述第二FRC电路；其中，所述上限输入量为允许输入的最大数据量；
    所述第一FRC电路，用于对所述SOC电路输出信号进行倍频处理，得到第一FRC电路输出信号，所述第一FRC电路输出信号对应于左侧画面帧；
    所述第二FRC电路，用于对所述SOC电路输出信号进行倍频处理，得到第二FRC电路输出信号，所述第二FRC电路输出信号对应于右侧画面帧；
    所述第一FRC电路，还用于将所述左侧画面帧按照所述第一FRC电路输出信号的分辨率和刷新频率输入至所述显示屏；
    所述第二FRC电路，还用于将所述右侧画面帧按照所述第二FRC电路输出信号的分辨率和刷新频率输入至所述显示屏；
    其中，所述第一FRC电路输出信号与所述第二FRC电路输出信号的分辨率之和等于目标分辨率，所述目标分辨率为预设的显示屏输出信号的分辨率； 所述第一FRC电路输出信号和所述第二FRC电路输出信号的刷新频率等于第一目标刷新频率，所述第一目标刷新频率为预设的显示屏输出信号的刷新频率。
  12. 根据权利要求11所述的显示设备，其特征在于，所述SOC电路还用于：
    判断所述视频源信号的数据量是否超过所述第一FRC电路的上限输入量；
    如果所述视频源信号的数据量未超过所述第一FRC电路的上限输入量，则判断所述视频源信号的分辨率是否等于所述目标分辨率；
    如果所述视频源信号的分辨率等于所述目标分辨率，则使所述SOC输出信号为所述视频源信号。
  13. 根据权利要求12所述的显示设备，其特征在于，所述SOC电路还用于：
    如果所述视频源信号的分辨率小于所述目标分辨率，则判断所述视频源信号的刷新频率是否小于或等于第二目标刷新频率；所述第二目标刷新频率为倍频处理前，所述SOC输出信号所能达到的最大刷新频率；
    如果所述视频源信号的刷新频率小于或等于第二目标刷新频率，则使所述SOC输出信号的分辨率等于所述视频源信号的分辨率，所述SOC输出信号的刷新频率等于所述第二目标刷新频率。
  14. 根据权利要求12所述的显示设备，其特征在于，所述SOC电路还用于：
    如果所述视频源信号的数据量超过所述第一FRC电路的上限输入量，则判断所述视频源信号的分辨率是否等于所述目标分辨率；
    如果所述视频源信号的分辨率等于所述目标分辨率，则使所述SOC输出信号的分辨率等于所述目标分辨率的一半，所述SOC输出信号的刷新频率等于第二目标刷新频率；其中，所述第二目标刷新频率为倍频处理前，所述SOC输出信号所能达到的最大刷新频率；
    其中，输入至所述第一FRC电路的SOC输出信号对应于左侧画面帧，输入至所述第二FRC电路的SOC输出信号对应于右侧画面帧。
  15. 根据权利要求12或13所述的显示设备，其特征在于，
    所述第一FRC电路还用于：判断如果所述第一FRC输出信号的分辨率等于所述目标分辨率，并且所述第一FRC输出信号的刷新频率等于所述第一目标 刷新频率时，所述第一FRC输出信号的数据量是否超过所述第一FRC电路的上限输出量；如果所述第一FRC输出信号的数据量超过所述第一FRC电路的上限输出量，则对所述SOC输出信号中的左侧画面帧进行倍频处理；
    所述第二FRC电路还用于：判断如果所述第二FRC输出信号的分辨率等于所述目标分辨率，并且所述第二FRC输出信号的刷新频率等于所述第一目标刷新频率时，所述第二FRC输出信号的数据量是否超过所述第二FRC电路的上限输出量；如果所述第二FRC输出信号的数据量超过所述第二FRC电路的上限输出量，则对所述SOC输出信号的右侧画面帧进行倍频处理；
    其中，所述上限输出量为允许输出的最大数据量。
  16. 根据权利要求11所述的显示设备，其特征在于，
    在第一FRC电路内预置第一通用I/O接口集合，在第二FRC电路内预置第二通用I/O接口集合，第一通用I/O接口集合和第二通用I/O接口集合内分别包括数量相等的通用I/O接口；
    利用第一通用I/O接口集合和第二通用I/O接口集合，对所述左侧画面帧和所述右侧画面帧进行同步处理。
  17. 根据权利要求16所述的显示设备，其特征在于，所述第二FRC电路还用于：
    读取第一FRC电路为第一通用I/O接口集合中全部通用I/O接口实时写入的接口值，计算第一通用I/O接口集合的状态值；
    实时设置第二FRC电路的同步校验值；
    判断第二FRC电路的同步校验值是否小于第一通用I/O接口集合的状态值；
    如果第二FRC电路的同步校验值小于第一通用I/O接口集合的状态值，则计算第二FRC电路的同步校验值与第一通用I/O接口集合的状态值之间的差值n1；
    丢弃左侧画面帧中的n1帧数据。
  18. 根据权利要求17所述的显示设备，其特征在于，所述第一FRC电路还用于：
    读取第二FRC电路为第二通用I/O接口集合中全部通用I/O接口实时写入的接口值，计算第二通用I/O接口集合的状态值；
    实时设置第一FRC电路的同步校验值；
    判断第一FRC电路的同步校验值是否小于第二通用I/O接口集合的状态值；
    如果第一FRC电路的同步校验值小于第二通用I/O接口集合的状态值，则计算第一FRC电路的同步校验值与第二通用I/O接口集合的状态值之间的差值n2；
    丢弃右侧画面帧中的n2帧数据。
  19. 一种显示设备，包括SOC电路和显示屏，其特征在于，还包括第一FRC电路和第二FRC电路，SOC电路包括视频接收器，所述视频接收器被配置为接收视频源信号；所述SOC电路还包括控制器，所述控制器被配置为：根据所述视频源信号的分辨率和刷新频率，以及根据所述第一FRC电路的上限输入量和所述第二FRC电路的上限输入量，确定SOC输出信号；其中，所述上限输入量为允许输入的最大数据量；所述控制器分别与所述第一FRC电路和所述第二FRC电路连接；
    所述第一FRC电路，用于对所述SOC输出信号进行倍频处理，得到第一FRC输出信号，所述第一FRC输出信号对应于左侧画面帧；
    所述第二FRC电路，用于对所述SOC输出信号进行倍频处理，得到第二FRC输出信号，所述第二FRC输出信号对应于右侧画面帧；
    所述显示屏，用于接收所述左侧画面帧和所述右侧画面帧，并显示所述左侧画面帧和所述右侧画面帧整合后的图像；
    其中，所述第一FRC输出信号和所述第二FRC输出信号的刷新频率等于预设的显示屏输出信号的刷新频率。
  20. 一种图像输出方法，用于如权利要求11-18任一项所述的显示设备，其特征在于，所述方法包括：
    SOC电路接收视频源信号，根据所述视频源信号的分辨率和刷新频率，以及根据所述第一FRC电路的上限输入量和所述第二FRC电路的上限输入量，确定SOC输出信号，并将所述SOC输出信号分别输入至所述第一FRC电路和所述第二FRC电路；其中，所述上限输入量为允许输入的最大数据量；
    第一FRC电路对所述SOC输出信号进行倍频处理，得到第一FRC输出信号，所述第一FRC输出信号对应于左侧画面帧；
    第二FRC电路对所述SOC输出信号进行倍频处理，得到第二FRC输出信号，所述第二FRC输出信号对应于右侧画面帧；
    所述第一FRC电路将所述左侧画面帧按照所述第一FRC输出信号的分辨率和刷新频率输入至所述显示屏；
    所述第二FRC电路将所述右侧画面帧按照所述第二FRC输出信号的分辨率和刷新频率输入至所述显示屏；
    其中，所述第一FRC输出信号与所述第二FRC输出信号的分辨率之和等于目标分辨率，所述目标分辨率为预设的显示屏输出信号的分辨率；所述第一FRC输出信号和所述第二FRC输出信号的刷新频率等于第一目标刷新频率，所述第一目标刷新频率为预设的显示屏输出信号的刷新频率。
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