WO2022022106A1 - 图像数据处理装置、方法及显示装置 - Google Patents

图像数据处理装置、方法及显示装置 Download PDF

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Publication number
WO2022022106A1
WO2022022106A1 PCT/CN2021/099704 CN2021099704W WO2022022106A1 WO 2022022106 A1 WO2022022106 A1 WO 2022022106A1 CN 2021099704 W CN2021099704 W CN 2021099704W WO 2022022106 A1 WO2022022106 A1 WO 2022022106A1
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Prior art keywords
data
image
frame
memory
input
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PCT/CN2021/099704
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English (en)
French (fr)
Inventor
耿立华
李彦孚
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京东方科技集团股份有限公司
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Priority to US17/755,372 priority Critical patent/US20220345769A1/en
Publication of WO2022022106A1 publication Critical patent/WO2022022106A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
    • H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394
    • H04N21/43635—HDMI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/431—Generation of visual interfaces for content selection or interaction; Content or additional data rendering
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/127—Updating a frame memory using a transfer of data from a source area to a destination area
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an image data processing apparatus, method, and display apparatus.
  • the resolution of the video is constantly increasing, such as 4K high-definition video with a resolution of 4096 ⁇ 2160 pixels, or 8K ultra-high-definition video with a resolution of 7680 ⁇ 4320 pixels, etc.
  • the data traffic that needs to be transmitted and displayed for video increases with the increase of its resolution, resulting in huge data traffic that needs to be transmitted and displayed for high-definition video and ultra-high-definition video. Therefore, in the transmission process of high-definition video or ultra-high-definition video from the source end to the display device, it is necessary to use multiple video interfaces to multiplex the video at the same time.
  • the video input from different interfaces needs to complete the synchronization of the video data, the conversion of the image segmentation method of the input data and the image segmentation method of the required data when arriving in the system. Frame rate conversion, etc.
  • the purpose of the technical solution of the present disclosure is to provide an image data processing device, method and display device, which can ensure the data synchronization when multi-interface video data is input, the conversion between the image segmentation method of the input data and the image segmentation method of the required data, and the frame rate conversion.
  • Embodiments of the present disclosure provide an image data processing apparatus, including:
  • each of the write controllers configured to respectively acquire input data of a plurality of image blocks into which a multi-frame input image is divided, wherein each of the write controllers is configured to acquire a plurality of images into which each frame of the input image is divided input data of an image block in the block, and determine the frame address of the input data stored in the memory, and send the input data to the memory according to the determined frame address;
  • a plurality of read controllers wherein each of the read controllers is associated with at least one of the write controllers, and each of the read controllers is configured to determine a first frame address, and obtain from the first frame address
  • the memory is the data of the second frame address, and outputs the acquired data of the second frame address, wherein the first frame address is the write controller associated with each of the read controllers
  • the frame address of the currently acquired input data in the memory, the second frame address and the first frame address differ by a preset fixed number of frame addresses.
  • each of the read controllers is associated with at least two of the write controllers
  • the image blocks corresponding to the data acquired by the read controllers include the first A sub-image block and a second sub-image block, excluding the third sub-image block and the fourth sub-image block, wherein the input data corresponding to the input data acquired by the first write controller associated with the read controller
  • the image block includes the first sub-image block and the third sub-image block
  • the image block corresponding to the input data acquired by the second write controller associated with the read controller includes the second sub-image block and Fourth sub-image block.
  • the read controller is configured to: after acquiring the data of the second frame address in the memory, when acquiring the data from the memory again, if the same as the If the frame address in the memory of the input data currently obtained by the write controller associated with the read controller still remains the first frame address, the data at the second frame address is repeatedly obtained.
  • the read controller is configured to: before acquiring the data of the second frame address from the memory, if the memory also includes the data of the third frame address. If the data is not obtained, the data obtained as the third frame address is discarded, wherein the time when the write controller associated with the read controller sends the input data corresponding to the third frame address is at the time of sending the address. before the time of the input data corresponding to the second frame address.
  • the image data processing apparatus further comprises:
  • a detection module configured to detect whether the input data input to each of the write controllers is abnormal data
  • a first image padding module connected to the detection module and the read controller, the first image padding module is configured to: acquire data output by each of the read controllers, in response to the detection module determining The input data of the image block corresponding to the target frame input to the write controller is abnormal data, and the data of the image block corresponding to the target frame is output as preset padding image data; or, the first image padding module is Configured as:
  • the read controller In response to the detection module determining that the input data currently input to the write controller is abnormal data, the read controller stops acquiring data in the memory, and the first image padding module outputs preset padding image data.
  • the image data processing apparatus wherein, for the first image padding module is configured to: acquire data output by each of the read controllers, in response to the detection module determining that the input to the The input data of the image block corresponding to the target frame of the writing controller is abnormal data, and the data of the image block corresponding to the target frame is filled with the preset image data output situation,
  • the first image padding module is further connected to the write controller, and the write controller is further configured to output the frame address of the image block corresponding to the target frame in the memory to the first image padding module , the first image filling module determines the data of the image block corresponding to the target frame output by the read controller according to the frame address of the image block corresponding to the target frame in the memory.
  • the write controller is further configured to, when sending the input data to the memory, if it is determined that the input data is abnormal data, according to the determined
  • the frame address is sent to the memory with preset padded image data instead of the input data, or preset characters are sent to the memory.
  • the image data processing apparatus further comprises:
  • a second image filling module connected to the read controller, is configured to, in response to the output data of the image block corresponding to the target frame outputted by the read controller being the preset character, make the image corresponding to the target frame
  • the data of the block is output with preset padding image data.
  • one of the write controllers sends the input data to the target frame address of the memory, if the interval is preset. If the input data is not received for a period of time, after the input data is received again, the input data is sent to the memory from a frame address next to the target frame address of the memory.
  • the image data processing apparatus wherein, in the process of acquiring the data of the second frame address from the memory, the read controller, if the write associated with the read controller The frame address of the input data currently sent by the controller to the memory is changed to the fourth frame address, and the read controller keeps acquiring the data of the second frame address until the data acquisition of the second frame address is completed, wherein , the fourth frame address is different from the first frame address.
  • the image data processing apparatus further comprises:
  • an arbiter connected to the memory, the write controller and the read controller, respectively, the arbiter is configured to configure the transmission authority of each write controller to send the input data to the memory, and configure Each of the read controllers has a transfer right to read data from the memory.
  • the image data processing apparatus wherein the image data processing apparatus further includes the memory, the memory is a double-rate memory, and the double-rate memory communicates with the arbitration through a memory controller device connection;
  • the arbiter is further configured to control data transfer between the write controller and the read controller and the memory controller when the write controller and the read controller are configured with transfer permissions The path is connected, and when the write controller and the read controller are not configured with transfer rights, the data transfer path between the write controller and the read controller and the memory controller is controlled to be disconnected.
  • the image data processing apparatus further comprises:
  • At least two image data input interfaces each of which is connected to at least one of the write controllers; the image data input interfaces are configured to receive part of the data to be processed of each frame of the input image, and to The part of the data to be processed is subjected to format conversion to obtain the input data sent to the write controller connected thereto.
  • different write controllers send the input data belonging to the same frame of input image to the same frame address of the memory, or to different frames of the memory. frame address.
  • An embodiment of the present disclosure further provides a display device, which includes a display module and the image data processing device according to any one of the above.
  • Embodiments of the present disclosure also provide an image data processing method, including:
  • a plurality of write controllers respectively obtain input data of a plurality of image blocks into which the multi-frame input image is divided, wherein each write controller obtains input data of one image block of the plurality of image blocks into which each frame of the input image is divided , and determine the frame address of the input data stored in the memory, and send the input data to the memory according to the determined frame address;
  • a plurality of read controllers respectively determine the first frame address, obtain the data of the second frame address in the memory according to the first frame address, and output the obtained data of the second frame address, wherein the first frame address is A frame address is the frame address of the input data currently acquired by the write controller associated with each read controller, and the second frame address differs from the first frame address by a preset fixed number of frame addresses ; wherein each of the read controllers is associated with at least one of the write controllers.
  • FIG. 1 is a schematic structural diagram of an image data processing apparatus according to Embodiment 1 of the present disclosure
  • FIG. 2 is a schematic diagram illustrating the conversion between the image segmentation method of the input data and the image segmentation method of the required data
  • FIG. 3 is a schematic structural diagram of an image data processing apparatus according to Embodiment 2 of the present disclosure.
  • FIG. 4 is a schematic diagram illustrating the relationship between an image block division method of input data and an image block division method of output data
  • FIG. 5 is a schematic diagram illustrating the principle of outputting preset padding data by a first image padding module
  • 6a and 6b are schematic diagrams illustrating a read/write control method using one of the implementation manners of the image data processing apparatus according to the embodiment of the present disclosure
  • FIG. 7 is a schematic diagram illustrating a read/write control method in another implementation manner of the image data processing apparatus according to the embodiment of the present disclosure.
  • FIG. 8 is a schematic flowchart illustrating an image data processing method according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides an image data processing device, which is configured by setting and A plurality of write controllers corresponding to the divided image blocks of the input image one-to-one, and a plurality of read controllers corresponding to the divided image blocks of the output image, the plurality of write controllers determine the divided image blocks of each frame The frame address where the input data of one image block among the multiple image blocks is stored in the memory, and the input data is written into the memory according to the frame address; the read controller determines that the output data of the corresponding image block is stored in the memory and read the output data from the memory according to the determined frame address, so that multiple write controllers and multiple read controllers are used to write and read multiple frames of input images in the memory respectively.
  • the conversion between the image segmentation the conversion between the image segmentation
  • the read controller follows the associated write controller when reading data from the memory.
  • each image block output from multiple read controllers can belong to the same image frame, that is, the output image frame synchronization can be simply realized.
  • the image data processing apparatus includes:
  • a plurality of write controllers 200 are configured to respectively obtain input data of a plurality of image blocks into which the multi-frame input image is divided, wherein each write controller 200 is configured to obtain a plurality of images into which each frame of the input image is divided input data of an image block in the block, and determine the frame address of the input data stored in the memory 100, and send the input data to the memory 100 according to the determined frame address;
  • a plurality of read controllers 300 wherein each read controller 300 is associated with at least one write controller 200, and each read controller 300 is configured to determine a first frame address, and obtain the address in the memory 100 according to the first frame address.
  • the data of the second frame address is output, and the obtained data is the second frame address, wherein the first frame address is the input data currently obtained by the write controller 200 associated with each read controller 300 in the memory 100 frame address, the difference between the second frame address and the first frame address is a preset fixed number of frame addresses.
  • the write controller 200 and the read controller 300 may be field programmable gate array (Field Programmable Gate Array, FPGA) chips, respectively, which are respectively formed as the write controller 200 and the read controller.
  • FPGA Field Programmable Gate Array
  • the FPGA chip of 300 is connected with the memory 100 through circuit lines.
  • the number of the write controllers 200 is determined by the number of divisions of the multiple image blocks into which the input image is divided, and the number of the read controllers 300 is determined by the number of divisions of the multiple image blocks in the output image.
  • the input image can be input to the writing controller 200 through four HDMI2.0 interfaces, and each frame of the input image is divided into four image blocks A, B, C and D;
  • each frame of the input image is divided into four image blocks A', B', C according to the "Chuan” font segmentation method.
  • 'and D' that is, it is necessary to transform the input data divided according to the "Tian” font into the output data divided according to the "chuan” font, so that it can be input to the display device to realize the conversion of the image segmentation method of the input data.
  • the image block A' corresponds to the left part of the image block of the image block A and the image block of the image block C of the input image.
  • the left part of the image block; the image block B' corresponds to the right part of the image block of the image block A of the input image and the right part of the image block of the image block C;
  • the image block C' corresponds to the left part of the image block and the image block of the image block B of the input image
  • the left part of the image block of D; the image block D' corresponds to the right part of the image block of the image block B and the right part of the image block of the image block D of the input image.
  • the number of write controllers 200 is four, and the input data of the corresponding image block in each frame of the input image is input to one of the write controllers 200, see FIG. 1 and FIG. 2, the input data of image block A, image block B, image block C and image block D in the input image of each frame are respectively input to the first write controller 201 and the second write controller in the write controller 200.
  • the read controller 301 , the second read controller 302 , the third read controller 303 and the fourth read controller 304 are read out from the memory 100 to enable further input to the display module for image display.
  • the transformation of the image segmentation method of the input data can be realized through the above-mentioned implementation structure.
  • the multi-interface can be guaranteed by controlling the timing of writing and reading. Data synchronization and frame rate conversion when video data is input.
  • the image data processing apparatus described in the embodiment of the present disclosure realizes the above-mentioned data synchronization, the conversion between the image segmentation method of the input data and the image segmentation method of the required data, and the frame rate conversion.
  • the specific structure and manner are described in detail.
  • the image data processing apparatus includes a memory 100 , multiple write controllers 200 and multiple read controllers 300 , and optionally, further includes: a video input module 400 and an arbiter 500 , a timing signal generator 600 , a detection module 700 , a first image filling module 800 , a memory control module 900 and a video output module 1000 .
  • the number of video input modules 400 is at least two, each video input module 400 corresponds to a video input interface, and is responsible for receiving part of the data to be processed of each frame of input image according to the protocol standard of the video input interface. Specifically, each frame of input image of the input video is divided into several parts of data to be processed according to the number of video input modules 400, which are respectively input by the corresponding video input module 400, and transmitted to the corresponding write data through the video input module 400. controller 200.
  • the format of the video input to each video input module 400 for part of the data to be processed may be different from the format of the data that the write controller 200 can receive and process. Therefore, the video input module 400 is configured to receive part of the data to be processed in each frame of the input image, and perform format conversion on the part of the data to be processed to obtain the input data sent to the corresponding write controller 200 .
  • the data format of the video input to each video input module 400 may be one of RGB, YCbCbr444, YCbCr422 and YCbCr420, and the bit depth may be 8 bits, 10 bits or 12 bits, etc.
  • the video input module 400 can convert all The input is part of the data to be processed in the above format, which is restored to the standard video timing and data (such as including frame synchronization signal, line synchronization signal, video data enable signal and video data), and the format of this part of the data to be processed is unified. It is the format of RGB and preset bit depth (such as 10bit bit depth).
  • the video interfaces that the video input module 400 can support include, but are not limited to, a high definition multimedia interface (High Definition Multimedia Interface, HDMI), a display interface (DisplayPort, DP), and a low-voltage differential signal (Low-Voltage Differential Signaling, LVDS) version, etc.
  • a high definition multimedia interface High Definition Multimedia Interface, HDMI
  • a display interface DisplayPort, DP
  • a low-voltage differential signal Low-Voltage Differential Signaling, LVDS version
  • the writing controller 200 is connected to the video input module 400, wherein one video input module 400 is connected to at least one writing controller 200, and the number of the writing controllers 200 is determined by the division of the multiple image blocks into which the input image is divided The number is determined, and each write controller 200 obtains the input data of the corresponding image block in each frame of the input image from the connected at least one video input module 400 .
  • the number of write controllers 200 and video input modules 400 is the same, and multiple write controllers 200 are connected to multiple video input modules 400 in one-to-one correspondence, but not limited to this.
  • at least one video input module is used.
  • the data output of the module 400 can satisfy the data input of the corresponding image block of the write controller 200 as the set condition.
  • the write controller 200 performs data format conversion on the received input data of the corresponding image block in pixel row units, wherein the pixel row data for each format conversion may be called burst format data, and specifies the input data
  • the address of the image frame, line and pixel in the memory 100, and the input data of one pixel line of the corresponding image block is written to the memory 100 in a burst (also called one-shot) manner.
  • the read controller 300 specifies the addresses in the memory 100 of the image frames, lines and pixels to be read from the memory 100, and optionally reads the output data from the memory 100 in bursts, each burst from the memory 100.
  • the memory 100 reads out the output data of one pixel row of the corresponding image block.
  • the output data read by the read controller 300 is output to the driver chip of the display module through the video output module 1000 to display the output image on the display module.
  • the image data processing apparatus further includes an arbiter 500, which is connected to the memory 100, the write controller 200, and the read controller 300, respectively, and the arbiter 500 is configured to configure each write controller 200 to write the transmission authority of the input data to the memory 100 , and configure the transmission authority of each read controller 300 to read the output data from the memory 100 .
  • an arbiter 500 which is connected to the memory 100, the write controller 200, and the read controller 300, respectively, and the arbiter 500 is configured to configure each write controller 200 to write the transmission authority of the input data to the memory 100 , and configure the transmission authority of each read controller 300 to read the output data from the memory 100 .
  • the write controller 200 configured with the transmission authority obtains the transmission authority to write input data to the memory 100 , and can write input data to the memory 100 ;
  • the read controller 300 configured with the transmission authority obtains the read output data from the memory 100 The transmission authority can read the output data from the memory 100 .
  • the memory 100 is a double data rate (Double Data Rate, DDR) memory
  • the DDR memory is connected to the arbiter 500 through the memory control module 900, wherein the write controller 200 and the read controller 300 are connected by
  • the data transmission path is connected with the memory control module 900, and the data transmission path with the memory control module 900 is disconnected when the write controller 200 and the read controller 300 are not configured with the transmission authority.
  • the arbiter 500 is responsible for connecting the memory 100, the write controller 200, the read controller 300 and the memory control module 900 together through a bus with a burst function, and through a certain arbitration mechanism
  • a write controller 200 arbitrates with each read controller 300, and the arbitrated write controller 100 and read controller 300 are configured with transmission rights, can directly establish a connection with the memory control module 900, and independently occupy the memory control module 900. data transmission path between.
  • connection between the write controller 200 and the read controller 300 and the arbiter 500 is a bus that supports the data burst function.
  • an AXI4-MM bus is used, wherein the write controller 200 is connected to the read controller.
  • the setting end of the arbiter 300 is the master end of the bus, and the setting end of the arbiter 500 is the slave end of the bus.
  • the type of bus between the write controller 200 and the read controller 300 and the arbiter 500 is the same as that between the memory control module 900 and the arbiter 500 .
  • the arbiter 500 configures the transmission rights of the multiple write controllers 200 and the multiple read controllers 300 in a round-robin manner, that is, each write controller 200 and each read controller 300 obtain transmission rights. Equally and cyclically obtain transmission permissions.
  • the write controller 200 performs data bursts in units of pixel rows, determines parameters such as data bit width and data length for burst writing according to the number of pixel data in the pixel row, and determines that the input data of each pixel row is stored in the memory 100 After obtaining the transmission authority to write data to the memory 100, write the input data of one pixel row to the memory 100, and release the transmission authority after completing a burst.
  • the data written in each burst is pixel data of one pixel row; in another embodiment, the data written in each burst is part of the pixel data of one pixel row, and the pixel data of one pixel row can be Writing to the memory 100 is performed through multiple (eg, two) burst write processes.
  • the read controller 300 performs data bursts in units of pixel rows, determines parameters such as the data bit width and data length of the burst read according to the number of pixel data in the pixel row, and determines that the output data of each pixel row is stored in the memory 100 . After obtaining the transmission authority to read data from the memory 100, read the output data of one pixel row from the memory 100, and release the transmission authority after completing a burst.
  • the data read in each burst is pixel data of one pixel row; in another embodiment, the data read in each burst is part of the pixel data of one pixel row, and the pixel data of one pixel row can be Data is read from the memory 100 through multiple (eg, two) burst read processes.
  • input data is stored according to pixel rows, each pixel row corresponds to a row of addresses, and each pixel in each pixel row corresponds to a pixel address.
  • the storage space in the memory 100 is divided and organized, the storage space is divided into a plurality of sub-storage spaces, each sub-storage space corresponds to a frame address, and further each sub-storage space includes the row address of the corresponding pixel row and the corresponding The pixel address of each pixel. Therefore, the storage space in the memory 100 includes a frame address (Frame Address, FA), a line address (Line Address, LA), and a pixel address (Pixel Address, PA).
  • the storage space of the memory 100 is divided into n sub-storage spaces, each sub-storage space stores an image of one frame, and each sub-storage space corresponds to a frame address;
  • the frame addresses corresponding to the two sub-storage spaces are 2, ..., and so on, and the frame address corresponding to the nth sub-space is n.
  • the input data is stored in the form of pixel rows, and each pixel row corresponds to a row address.
  • the row address corresponding to the first pixel row of the input data is 0, and the second pixel row corresponds to the row address.
  • the corresponding row address is 1, ..., and so on, the row address corresponding to the Hth row is H-1.
  • each pixel in each pixel row corresponds to an address, which is a pixel address.
  • the pixel address of the first pixel of each pixel row is 0, the pixel address of the second pixel is 1, ..., and so on, the address of the Lth pixel is L-1.
  • the frame address can be mapped to the memory 100.
  • the bank address of the memory bank, the row address can be mapped to the row line address of the memory 100 and so on.
  • the memory control module 900 is responsible for interfacing with the memory 100 , completing the initialization and management of the memory 100 , converting bus burst data into data that meets the interface requirements of the memory 100 , and executing the data in the memory 100 burst access.
  • the image data processing apparatus further includes a timing signal generator 600 connected to each read controller 300 , and the timing signal generator 600 is configured to input to each read controller 300 The timing signal causes the read controller 300 to output the output data read from the memory 100 in response to the timing signal.
  • a timing signal is input to each read controller 300 through the timing signal generator 600, so that the read controller 300 transmits the read output data to the display module according to the timing signal, so as to ensure the read controller
  • the timing of transmitting the output data to the display module by 300 can meet the data input frequency requirements of the display module, ensuring the time synchronization of the transmission of multiple output data belonging to the same frame read from the multiple read controllers 300 to the display module.
  • the image data processing apparatus further includes a detection module 700 and a first image filling module 800 .
  • the detection module 700 is configured to detect whether the input data input to each write controller 200 is abnormal data
  • the first image padding module 800 is connected to the detection module 700 and each reading controller 300, and the first image padding module 800 is configured to: obtain the data output by each reading controller 300, and determine the input to the detection module 700.
  • the input data of the image block corresponding to the target frame of the write controller 200 is abnormal data
  • the data of the image block corresponding to the target frame is output as preset padding data; or, the first image padding module 800 is configured as:
  • the read controller 300 stops acquiring data in the memory 100, and the first image padding module 800 outputs preset padding image data.
  • the detection module 700 is responsible for detecting whether the input data input by each video input module 400 is abnormal data, and the detected content includes whether the video input module 400 is online (that is, whether the corresponding video input module 400 is connected to a playback source), Whether the resolution and frame rate of the input data are abnormal, etc.
  • the first image padding module 800 outputs the output data of the image block corresponding to the target frame as preset padding data , for example, fill the display area of the image block corresponding to the target frame with black, so as to avoid displaying the wrong format of the image frame, and avoid the situation of wrong image display such as screen painting, flickering and dislocation.
  • the first image padding module 800 is configured to: obtain the data output by each read controller 300, in response to the detection module 700 determining that the input data of the image block corresponding to the target frame input to the write controller 200 is: Abnormal data, the data of the corresponding image block of the target frame is output with the preset padding image data, the first image padding module 800 is also connected with the writing controller 200, and the writing controller 200 is also configured to send the first image
  • the filling module 800 outputs the frame address of the corresponding image block of the target frame in the memory 100, and the first image filling module 800 determines the output of the read controller 300 according to the frame address of the corresponding image block of the target frame in the memory 100.
  • the target frame corresponds to the data of the image block.
  • the first image padding module 800 reads the data from the memory 100 according to the frame address of the target frame determined as abnormal data by the write controller 200 in the memory 100 , and reads the data from the memory 100 according to the frame address associated therewith.
  • the form of the frame address of the data written by the write controller 200 determines the data of the corresponding image block of the target frame output by the read controller 300, and performs preset filling data output, such as filling the display area of the corresponding image block of the target frame with black , to avoid displaying incorrectly formatted image frames.
  • the first image padding module 800 in response to the detection module 700 determining that the input data currently input to the write controller 200 is abnormal data, causes the read controller 300 to stop acquiring the data in the memory 100 at the present time, and outputs a preset data. It is assumed that the image data is padded until the detection module 700 determines that the input data input to the write controller 200 is normal data. In this way, the first image filling module 800 can simply determine the data that needs to be pre-filled for data output when the reading controller 300 performs data output, and can effectively avoid displaying the wrong format image frame. .
  • the detection module 700 may detect that part of the input data of the image block corresponding to the target frame is abnormal data, and when detecting that the part of the input data corresponding to the image block of the target frame is abnormal data, the first image filling module 800 can output the pixel of the image block corresponding to the output screen of the reading controller 300, and the pixel of the detected error data is output with the preset filling data, and the first image filling module 800 can fill the image of the corresponding position into a black screen according to the detection result of the detection module 700. , for example, as shown in FIG. 4 and FIG.
  • the first image filling module 800 The position corresponding to the image block A' (ie, the upper left quarter) of the output picture of the read controller 300 will be filled with a black picture.
  • the write controller 200 is further configured to, when sending the input data to the memory 100, if it is determined that the input data is abnormal data, according to the determined frame address, to Preset padding image data is sent to the memory instead of the input data, or preset characters are sent to the memory.
  • the preset padding image data is written into the memory 100 through the write controller 200, so that the read controller 300 directly reads and outputs the preset padding image data, and then the output image
  • the writing controller 200 can also write preset characters into the memory 100, so that the reading controller 300 can write the preset characters according to the read preset characters.
  • the data of the image block corresponding to the target frame is output as the preset padding image data, which can also achieve the effect of effectively avoiding the display of image frames in an incorrect format.
  • the image data processing apparatus further includes:
  • a second image filling module (not shown in the figure), connected to the read controller, is configured to, in response to the output data of the image block corresponding to the target frame output by the read controller being the preset character, to The data of the image block corresponding to the target frame is output as the preset padding image data.
  • the write controller and the read controller can control the access address, access timing and access speed of the input image frame and the output image frame in the memory. Data synchronization when inputting multi-interface video data, conversion between the image segmentation method of the input data and the image segmentation method of the required data, and frame rate conversion.
  • the image data processing device can realize the data synchronization when the multi-interface video data is input, the conversion between the image segmentation method of the input data and the image segmentation method of the required data, and the frame rate conversion.
  • the implementation process is described in detail.
  • different write controllers 200 write input data belonging to the same frame of input image into the same frame address of the memory 100 , and the write controller 200 writes the input data to the memory 100 .
  • the process of inputting the image frame is not related to the process of reading the output image frame of the output data from the memory 100 by the read controller 300 , that is, the writing process and the reading process of the image data in the memory 100 are separated from each other.
  • the storage space of the memory 100 is divided into n sub-storage spaces, that is, sub-storage spaces S1, S2, ⁇ ⁇ ⁇ , Sn, and each sub-storage space stores an image of one frame
  • each sub-storage space corresponds to a frame address
  • each row address in each sub-storage space corresponds to a row address of a pixel row
  • each pixel in each pixel row corresponds to an address, respectively, is the pixel address.
  • the frame address can be mapped to the memory 100.
  • the Bank address, the row address can be mapped to the Line address of the memory 100, etc.
  • the writing process and the reading process of image data in the memory 100 are separated from each other, that is, different write controllers 200 write input data belonging to different image blocks of the same frame of input image into the same frame of the memory 100 In the address, that is, the space corresponding to the same frame address; on this basis, multiple read controllers 300 read out different image blocks belonging to the same frame output image from the same frame address of the memory 100 .
  • the write controller 200 sequentially writes the input data of each frame of the input image to the memory 100 in a manner of increasing frame addresses in sequence; the read controller 300 sequentially reads out each frame of the output image from the memory 100 in a manner of increasing frame addresses in sequence and the clock frequency at which the write controller 200 triggers writing is synchronized with the clock frequency at which the read controller 300 triggers reading.
  • each sub-storage space corresponds to a frame address, which is used to store the input data of one frame of image, and the stored input data of one frame of image is arranged according to the pixel row, so that each frame address is within Input data corresponding to the four image blocks A, B, C, and D are included, respectively.
  • the four write controllers 200 are in one-to-one correspondence with the four image blocks, and each write controller 200 correspondingly reads the input data of one of the image blocks, and writes the input data of the corresponding image block into the corresponding image of the memory 100 in the block storage space.
  • the input data of the corresponding image blocks A, B, C and D stored in the frame address N are respectively expressed as I(x)-A, I(x)-B, I(x)-C and I(x )-D.
  • x is any integer from 1 to n
  • n is the maximum number of frames of the stored image.
  • FIG. 6b is a diagram showing the structure of the image frame read by the read controller 300 from the memory 100.
  • the four read controllers 300 and the four Each image block is in one-to-one correspondence, and the four read controllers 300 correspond to the image blocks divided according to Fig. 6b, respectively, and read the stored data from the corresponding image blocks;
  • the output data within the frame address N are represented as O(x)-A', O(x)-B', O(x)-C' and O(x)-D', respectively.
  • x is any integer from 1 to n
  • n is the maximum number of frames of the stored image.
  • each write controller 200 writes the frame address of the input data to the memory 100 in increments of 1, and performs data bursts in units of pixel rows. , the corresponding frame address is increased by 1, and the data of the next frame of input image is written; similarly, the frame address of the output data read by the read controller 300 from the memory 100 is incremented by 1, and the data burst is performed in pixel row units. After the memory 100 reads the output data of one frame of output image, the corresponding frame address is incremented by one, and the data of the next frame of output image is read.
  • the transformation between the image segmentation method of the input data and the image segmentation method of the required output data can be realized, specifically:
  • each video input module 400 corresponds to a write controller 200 , and each write controller 400 is responsible for writing the input data input from the corresponding video input module 400 to the storage module 100 .
  • the first write controller 201 can store the input data input by the corresponding video input module 400 in the position I(x)-A
  • the second write controller 202 can store the input data in the position I(x)-A.
  • the input data input by the corresponding video input module 400 is stored in the position I(x)-B
  • the third write controller 203 stores the input data input by the corresponding video input module 400 in the position I(x)-C
  • the quad write controller 204 stores the input data inputted by the corresponding video input module 400 in the position I(x)-D, and so on, where x is any integer from 1 to n, and n is the stored image Maximum number of frames.
  • the write controller 200 writes the input data of the input image into the memory by using a data burst, and transmits data of one row of pixels in each burst, and the address of each burst is the address of the first pixel of the pixel row.
  • the burst address of the qth row of the pth frame of the input image block B is: frame address p + row address q + pixel address L/2, where L is the pixel address; after completing the burst of one pixel row, proceed to the next pixel row bursts, so the row address is incremented by one until all pixel rows are written into memory 100.
  • each read controller 300 reads one image block correspondingly, for example, the first read controller 301 reads The image block at the position of O(x)-A', the second read controller 302 reads the image block at the position of O(x)-B', and the third read controller 303 reads the image at the position of O(x)-C' block, the fourth read controller 304 reads the image block at the position O(x)-D', and so on. Therefore, the way of image segmentation to achieve the output image is changed compared to the way of image segmentation of the input image.
  • the read controller 300 reads out the image frame from the memory 100 by means of data bursts, and transmits the output data of one pixel row in each burst, and the address of each burst is the address of the first pixel of the pixel row,
  • the burst address of the qth row of the pth frame of the output image block D is: frame address p + row address q + pixel address L*3/4. After the burst of one row of pixels is completed, the burst of the next pixel row will be performed, so The row address is incremented by one until all pixel rows have been read from memory.
  • frame rate conversion when multi-interface video data is input can be implemented, specifically:
  • the write controller sequentially writes the input data of n frames of the input image to the memory within the target clock cycle
  • the read controller writes the input data of n frames of the input image to the memory in the target clock cycle.
  • the output data of m frames of output images are sequentially read from the memory in the cycle, and then the read controller abandons reading the output images of the nm frames after the mth frame of output images;
  • n is the value obtained by dividing the frame rate of the input image by the target common divisor
  • m is the value obtained by dividing the frame rate of the output image by the target common divisor
  • the target common divisor is the frame rate of the input image and the target common divisor.
  • the common divisor is an integer value that can be equally divided by the frame rate of the input image and the frame rate of the output image at the same time.
  • the target common divisor may be the greatest common divisor between the frame rate of the input image and the frame rate of the output image.
  • the frame rate conversion is realized by controlling the number of times of reading and writing frames.
  • the clocks for data writing of the write controller 200 and data readout of the read controller 300 are kept as the same source clock, and the two clocks are kept at the same source.
  • the clock frequency and frame rate between the two maintain the same proportional relationship.
  • the write controller 200 sequentially writes the input of m frames of the input image to the memory 100 within the target clock cycle.
  • the read controller 300 sequentially reads the output data of m frames of output images from the memory 100 within the target clock cycle, and then the write controller 200 discards the input images of nm frames after the mth frame of input images.
  • the read controller 300 every time the write controller 200 writes n frames of input images, the read controller 300 reads out m frames of output images correspondingly, and discards the n-m frames of input images after the mth frame of input images.
  • the common divisors of the two include 1, 2, 5, and 10. If the common divisor of the target is determined to be 10, then the common divisor of the target is determined to be The greatest common divisor is 10, and n is determined to be 6 and m to be 5.
  • the corresponding sequence of writing image frames by the write controller 200 to the memory 100 is 1, 2, 3, 4, 5, and 6, and the read controller 300 reads from the memory 200.
  • the sequence of taking image frames is 1, 2, 3, 4, and 5, and the output image of the sixth frame is discarded.
  • the read control when the frame rate of the input image is lower than the frame rate of the output image, when the write controller sequentially writes the input data of n frames of the input image to the memory within the target clock cycle, the read control The controller reads the output data of n frames of output images from the memory correspondingly within the target clock cycle, and then for the last mn frames of output images in the read n frames of output images, the read controller reads the output images of the n frames in the Read each time repeatedly within the target clock cycle;
  • n is the value obtained by dividing the frame rate of the input image by the target common divisor
  • m is the value obtained by dividing the frame rate of the output image by the target common divisor
  • the target common divisor is the frame rate of the input image and the target common divisor.
  • the read controller 300 every time the write controller 200 writes n frames of input images, the read controller 300 reads out m frames of output images correspondingly. In addition to sequentially reading the n frames of input images written by the write controller 200, It is also necessary to repeat the reading of the output images of the following mn frames once after reading the output image of the nth frame. For example, when the frame rate of the input image is 50fps and the frame rate of the output image is 60fps, the common divisors of the two include 1, 2, 5, and 10.
  • the target common divisor is determined to be the greatest common divisor of 10
  • determine n is 5, m is 6, and mn is 1; then the sequence of writing image frames by the corresponding write controller 200 to the memory 100 is 1, 2, 3, 4, 5, a total of 5 frames, and the read controller 300 reads from the memory 200
  • the sequence of taking image frames is 1, 2, 3, 4, 5, 5, a total of 6 frames, and the output image of the 5th frame is read repeatedly once.
  • the multiple write controllers 200 simultaneously write the input quantities of multiple image blocks of the same frame into the same sub-storage space of the memory 100, that is, the address space with the same frame address;
  • the controller 300 simultaneously reads out multiple image blocks of an image frame from the same sub-storage space of the memory 100, and the read controller 300 uses the same video timing for driving to ensure pixel-level synchronization.
  • the writing controller 200 Since the writing controller 200 is directly connected to the video input module 400, due to the influence of external input, the cable of a certain video input module 400 may be unplugged, or all the video input modules 400 suddenly stop input, etc. Use certain methods and mechanisms to deal with these situations.
  • the memory stores the next frame address of the input data, and writes the currently received input data into the corresponding next frame address of the memory.
  • the corresponding write controller 200 stops the write operation to the memory 100, and the current data in the memory 100
  • the write address also stops updating and stops at a certain address space, while the write controller 200 corresponding to other normally connected video input modules 400 is still writing data to the memory 100 normally, and the write address is also constantly updated.
  • different video input modules 400 that is, the input data writing frame address corresponding to the input interface, will be different.
  • the video cable is plugged into the input to restore the video again, the image blocks of different input interfaces will be written into different sub-storage spaces. , causing the frame to be out of synchronization.
  • the corresponding write controller 200 must follow the frame used by the write controller 200 corresponding to the video input module that is being input normally. address, for example, video input modules A and C stop video input, while video input modules B and D input normally, then the corresponding write controllers A and C stop writing image data to the memory, the frame address stays at a, and the corresponding The corresponding write controllers B and D continue to write image data to the memory, and the frame address is continuously updated and accumulated.
  • the frame address is updated to b, the video input of the video input modules A and C is restored, and the write controller is at this time.
  • a and C can no longer use frame address a, but use frame address c to start writing video data.
  • the frame address input by the write controllers B and D is also the frame address c, so the data synchronization of the video data input of each interface is realized.
  • all write controllers use the frame address corresponding to any one of the write controllers;
  • the write controller corresponding to the first recovered video input module uses the next frame address of the frame address at the last stop to write data, and the later recovered write controller follows the previous recovered write controller. frame address.
  • a plurality of The data output of the read controller and the data input of the associated multiple write controllers are kept different by a preset fixed number of frame addresses, which can also realize data synchronization when multi-interface video data is input, and image segmentation of input data.
  • the storage space of the memory 100 is divided into n sub-storage spaces, each sub-storage space stores an image of one frame, and each sub-storage space corresponds to a frame address; Corresponds to an address, which is the pixel address.
  • different write controllers 200 may write the input data belonging to the same frame of input image into the same frame address of the memory 100, or may write into different frame addresses.
  • each read controller 300 is associated with at least one write controller 200, and each read controller 300 is configured to determine the first frame address, and obtain the second frame address in the memory 100 according to the first frame address and output the acquired data of the second frame address, wherein the first frame address is the frame address in the memory 100 of the input data currently acquired by the write controller 200 associated with each read controller 300, The difference between the second frame address and the first frame address is a preset fixed number of frame addresses.
  • the read controller 300 reads the output data of the second frame address from the memory 100;
  • the first frame address and the second frame address differ by a preset fixed number of frame addresses.
  • the frame address read from the memory 100 by the read controller 300 follows the frame address of the data written to the memory 100 by the write controller 200 . Therefore, it is only necessary to determine the write controller 200 followed by the read controller 300, that is, to determine the write controller 200 associated with the read controller 300, and to determine when the associated write controller 200 is currently writing input data to the memory 100. , that is, the frame address when the read controller 300 reads the output data from the memory 100 can be determined. Therefore, different write controllers 200 are not required to write the input data belonging to the same frame of input image into the same frame address of the memory 100, and there is no restriction on the storage frame address of the same frame of input image in the memory. When reading data from the memory 100, follow the frame address of the data written by the associated write controller 200, so that each image block output from the multiple read processors 300 belongs to the same image frame, that is, the output image is simply realized. frame sync.
  • the frame address of the read controller 300 reading the image frame from the memory 100 follows the frame address of the write controller 200 written to the memory 100, and the following write controller 200 is selected according to the image span.
  • each read controller 300 is associated with at least two write controllers 200, and the image blocks corresponding to the data acquired by the read controllers 300 include the first sub-image block and the second sub-image block, and do not include The third sub-image block and the fourth sub-image block, wherein the image blocks corresponding to the input data acquired by the first write controller associated with the read controller 300 include the first and third sub-image blocks
  • the image block corresponding to the input data acquired by the second write controller associated with the read controller includes a second sub-image block and a fourth sub-image block.
  • the image block A' when the image block corresponding to the data acquired by the read controller 300 is A', the image block A' includes the left part of the image block (the first sub-image block) of the image block A of the input data. and the left part image block (second sub image block) of image block C of the input data, excluding the right part image block (third sub image block) of image block A and the right part image block (fourth sub image block) of image block C image block); and the image block A corresponding to the input data acquired by the first write controller associated with the read controller 300 includes the first sub-image block and the third sub-image block, and is related to the read controller
  • the image block C corresponding to the input data acquired by the connected second write controller includes a second sub-image block and a fourth sub-image block.
  • the read controller 300 for reading tile A' is associated with two write controllers (a write controller corresponding to the input data tile A and a write controller corresponding to the input data tile C).
  • the input data image block division method and the output data image block division method in FIG. 2 and FIG. 4 can be used to determine the write controller associated with each read controller, which will not be described here.
  • the write controller 200 associated with the read controller 300 is determined according to the correspondence between the image blocks of the image frame corresponding to the read controller 300 and the image blocks of the image frame corresponding to the write controller 200 . Wherein, when the image blocks corresponding to the read controller 300 are distributed in the image blocks of different write controllers 200 , the write controller 200 including each part of the image block corresponding to the read controller 300 belongs to the read controller 300 . Associated write controller 200 .
  • the image block A' corresponding to the output data of the read controller 300 is distributed in the input image block A and the image block C of the write controller 200, so the read control corresponding to the image block A'
  • the read frame address of the controller 300 follows the write frame address of the write controller 200 corresponding to the image block A and the image block C respectively, and the write controllers 200 followed by different parts of the image block are different.
  • the frame address of the read controller 300 follows the frame address of the write controller 200 corresponding to the image block A.
  • the frame address of the read controller follows the image block.
  • the following method is to make the second frame address of the memory 100 read by the read controller 300 and the first frame address written to the memory 100 by the write controller 200, and the difference between the two frame addresses is a preset fixed number frame address. That is, the frame address read by the read controller 300 is the frame address written by the write controller 200 minus a preset fixed number of frame address values s (s is one of 1, 2, . . . n-1) One, n is the total number of sub-storage spaces), where s is preferably 2.
  • the above-mentioned storage method of the image data can realize the conversion between the image segmentation method of the input data and the image segmentation method of the required data, specifically:
  • Each video input module 400 corresponds to a write controller 200
  • each write controller 200 corresponds to an image block of the input image, and is responsible for writing the input data input by the corresponding video input module 400 into the storage space of the storage module 100
  • Each read controller 300 corresponds to an image block of the output image, and reads the output data from the storage space of the storage space 100 according to the following manner.
  • the write controller 200 writes the input data of the input image into the memory in a data burst mode, and transmits data of one row of pixels in a burst; similarly, the read controller 300 uses a data burst mode to write the image frame from The memory 100 is read out, and the output data of one pixel row is transmitted in bursts each time.
  • the specific manners of data writing and data reading are the same as those in the first embodiment, and will not be described in detail here.
  • the writing controller writes the image block A into the sub-storage space with the frame address 4, and writes the image block B and the image block C into the sub-storage space with the frame address 4.
  • Write the sub-storage space with the frame address 3 and write the image block D into the sub-storage space with the frame address 5.
  • the read controller 300 follows the frame address of the write controller. Assuming that the preset fixed number of frame address values s that are different from the follow addresses are 2, the read controllers A' and B' follow the write control when reading the upper half of the image.
  • Read and write are done in bursts. Each burst corresponds to writing or reading a row of pixel data. Each burst of a row is completed, the row address of the burst is incremented by one, until the whole frame of image reading and writing is completed.
  • the image frame read by the read controller 300 is 2 frames less than the image frame corresponding to the input image of the write controller 200, that is, each image block of the output image frame corresponds to the second input frame image, and the image frame segmentation method is realized at the same time. transformation.
  • frame rate conversion when multi-interface video data is input can be implemented, specifically:
  • the read controller 300 is further configured to: after acquiring the data at the second frame address in the memory 100, when acquiring data from the memory 100 again, if the write controller 200 associated with the read controller 300 is currently The frame address of the acquired input data in the memory 100 is still kept as the first frame address, and the data of the second frame address is repeatedly acquired.
  • the value of the preset fixed number of frame addresses differing from the following addresses is s.
  • the frame rate of the written image is less than the frame rate of the read image, after the read controller 300 completes reading one frame of image, if the write control The frame address written by the controller 200 has not changed, so the frame address of the next frame read by the read controller 300 remains unchanged, so that the repeated reading of the frame can be completed.
  • the frame address written by the write controller 200 may have been updated multiple times ( If it is twice); based on this, when the read controller 300 reads the next frame, the read frame address needs to increase the preset fixed number of frame address values s, and the output data of the frame address in the middle is discarded . For example, when s is 2, when the read controller 300 reads the next frame, the read frame address is increased by 2 frame addresses, and the middle frame is discarded.
  • the read controller 300 reads the output data of the second frame address from the memory 100, and then reads the output data from the memory 100 again, if the write controller 200 associated with the read controller 300 writes to the memory 100 When the frame address of the written input data still remains at the first frame address, the output data of the output image at the second frame address is repeatedly read.
  • the read controller 300 Before the read controller 300 reads the output data of the second frame address from the memory 100, if the output data that also includes the third frame address in the memory 100 is not read, it will discard the same, that is, give up the acquisition of the third frame address. output data; wherein, the time when the write controller 200 associated with the read controller 300 sends the input data corresponding to the third frame address is before the time when the input data corresponding to the second frame address is sent; that is, the third frame The frame address difference between the address and the first frame address is greater than the preset number.
  • the clocks at both ends of the write controller 200 and the read controller 300 are not required to be synchronized, and the ratio of the clock frequency and the frame rate at both ends is not required to be the same.
  • the write controller 200 Since the read controller 300 follows the frame address of the write controller 200 according to the image block, the write controller 200 is not required to write different image blocks of the same frame into the same sub-storage space, so multiple image blocks of the same frame are written into the same sub-storage space.
  • the frame address can vary. In this way, there is no need for frame address synchronization between different video input modules. When the video input of a video input module stops, the frame address also stops updating. When it resumes again, it can continue to start at the frame address when it was stopped.
  • the read controller 300 Since the frame address of the write controller 200 is likely to be changed and updated during the read controller 300 reads a certain frame of image, the read controller 300 needs to change the frame corresponding to the write controller 200 at the beginning of each frame of image reading. The address is latched, and then the processing of subtracting a preset fixed number of frame address values s is performed. According to the frame address currently written by the write controller 200, the frame address to be read is determined. In the process of reading, the latched address is uniformly used, so that even if the frame address of the write controller 200 changes, the frame address of the read controller 300 will not be affected.
  • the read controller 300 in the process of reading the output data of the second frame address from the memory 100 by the read controller 300, if the frame address of the input data currently written to the memory 100 by the write controller 200 associated with the read controller 300 is changed from the first frame address The frame address is changed to the fourth frame address, and the read controller 300 keeps reading the output data of the second frame address until the output data of the second frame address is read.
  • the image data processing apparatus utilizes multiple write controllers and multiple read controllers to respectively write and read input data of each frame in the memory, which can ensure the accuracy of multi-interface video data input.
  • An embodiment of the present disclosure further provides a display device, where the display device includes the image data processing device of any of the foregoing implementation structures.
  • the display device further includes a display module, which is connected to the image data processing device, and the output data read by the read controller 300 of the image data processing device can be input to the display module for displaying the input from the video input module. video image.
  • the image data processing device converts the data input by the video input module into data that can be input to the display module, and ensures the data synchronization when the multi-interface video data is input.
  • FIG. 8 Another aspect of the embodiments of the present disclosure further provides an image data processing method, as shown in FIG. 8 , including:
  • the multiple write controllers respectively acquire the input data of the multiple image blocks into which the multi-frame input image is divided, wherein each write controller acquires the input data of one image block in the multiple image blocks into which the input image of each frame is divided input data, and determine the frame address of the input data stored in the memory, and send the input data to the memory according to the determined frame address;
  • the plurality of read controllers respectively determine the first frame address, obtain the data of the second frame address in the memory according to the first frame address, and output the obtained data of the second frame address, wherein all the The first frame address is the frame address of the input data currently acquired by the write controller associated with each read controller, and the difference between the second frame address and the first frame address is a preset fixed number frame address; wherein each of the read controllers is associated with at least one of the write controllers.
  • the read controller reads data from the memory following the associated write process.
  • the frame address of the data written by the controller can make each image block output from multiple read controllers belong to the same image frame, that is, the output image frame synchronization can be simply realized, and the image segmentation method of the input data and the required data can be realized.
  • the transformation of the image segmentation method and the transformation of the frame rate can be realized.

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Abstract

本公开提供一种图像数据处理装置、方法及显示装置。该系统包括：多个写控制器，与输入图像被划分的多个图像块一一对应，被配置为获取每一帧输入图像中相对应的图像块的输入数据，并确定输入数据在存储器中存储的帧地址，根据所确定的帧地址向存储器写入输入数据；多个读控制器，每一读控制器分别与输出图像被划分的其中一个图像块对应，读控制器被配置为确定每一帧输出图像中相对应的图像块的输出数据在所述存储器中存储的帧地址，根据所确定的帧地址从存储器读出输出数据。

Description

图像数据处理装置、方法及显示装置
本公开要求中国在先申请，申请日为2020年7月30日，申请号为202010750943.1专利申请的优先权。
技术领域
本公开涉及显示技术领域，尤其是指一种图像数据处理装置、方法及显示装置。
背景技术
在视频显示系统中，为了提升用户的视觉享受品质，视频的分辨率在不断提高，比如分辨率为4096×2160像素的4K高清视频，或分辨率为7680×4320像素的8K超高清视频等，使得视频需要传输和显示的数据流量随其分辨率的提高而不断增加，导致高清视频和超高清视频需要传输和显示的数据流量较为巨大。因此，在高清视频或超高清视频从源端到显示设备的传输过程中，需要同时使用多个视频接口对视频进行多路传输。
在超高分辨率的视频通过多个视频接口输入到系统中时，不同接口输入的视频到达系统内需要完成视频数据的同步、输入数据的图像分割方式与所需要数据的图像分割方式的变换以及帧率变换等。
发明内容
本公开技术方案的目的是提供一种图像数据处理装置、方法及显示装置，能够保证多接口视频数据输入时的数据同步、输入数据的图像分割方式与所需要数据的图像分割方式的变换以及帧率变换。
本公开实施例提供一种图像数据处理装置，其中，包括：
多个写控制器，被配置为分别获取多帧输入图像被划分的多个图像块的输入数据，其中，每一所述写控制器被配置为获取每一帧输入图像被划分的多个图像块中的一个图像块的输入数据，并确定所述输入数据在存储器中存储的帧地址，根据所确定的帧地址向所述存储器发送所述输入数据；
多个读控制器，其中，每一所述读控制器与至少一所述写控制器相关联， 每一所述读控制器被配置为确定第一帧地址，根据所述第一帧地址获取所述存储器中为第二帧地址的数据，并输出所获取的为第二帧地址的数据，其中，所述第一帧地址是与每一所述读控制器相关联的所述写控制器当前获取的输入数据在所述存储器中的帧地址，所述第二帧地址与所述第一帧地址之间相差预设固定数量个帧地址。
可选地，所述的图像数据处理装置，其中，每一所述读控制器与至少两个所述写控制器相关联，所述读控制器所获取的数据相对应的图像块，包括第一子图像块和第二子图像块，且不包括第三子图像块和第四子图像块，其中，与所述读控制器相关联的第一写控制器所获取的输入数据相对应的图像块包括所述第一子图像块和第三子图像块，与所述读控制器相关联的第二写控制器所获取的输入数据相对应的图像块包括所述第二子图像块和第四子图像块。
可选地，所述的图像数据处理装置，其中，所述读控制器被配置为：获取所述存储器中为第二帧地址的数据后，再次从所述存储器获取数据时，若与所述读控制器相关联的所述写控制器当前获取的输入数据在所述存储器中的帧地址仍保持为所述第一帧地址，则重复获取为所述第二帧地址的数据。
可选地，所述的图像数据处理装置，其中，所述读控制器被配置为：从所述存储器获取为第二帧地址的数据之前，若所述存储器内还包括为第三帧地址的数据未被获取，则放弃获取为所述第三帧地址的数据，其中，与所述读控制器相关联的所述写控制器发送所述第三帧地址对应的输入数据的时间在发送所述第二帧地址对应的输入数据的时间之前。
可选地，所述的图像数据处理装置，其中，所述图像数据处理装置还包括：
检测模块，被配置为检测输入至每一所述写控制器的输入数据是否为异常数据；
第一图像填补模块，与所述检测模块和所述读控制器连接，所述第一图像填补模块被配置为：获取由每一所述读控制器输出的数据，响应于所述检测模块确定输入至所述写控制器的目标帧相对应图像块的输入数据为异常数据，将所述目标帧相对应图像块的数据以预设填补图像数据输出；或者，所述第一图像填补模块被配置为：
响应于所述检测模块确定当前输入至所述写控制器的输入数据为异常数据，所述读控制器停止获取所述存储器中的数据，所述第一图像填补模块输出 预设填补图像数据。
可选地，所述的图像数据处理装置，其中，对于所述第一图像填补模块被配置为：获取由每一所述读控制器输出的数据，响应于所述检测模块确定输入至所述写控制器的目标帧相对应图像块的输入数据为异常数据，将所述目标帧相对应图像块的数据以预设填补图像数据输出的情形，
所述第一图像填补模块还与所述写控制器连接，所述写控制器还被配置为向所述第一图像填补模块输出所述目标帧相对应图像块在所述存储器中的帧地址，所述第一图像填补模块根据所述目标帧相对应图像块在所述存储器中的帧地址，确定所述读控制器输出的所述目标帧相对应图像块的数据。
可选地，所述的图像数据处理装置，其中，所述写控制器还被配置为在向所述存储器发送所述输入数据时，若确定所述输入数据为异常数据，则根据所确定的帧地址，以预设填补图像数据代替所述输入数据发送至所述存储器，或者向所述存储器发送预设字符。
可选地，所述的图像数据处理装置，其中，所述图像数据处理装置还包括：
第二图像填补模块，与所述读控制器连接，被配置为响应于所述读控制器输出的目标帧相对应图像块的输出数据为所述预设字符，将所述目标帧相对应图像块的数据以预设填补图像数据输出。
可选地，所述的图像数据处理装置，其中，多个所述写控制器中，其中一所述写控制器在向所述存储器的目标帧地址发送所述输入数据后，若间隔预设时长未接收到所述输入数据，则在重新接收所述输入数据后，从所述存储器的所述目标帧地址的下一个帧地址开始向所述存储器发送所述输入数据。
可选地，所述的图像数据处理装置，其中，所述读控制器在从所述存储器获取所述第二帧地址的数据的过程中，若与所述读控制器相关联的所述写控制器当前向所述存储器所发送输入数据的帧地址变更为第四帧地址，所述读控制器保持获取所述第二帧地址的数据，直至所述第二帧地址的数据获取完毕，其中，所述第四帧地址和所述第一帧地址不同。
可选地，所述的图像数据处理装置，其中，所述图像数据处理装置还包括：
仲裁器，与所述存储器、所述写控制器和所述读控制器分别连接，所述仲裁器用于配置每一所述写控制器向所述存储器发送所述输入数据的传输权限，以及配置每一所述读控制器从所述存储器读出数据的传输权限。
可选地，所述的图像数据处理装置，其中，所述图像数据处理装置还包括所述存储器，所述存储器为双倍速率存储器，且所述双倍速率存储器通过存储器控制器与所述仲裁器连接；
所述仲裁器还被配置为，当所述写控制器和所述读控制器被配置传输权限时，控制所述写控制器和所述读控制器与所述存储器控制器之间的数据传输通路连通，当所述写控制器和所述读控制器未被配置传输权限时，控制所述写控制器和所述读控制器与所述存储器控制器之间的数据传输通路断开。
可选地，所述的图像数据处理装置，其中，所述图像数据处理装置还包括：
至少两个图像数据输入接口，每一所述图像数据输入接口与至少一所述写控制器连接；所述图像数据输入接口被配置为接收每一帧输入图像的部分待处理数据，并对所述部分待处理数据进行格式转换，获得发送至与其相连接的所述写控制器的所述输入数据。
可选地，所述的图像数据处理装置，其中，不同的所述写控制器将属于同一帧输入图像的输入数据，发送至所述存储器的同一帧地址中，或者发送至所述存储器的不同帧地址中。
本公开实施例还提供一种显示装置，其中，包括显示模组和如上任一项所述的图像数据处理装置。
本公开实施例还提供一种图像数据处理方法，其中，包括：
多个写控制器分别获取多帧输入图像被划分的多个图像块的输入数据，其中，每一写控制器获取每一帧输入图像被划分的多个图像块中的一个图像块的输入数据，并确定所述输入数据在存储器中存储的帧地址，根据所确定的帧地址向所述存储器发送所述输入数据；
多个读控制器分别确定第一帧地址，根据所述第一帧地址获取所述存储器中为第二帧地址的数据，并输出所获取的为第二帧地址的数据，其中，所述第一帧地址是与每一读控制器相关联的所述写控制器当前获取的输入数据的帧地址，所述第二帧地址与所述第一帧地址之间相差预设固定数量个帧地址；其中，每一所述读控制器与至少一所述写控制器相关联。
附图说明
为了更清楚地说明本公开文本实施例或相关技术中的技术方案，下面将对 实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例一所述图像数据处理装置的结构示意图；
图2为说明输入数据的图像分割方式与所需要数据的图像分割方式的变换的原理示意图；
图3为本公开实施例二所述图像数据处理装置的结构示意图；
图4为说明输入数据的图像块分割方式与输出数据的图像块分割方式之间关系的示意图；
图5为说明第一图像填补模块进行预设填补数据输出的原理示意图；
图6a和图6b为说明采用本公开实施例所述图像数据处理装置的其中一实施方式，读写控制方法的示意图；
图7为说明采用本公开实施例所述图像数据处理装置的另一实施方式，读写控制方法的示意图；
图8为说明本公开实施例所述图像数据处理方法的流程示意图。
具体实施方式
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
为保证多接口视频数据输入时的数据同步、输入数据的图像分割方式与所需要数据的图像分割方式之间的变换以及帧率变换，本公开实施例提供一种图像数据处理装置，通过设置与输入图像被划分的图像块一一对应的多个写控制器，以及与输出图像被划分的图像块一一对应的多个读控制器，多个写控制器确定每一帧输入图像被划分的多个图像块中一个图像块的输入数据在存储器中存储的帧地址，并依据该帧地址向存储器中写入输入数据；读控制器确定相对应的图像块的输出数据在所述存储器中存储的帧地址，根据所确定的帧地址从所述存储器读出所述输出数据，这样利用多个写控制器和多个读控制器，分别进行多帧输入图像在存储器中的写入和读取，能够保证多接口视频数据输入时的数据同步、输入数据的图像分割方式与所需要数据的图像分割方式之间的变换以及帧率变换。
本公开实施例中，可选地，多个写控制器的数据输入与多个读控制器的数据输出的过程中，读控制器从存储器中读取数据时跟随与之相关联的写控制器写入数据的帧地址，便可使从多个读控制器输出的各图像块属于同一图像帧，即简单地实现输出图像帧同步。
具体地，本公开实施例所述图像数据处理装置，如图1所示，包括：
多个写控制器200，被配置为分别获取多帧输入图像被划分的多个图像块的输入数据，其中，每一写控制器200被配置为获取每一帧输入图像被划分的多个图像块中的一个图像块的输入数据，并确定所述输入数据在存储器100中存储的帧地址，根据所确定的帧地址向存储器100发送所述输入数据；
多个读控制器300，其中，每一读控制器300与至少一写控制器200相关联，每一读控制器300被配置为确定第一帧地址，根据第一帧地址获取存储器100中为第二帧地址的数据，并输出所获取的为第二帧地址的数据，其中，第一帧地址是与每一读控制器300相关联的写控制器200当前获取的输入数据在存储器100中的帧地址，第二帧地址与第一帧地址之间相差预设固定数量个帧地址。
本公开实施例中，可选地，写控制器200与读控制器300可以分别为现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)芯片，分别对应形成为写控制器200与读控制器300的FPGA芯片与存储器100通过电路线路连接。
本公开实施例中，写控制器200的数量由输入图像被划分的多个图像块的分割数量确定，读控制器300的数量由输出图像中被划分的多个图像块的分割数量确定。
举例说明，如图2所示，输入图像可以通过4个HDMI2.0接口输入至写控制器200，每一帧输入图像依据“田”字型分割方式被划分为四个图像块A、B、C和D；当输入显示模组时，需要输入依据“川”字型分割的图像，每一帧输入图像依据“川”字型分割方式被划分为四个图像块A’、B’、C’和D’，也即需要将依据“田”字型分割的输入数据，变换为依据“川”字型分割的输出数据，以能够输入至显示装置，实现输入数据的图像分割方式的变换。
具体地，结合图4所示，所输出的四个图像块A’、B’、C’和D’中，图像块A’对应输入图像的图像块A的左部分图像块和图像块C的左部分图像块； 图像块B’对应输入图像的图像块A的右部分图像块和图像块C的右部分图像块；图像块C’对应输入图像的图像块B的左部分图像块和图像块D的左部分图像块；图像块D’对应输入图像的图像块B的右部分图像块和图像块D的右部分图像块。
基于该实施方式，本公开实施例中，写控制器200的数量为四个，每一帧输入图像中相对应的图像块的输入数据被输入至其中一写控制器200，参阅图1和图2所示，每一帧输入图像中的图像块A、图像块B、图像块C和图像块D的输入数据分别被输入至写控制器200中的第一写控制器201、第二写控制器202、第三写控制器203和第四写控制器204；每一帧输出图像中的图像块A’、图像块B’、图像块C’和图像块D’的输出数据分别被第一读控制器301、第二读控制器302、第三读控制器303和第四读控制器304从存储器100读出，以能够进一步输入至显示模组，用于图像显示。
因此，采用本公开实施例所述图像数据处理装置，通过上述实施结构，能够实现输入数据的图像分割方式的变换。
由于多个写控制器200向存储器100写入输入数据，以及多个读控制器300从存储器100读出输出数据分别能够为独立控制，通过控制写入和读出时的时序即能够保证多接口视频数据输入时的数据同步和帧率变换。
以下结合本公开实施例所述图像数据处理装置，对本公开实施例所述图像数据处理装置实现上述的数据同步、输入数据的图像分割方式与所需要数据的图像分割方式的变换以及帧率变换的具体结构和方式进行详细说明。
参阅图3所示，本公开实施例所述图像数据处理装置，包括存储器100、多个写控制器200和多个读控制器300，可选地，还包括：视频输入模块400、仲裁器500、时序信号发生器600、检测模块700、第一图像填补模块800、存储器控制模块900和视频输出模块1000。
其中，视频输入模块400的数量为至少两个，每一视频输入模块400对应一个视频输入接口，负责依据视频输入接口的协议标准接收每一帧输入图像的部分待处理数据。具体地，所输入视频的每一帧输入图像依据视频输入模块400的数量被划分为几个部分的待处理数据，分别由对应的视频输入模块400输入，通过视频输入模块400传输至对应的写控制器200。
其中，输入至每一视频输入模块400的部分待处理数据的视频的格式可能 与写控制器200能接收和处理的数据的格式不同。因此视频输入模块400被配置为接收每一帧输入图像的部分待处理数据，并对该部分待处理数据进行格式转换，获得发送至相对应的写控制器200的输入数据。
例如，输入至每一视频输入模块400的视频的数据格式可能为RGB、YCbCbr444、YCbCr422和YCbCr420的其中一种，位深可能为8位、10位或者12位等，视频输入模块400能够将所输入的为上述格式的部分待处理数据，恢复为标准的视频时序和数据(如包括帧同步信号、行同步信号、视频数据使能信号和视频数据)，并将该部分待处理数据的格式统一为RGB、预设位深(如为10bit位深)的格式。
本公开实施例中，视频输入模块400可以支持的视频接口包括但不限于高清多媒体接口(High Definition Multimedia Interface，HDMI)、显示接口(DisplayPort，DP)和低电压差分信号(Low-Voltage Differential Signaling，LVDS)版本等。
本公开实施例中，写控制器200与视频输入模块400连接，其中一个视频输入模块400与至少一个写控制器200连接，写控制器200的数量由输入图像被划分的多个图像块的分割数量确定，每一写控制器200由所连接的至少一个视频输入模块400获取每一帧输入图像中相对应的图像块的输入数据。
可选地，写控制器200和视频输入模块400的数量相同，多个写控制器200与多个视频输入模块400一一对应地连接，但并不以此为限，具体以至少一视频输入模块400的数据输出能够满足写控制器200的相对应的图像块的数据输入为设定条件。
具体地，写控制器200将接收的相对应的图像块的输入数据以像素行为单位进行数据格式转换，其中每次进行格式转换的像素行数据可以称为突发格式数据，并指定输入数据的图像帧、行和像素在存储器100中的地址，并以突发(也可以称为一次触发)的方式向存储器100写入相对应的图像块的其中一像素行的输入数据。读控制器300指定从存储器100中读出所需要读取的图像帧、行和像素在存储器100中的地址，可选地以突发的方式从存储器100读出输出数据，每次突发从存储器100读出相对应的图像块的其中一像素行的输出数据。读控制器300所读出的输出数据通过视频输出模块1000输出至显示模组的驱动芯片，以在显示模组上显示所输出图像。
本公开实施例中，可选地，所述图像数据处理装置还包括仲裁器500，与存储器100、写控制器200和读控制器300分别连接，该仲裁器500用于配置每一写控制器200向存储器100写入输入数据的传输权限，以及配置每一读控制器300从存储器100读出输出数据的传输权限。
具体地，被配置传输权限的写控制器200获得向存储器100写入输入数据的传输权限，能够向存储器100写入输入数据；被配置传输权限的读控制器300获得从存储器100读取输出数据的传输权限，能够从存储器100中读出输出数据。
本公开实施例中，可选地，存储器100为双倍速率(Double Data Rate，DDR)存储器，且DDR存储器通过存储器控制模块900与仲裁器500连接，其中写控制器200和读控制器300被配置传输权限时与存储器控制模块900之间的数据传输通路连通，写控制器200和读控制器300未被配置传输权限时与存储器控制模块900之间的数据传输通路断开。
采用该实施结构，仲裁器500负责将存储器100、写控制器200、读控制器300和存储器控制模块900通过具有突发功能的总线连接在一起，并且通过一定的仲裁机制对所接入的每一写控制器200和每一读控制器300进行仲裁，获得仲裁的写控制器100和读控制器300被配置传输权限，能够直接与存储器控制模块900建立连接，独立占用与存储器控制模块900之间的数据传输通路。
可选地，写控制器200和读控制器300分别与仲裁器500之间的连接为支持数据突发功能的总线，可选的为采用AXI4-MM总线，其中，写控制器200与读控制器300的设置端为总线主Master端，仲裁器500的设置端为总线从Slave端。
写控制器200和读控制器300分别与仲裁器500之间的总线类型，与存储器控制模块900和仲裁器500之间的总线类型相同。
可选地，仲裁器500采用循环均等的方式配置多个写控制器200和多个读控制器300的传输权限，即每一写控制器200和每一读控制器300在获得传输权限上是平等的，均等循环地获取传输权限。
具体地，写控制器200以像素行为单位进行数据突发，根据像素行像素数据的数量决定突发写入的数据位宽、数据长度等参数，并确定每一像素行的输入数据在存储器100中存储的地址，在获得向存储器100写入数据的传输权限 后，向存储器100写入其中一像素行的输入数据，在完成一次突发后释放该传输权限。其中一实施方式，每次突发写入的数据为一像素行的像素数据；另一实施方式，每次突发写入的数据为一像素行的部分像素数据，一像素行的像素数据可以通过多次(如为两次)突发写入过程，写入至存储器100。
同理，读控制器300以像素行为单位进行数据突发，根据像素行像素数据的数量决定突发读取的数据位宽、数据长度等参数，并确定每一像素行的输出数据在存储器100中存储的地址，在获得从存储器100读取数据的传输权限后，从存储器100读取其中一像素行的输出数据，在完成一次突发后释放该传输权限。其中一实施方式，每次突发读取的数据为一像素行的像素数据；另一实施方式，每次突发读取的数据为一像素行的部分像素数据，一像素行的像素数据可以通过多次(如为两次)突发读取过程，从存储器100读取数据。
本公开实施例中，可选地，在存储器100的每一子存储空间内，输入数据依据像素行进行存储，每一像素行对应一行地址，每一像素行内的每一像素对应一像素地址。
存储器100内的存储空间被进行划分和组织，存储空间被划分为多个子存储空间，每一子存储空间对应一个帧地址，进一步地每一子存储空间内，包括对应像素行的行地址以及对应每一像素的像素地址。因此，存储器100内的存储空间包括帧地址(Frame Address，FA)、行地址(Line Address，LA)和像素地址(Pixel Address,PA)。
具体地，存储器100的存储空间被划分为n个子存储空间，每个子存储空间存放一帧的图像，每个子存储空间对应一个帧地址；例如：第1个子存储空间对应的帧地址为1，第2个子存储空间对应的帧地址为2，…，依此类推，第n个子空间对应的帧地址为n。可选地，在每个子存储空间内，输入数据按照像素行的方式进行存储，每个像素行对应着一个行地址，比如输入数据的第1像素行对应的行地址为0，第2像素行对应的行地址为1，…，依此类推，第H行对应的行地址为H-1。可选地，每一像素行内的每个像素分别对应一个地址，为像素地址。例如，每一像素行的第1个像素的像素地址为0，第2个像素的像素地址为1，…，依此类推，第L个像素的地址为L-1。
可选地，帧地址、行地址和像素地址与存储器100的物理地址存在一定的映射关系，且帧地址、行地址和像素地址分别与存储器100的映射关系不同， 比如帧地址可以映射为存储器100的存储库Bank地址，行地址可以映射为存储器100的行Line地址等。
本公开实施例中，存储器控制模块900负责与存储器100进行接口，负责完成存储器100的初始化及管理，将总线突发数据转换为符合存储器100接口要求的数据，并执行该些数据在存储器100中的突发存取。
本公开实施例中，可选地，所述图像数据处理装置还包括时序信号发生器600，与每一读控制器300连接，该时序信号发生器600被配置为向每一读控制器300输入时序信号，使读控制器300响应该时序信号，输出从存储器100读出的所述输出数据。
采用该实施结构，通过时序信号发生器600向每一读控制器300输入时序信号，使读控制器300根据该时序信号，将所读取的输出数据传输至显示模组，以保证读控制器300将输出数据传输至显示模组的时序能够符合显示模组的数据输入频率要求，保证从多个读控制器300读出的属于同一帧的多个输出数据传输至显示模组的时间同步。
本公开实施例中，可选地，如图3所示，所述图像数据处理装置还包括检测模块700和第一图像填补模块800。
其中，检测模块700，被配置为检测输入至每一写控制器200的输入数据是否为异常数据；
第一图像填补模块800，与检测模块700和每一读控制器300连接，该第一图像填补模块800被配置为：获取由每一读控制器300输出的数据，在检测模块700确定输入至写控制器200的目标帧相对应图像块的输入数据为异常数据时，将目标帧相对应图像块的数据以预设填补数据输出；或者，第一图像填补模块800被配置为：
响应于检测模块700确定当前输入至写控制器200的输入数据为异常数据，读控制器300停止获取存储器100中的数据，第一图像填补模块800输出预设填补图像数据。可选地，检测模块700负责检测由每一视频输入模块400输入的输入数据是否为异常数据，检测的内容包括视频输入模块400是否在线(即对应的视频输入模块400是否连接了播放源)、输入数据的分辨率和帧率是否异常等。
其中，当检测模块700确定输入至写控制器200的目标帧相对应图像块的 输入数据为异常数据时，第一图像填补模块800将目标帧相对应图像块的输出数据以预设填补数据输出，例如将目标帧相对应图像块的显示区域填充为黑色，以避免将错误格式的图像帧显示出来，避免画屏、闪烁和错位等错误图像显示的情况。
可选地，对于第一图像填补模块800被配置为：获取由每一读控制器300输出的数据，响应于检测模块700确定输入至写控制器200的目标帧相对应图像块的输入数据为异常数据，将所述目标帧相对应图像块的数据以预设填补图像数据输出的情形，第一图像填补模块800还与写控制器200连接，写控制器200还被配置为向第一图像填补模块800输出目标帧相对应图像块在存储器100中的帧地址，第一图像填补模块800根据所述目标帧相对应图像块在存储器100中的帧地址，确定读控制器300输出的所述目标帧相对应图像块的数据。
采用上述方式，第一图像填补模块800根据写控制器200确定为异常数据的目标帧在存储器100中的帧地址，并依据读控制器300从存储器100中读取数据时跟随与之相关联的写控制器200写入数据的帧地址的形式，确定读控制器300输出的目标帧相对应图像块的数据，进行预设填补数据输出，如将目标帧相对应图像块的显示区域填充为黑色，以避免将错误格式的图像帧显示出来。
另一实施方式，第一图像填补模块800响应于检测模块700确定当前输入至写控制器200的输入数据为异常数据，使读控制器300在当前即停止获取存储器100中的数据，并输出预设填补图像数据，直至检测模块700确定输入至写控制器200的输入数据为正常数据。采用该方式，第一图像填补模块800能够通过简单地方式确定读控制器300进行数据输出时需要进行预设填补数据输出的数据，并能够达到有效地避免将错误格式的图像帧显示出来的效果。
因此，本公开实施例中，检测模块700可以检测目标帧相对应图像块的部分输入数据为异常数据，在检测到目标帧相对应图像块的部分输入数据为异常数据时，第一图像填补模块800可以将读控制器300输出画面对应图像块中，检测到错误数据的像素以预设填补数据输出，第一图像填补模块800根据检测模块700的检测结果可以将对应位置的图像填补为黑色画面，例如，结合图4和图5所示，在分割方式不变的情况下，当由图像块A输入的视频分辨率不符合预期，如分辨率或帧率异常时，第一图像填补模块800会将读控制器300输出画面对应图像块A’的位置(也即左上四分之一)填补为黑色画面。
本公开实施例所述图像数据处理装置，另一实施方式，写控制器200还被配置为在向存储器100发送输入数据时，若确定输入数据为异常数据，则根据所确定的帧地址，以预设填补图像数据代替所述输入数据发送至所述存储器，或者向所述存储器发送预设字符。
采用该实施方式，在输入数据为异常数据时，通过写控制器200向存储器100中写入预设填补图像数据，使读控制器300直接读取并输出该预设填补图像数据，在输出图像时进行预设图像填补；可选地，在输入数据为异常数据时，写控制器200也可以向存储器100中写入预设字符，使读控制器300根据所读取的预设字符，将目标帧相对应图像块的数据以预设填补图像数据输出，同样能够达到有效地避免将错误格式的图像帧显示出来的效果。
基于上述实施方式，可选地，所述图像数据处理装置还包括：
第二图像填补模块(图中未显示)，与所述读控制器连接，被配置为响应于所述读控制器输出的目标帧相对应图像块的输出数据为所述预设字符，将所述目标帧相对应图像块的数据以预设填补图像数据输出。根据以上，采用本公开实施例所述图像数据处理装置，利用写控制器和读控制器，能够控制输入图像帧和输出图像帧在存储器中的存取地址、存取时机和存取速度，实现多接口视频数据输入时的数据同步、输入数据的图像分割方式与所需要数据的图像分割方式之间的变换以及帧率变换。
以下对采用本公开实施例所述图像数据处理装置，能够实现多接口视频数据输入时的数据同步、输入数据的图像分割方式与所需要数据的图像分割方式之间的变换以及帧率变换的具体实施过程进行详细说明。
结合图3所示，该实施方式中，不同的写控制器200将属于同一帧输入图像的输入数据，写入存储器100的同一帧地址中，且写控制器200向存储器100写入输入数据的输入图像帧的过程，与读控制器300从存储器100读出输出数据的输出图像帧的过程相互没有关联，也即图像数据在存储器100中的写入过程和读取过程相互分离。
具体地，如图6a和图6b所示，存储器100的存储空间被划分为n个子存储空间，也即为子存储空间S1、S2，¨¨¨，Sn，每个子存储空间存放一帧的图像，每个子存储空间对应一个帧地址；可选地，每一子存储空间内的每一行地址分别对应一个像素行的行地址；可选地，每一像素行内的每个像素分别 对应一个地址，为像素地址。可选地，帧地址、行地址和像素地址与存储器100的物理地址存在一定的映射关系，且帧地址、行地址和像素地址分别与存储器100的映射关系不同，比如帧地址可以映射为存储器100的Bank地址，行地址可以映射为存储器100的Line地址等。
该实施方式中，图像数据在存储器100中的写入过程和读取过程相互分离，也即不同的写控制器200将属于同一帧输入图像不同图像块的输入数据，写入存储器100的同一帧地址中，即同一帧地址对应的空间；在此基础上，多个读控制器300将属于同一帧输出图像的不同图像块由存储器100的同一帧地址中读出。
写控制器200以帧地址依次递增的方式，依次向存储器100写入每一帧输入图像的输入数据；读控制器300以帧地址依次递增的方式，依次从存储器100读出每一帧输出图像的输出数据，且写控制器200触发写入的时钟频率与读控制器300触发读取的时钟频率同步。
如图6a所示为写控制器200写入到存储器100中的图像帧的结构形式图，以输入图像依据“田”字型分割方式被划分为四个图像块为例，n个子存储空间S1、S2，¨¨¨，Sn中，每一子存储空间对应一帧地址，用于存储一帧图像的输入数据，且所存储一帧图像的输入数据依据像素行排列，使每一帧地址内分别包括与四个图像块A、B、C和D对应的输入数据。其中，四个写控制器200与四个图像块一一对应，每一写控制器200对应分别读取其中一图像块的输入数据，将相应图像块的输入数据写入存储器100的相对应图像块的存储空间中。具体地，帧地址为N内所存储对应图像块A、B、C和D的输入数据分别表示为I(x)-A、I(x)-B、I(x)-C和I(x)-D。其中，x为1至n中的任一整数，n为所存储图像的最大帧数。
图6b所示为读控制器300从存储器100读取图像帧的结构形式图，以输出图像依据“川”字型分割方式被划分为四个图像块为例，四个读控制器300与四个图像块一一对应，该四个读控制器300分别对应依据图6b所示划分的图像块，由相应的图像块内读出存储数据；其中，四个读控制器300所分别读取的帧地址为N内的输出数据分别表示为O(x)-A’、O(x)-B’、O(x)-C’和O(x)-D’。其中，x为1至n中的任一整数，n为所存储图像的最大帧数。
具体地，每一写控制器200向存储器100写入输入数据的帧地址以1递增， 以像素行为单位进行数据突发，向存储器100写入一帧输入图像的每一像素行的输入数据后，对应的帧地址加一，进行下一帧输入图像的数据写入；同理，读控制器300从存储器100读取输出数据的帧地址以1递增，以像素行为单位进行数据突发，从存储器100读取一帧输出图像的输出数据后，对应的帧地址加一，进行下一帧输出图像的数据读出。
基于上述的图像数据的存储方式，能够实现输入数据的图像分割方式与所需要输出数据的图像分割方式之间的变换，具体为：
该实施方式中，如图3所示，每一视频输入模块400对应一个写控制器200，每一写控制器400负责将相对应的视频输入模块400输入的输入数据写入到存储模块100的存储空间中，如图6a所示并结合图3，第一写控制器201可以将对应的视频输入模块400输入的输入数据存储在I(x)-A位置上，第二写控制器202将对应的视频输入模块400输入的输入数据存储在I(x)-B位置上，第三写控制器203将对应的视频输入模块400输入的输入数据存储在I(x)-C位置上，第四写控制器204将对应的视频输入模块400输入的输入数据存储在I(x)-D位置上，以此类推，其中，x为1至n中的任一整数，n为所存储图像的最大帧数。
可选地，写控制器200使用数据突发的方式将输入图像的输入数据写入存储器中，每次突发传输一行像素的数据，每次突发的地址为像素行第一个像素的地址，比如输入图像块B第p帧第q行突发的地址为：帧地址p+行地址q+像素地址L/2，其中L为像素地址；完成一个像素行的突发后，进行下一个像素行的突发，所以行地址加一，直到所有的像素行都被写入存储器100中。
图像帧写入存储器100中后，再由读控制器300从存储器100中读出，如图6b所示，每一读控制器300对应读取一个图像块，例如第一读控制器301读取O(x)-A’位置的图像块，第二读控制器302读取O(x)-B’位置的图像块，第三读控制器303读取O(x)-C’位置的图像块，第四读控制器304读取O(x)-D’位置的图像块，以此类推。因此，实现输出图像的图像分割方式与输入图像的图像分割方式相比发生改变。
同样，读控制器300使用数据突发的方式将图像帧由存储器100中读出，每次突发传输一像素行的输出数据，每次突发的地址为像素行第一个像素的地址，比如输出图像块D第p帧第q行突发的地址为：帧地址p+行地址q+像素 地址L*3/4，完成一行像素的突发后，便进行下一个像素行的突发，所以行地址加一，直到所有的像素行都被从存储器中读出。
上述实施方式中，能够实现写入图像块和读取图像块不同时的图像数据的写入和读取，从而能够完成图像分割方式的变换。
该实施方式中，能够实现多接口视频数据输入时的帧率变换，具体为：
在输入图像的帧率大于输出图像的帧率时，所述写控制器在目标时钟周期内依次向所述存储器写入n帧输入图像的输入数据时，所述读控制器在所述目标时钟周期内对应依次从所述存储器读出m帧输出图像的输出数据，之后所述读控制器放弃读取第m帧输出图像之后的n-m帧的输出图像；
其中，n为输入图像的帧率与目标公约数相除所获得数值；m为输出图像的帧率与所述目标公约数相除所获得数值；所述目标公约数为输入图像的帧率与输出图像的帧率之间的公约数。需要说明的是，公约数也即为能够被输入图像的帧率与输出图像的帧率同时均整除的整数值。可选地，目标公约数可以为输入图像的帧率与输出图像的帧率之间的最大公约数。
具体地，帧率变换是通过读写帧的次数控制来实现的，该实施方式中，保持写控制器200的数据写入和读控制器300的数据读出的时钟为同源时钟，并且两者之间的时钟频率和帧率保持为同样的比例关系。
根据上述的实施方式，需要确定输入图像的帧率和输出图像的帧率的目标公约数，将输入图像的帧率除以该目标公约数，获得对应输入图像的帧率的数值n；将输出图像的帧率除以该目标公约数，获得对应输出图像的帧率的数值m。将n与m进行比较，也即将输入图像的帧率与输出图像的帧率进行比较，在n大于m时，写控制器200在目标时钟周期内依次向存储器100写入m帧输入图像的输入数据时，读控制器300在目标时钟周期内对应依次从存储器100读出m帧输出图像的输出数据，之后写控制器200丢弃第m帧输入图像之后的n-m帧的输入图像。
具体地，也即为写控制器200每写入n帧的输入图像，读控制器300对应读出m帧的输出图像，丢弃第m帧输入图像之后的n-m帧的输入图像。举例说明，在输入图像的帧率为60fps，输出图像的帧率为50fps时，这两者的公约数包括1、2、5、10，如确定目标公约数为10，则确定目标公约数为最大公约数10，确定n为6，m为5，相应的写控制器200向存储器100写入图像帧的 顺序为1、2、3、4、5、6，读控制器300从存储器200读取图像帧的顺序为1、2、3、4、5，放弃读取第6帧的输出图像。
另一实施方式中，在输入图像的帧率小于输出图像的帧率时，所述写控制器在目标时钟周期内依次向所述存储器写入n帧输入图像的输入数据时，所述读控制器在所述目标时钟周期内对应依次从所述存储器读出n帧输出图像的输出数据，之后对于所读取的n帧输出图像中的最后m-n帧输出图像，所述读控制器在所述目标时钟周期内分别重复读取一次；
其中，n为输入图像的帧率与目标公约数相除所获得数值；m为输出图像的帧率与所述目标公约数相除所获得数值；所述目标公约数为输入图像的帧率与输出图像的帧率之间的公约数。
该实施方式中，写控制器200每写入n帧的输入图像，读控制器300对应读出m帧的输出图像，除了依次读取写控制器200所写入的n帧的输入图像外，还需要在读取第n帧输出图像后，重复读取后面的m-n帧输出图像一次。举例说明，在输入图像的帧率为50fps，输出图像的帧率为60fps时，这两者的公约数包括1、2、5、10，如确定目标公约数为最大公约数10，则确定n为5，m为6，m-n为1；则相应的写控制器200向存储器100写入图像帧的顺序为1、2、3、4、5，共5帧，读控制器300从存储器200读取图像帧的顺序为1、2、3、4、5、5，共6帧，重复读取第5帧的输出图像一次。
根据以上，采用上述图像数据写入和读取的方式，能够实现多接口视频数据输入时的帧率变换。
该实施方式中，能够实现多接口视频数据输入时的数据同步，具体为：
为了保障帧同步，多个写控制器200将输入的同一帧的多个图像块的输入数量同时写入存储器100的同一子存储空间，即具有相同帧地址的地址空间；同时必须要求多个读控制器300同时在存储器100的同一个子存储空间读出一幅图像帧的多个图像块，且读控制器300使用相同的视频时序进行驱动，以保证像素级的同步。
由于写控制器200与视频输入模块400直接连接，所以受外部输入的影响，可能存在某一视频输入模块400的线缆被拔掉，或全部的视频输入模块400突然停止输入等情况发生，必须使用一定的方法和机制来对应这些情况。
本公开实施例中，多个所述写控制器200中，其中一写控制器200间隔预 设时长未接收到输入数据时，在重新接收输入数据后，确定其他所述写控制器在所述存储器中存储所述输入数据的下一帧地址，将当前所接收的所述输入数据，写入所述存储器的相应下一帧地址。
具体地，当某一或某几个视频输入模块400的视频线缆被拔掉或停止输入视频信号时，对应的写控制器200停止了对存储器100的写入操作，存储器100内当前的数据写入地址也停止更新，停止在某一地址空间上，而其他正常连接的视频输入模块400对应的写控制器200还在正常的向存储器100写入数据，写地址也在不停的更新，这样不同的视频输入模块400也即输入接口对应的输入数据写入帧地址就会不同，当视频线缆再次插上恢复视频的输入后，不同输入接口的图像块就会写入不同子存储空间，造成帧的不同步，为了避免出现这种情况发生，当停止输入的接口重新恢复输入时，其对应的写控制器200必须跟随正在正常输入的视频输入模块对应的写控制器200使用的帧地址，比如视频输入模块A和C停止视频输入，而视频输入模块B和D正常输入，则相对应的写控制器A和C停止对存储器的图像数据写入，帧地址停留在a，而相对应的写控制器B和D继续对存储器进行图像数据写入，帧地址在不停的更新累加，当帧地址更新到b时，视频输入模块A和C的视频输入恢复，此时写控制器A和C不可以再使用帧地址a，而要使用帧地址c开始进行视频数据的写入。此时，写控制器B和D输入的帧地址也是帧地址c，因此，实现各接口视频数据输入的数据同步。
可选地，若全部的视频输入模块都停止输入，且全部的视频输入模块同时恢复输入，则所有写控制器使用其中任一个写控制器对应的帧地址；而当全部的视频输入模块的输入逐次恢复时，则第一个恢复的视频输入模块相对应的写控制器使用上一次停止时帧地址的下一个帧地址进行数据写入，后面恢复的写控制器跟随前面恢复的写控制器的帧地址。
因此，通过上述方式，能够实现多接口视频数据输入时的数据同步，但是写控制器200必须将属于同一帧输入图像的输入数据，写入存储器100的同一帧地址。
本公开实施例所述图像数据处理装置，除采用上述读控制器300从存储器100读取数据的过程与写控制器200向存储器100的数据写入过程相互不关联方式外，还可以采用多个读控制器的数据输出与相关联的多个写控制器的数据 输入，保持相差预设固定数量个帧地址的方式，同样能够实现多接口视频数据输入时的数据同步、输入数据的图像分割方式与所需要数据的图像分割方式之间的变换以及帧率变换的效果。
该实施方式中，存储器100的存储空间被划分为n个子存储空间，每个子存储空间存放一帧的图像，每个子存储空间对应一个帧地址；可选地，每一像素行内的每个像素分别对应一个地址，为像素地址。
在该实施方式中，不同的写控制器200可以将属于同一帧输入图像的输入数据，写入存储器100的同一帧地址，也可以写入不同的帧地址。
该实施方式中，每一读控制器300与至少一写控制器200相关联，每一读控制器300被配置为确定第一帧地址，根据第一帧地址获取存储器100中为第二帧地址的数据，并输出所获取的为第二帧地址的数据，其中，第一帧地址是与每一读控制器300相关联的写控制器200当前获取的输入数据在存储器100中的帧地址，第二帧地址与第一帧地址之间相差预设固定数量个帧地址。采用该实施方式，读控制器300相关联的写控制器200在向存储器100写入为第一帧地址的输入数据后，读控制器300从存储器100读取为第二帧地址的输出数据；
其中，所述第一帧地址与所述第二帧地址相差预设固定数量个帧地址。
基于该实施方式，读控制器300从存储器100所读取的帧地址跟随写控制器200向存储器100所写入数据的帧地址。因此，只需要确定读控制器300所跟随的写控制器200，也即确定与读控制器300所关联的写控制器200，确定相关联的写控制器200当前向存储器100写入输入数据时的帧地址，即能够确定读控制器300从存储器100读取输出数据时的帧地址。因此，不要求不同的写控制器200将属于同一帧输入图像的输入数据，写入存储器100的同一帧地址，对同一帧输入图像在存储器中的存储帧地址没有限制，通过读控制器300从存储器100中读取数据时跟随与之相关联的写控制器200写入数据的帧地址，便可实现从多个读处理器300输出的各图像块属于同一图像帧，即简单地实现输出图像帧同步。
如图7所示，举例说明，存储器100的存储空间被划分为n个子存储空间，也即为子存储空间S1、S2，¨¨¨，Sn时，采用该实施方式，对于图像帧4，图像块I(4)-A被写入帧地址为4的子存储空间、图像块I(4)-B和图像块 I(4)-C分别被写入帧地址为3的子存储空间、图像块I(4)-D被写入帧地址为5的子存储空间中。
其中，读控制器300从存储器100中读取图像帧的帧地址跟随写控制器200的写入存储器100的帧地址，根据图像跨度选择所跟随的写控制器200。
具体地，每一读控制器300与至少两个写控制器200相关联，读控制器300所获取的数据相对应的图像块，包括第一子图像块和第二子图像块，且不包括第三子图像块和第四子图像块，其中，与读控制器300相关联的第一写控制器所获取的输入数据相对应的图像块包括所述第一子图像块和第三子图像块，与读控制器相关联的第二写控制器所获取的输入数据相对应的图像块包括第二子图像块和第四子图像块。
举例说明，如图4所示，读控制器300所获取的数据相对应的图像块为A’时，图像块A’包括输入数据的图像块A的左部分图像块(第一子图像块)和输入数据的图像块C的左部分图像块(第二子图像块)，不包括图像块A的右部分图像块(第三子图像块)和图像块C的右部分图像块(第四子图像块)；而与该读控制器300相关联的第一写控制器所获取的输入数据相对应的图像块A包括该第一子图像块和第三子图像块，与该读控制器相关联的第二写控制器所获取的输入数据相对应的图像块C包括第二子图像块和第四子图像块。
因此，对应用于读取图像块A’的读控制器300与两个写控制器(对应输入数据图像块A的写控制器和对应输入数据图像块C的写控制器)相关联。
根据以上原理，结合图2和图4的输入数据图像块的划分方式和输出数据图像块的划分方式，可以确定每一读控制器所关联的写控制器，在此不再一一举例说明。
具体地，根据读控制器300所对应图像帧的图像块和写控制器200所对应图像帧的图像块之间的对应关系，确定读控制器300相关联的写控制器200。其中，读控制器300所对应的图像块分布于不同的写控制器200的图像块中时，包括读控制器300所对应的图像块的每一部分的写控制器200属于该读控制器300所关联的写控制器200。
举例说明，如图7所示，比如读控制器300的输出数据对应的图像块A’分布于写控制器200的输入的图像块A和图像块C中，所以对应图像块A’的读控制器300的读取帧地址分别跟随图像块A和图像块C所对应的写控制器 200的写入帧地址，图像块不同部分所跟随的写控制器200不同，比如在读取图像块A’的上半部分时，读控制器300的帧地址跟随图像块A所对应的写控制器200的帧地址，在读取图像块A’的下半部分时，读控制器的帧地址跟随图像块C所对应写控制器的帧地址。
具体地，跟随方式为使读控制器300所读取存储器100的第二帧地址与写控制器200向存储器100所写入的第一帧地址，两个帧地址之间相差预设固定数量个帧地址。也即，读控制器300所读取的帧地址为写控制器200所写入的帧地址减去预设固定数量个帧地址值s(s为1，2，……n-1中的其中之一，n为子存储空间的总数量)确定，其中s优选的选择2。
上述的图像数据的存储方式，能够实现输入数据的图像分割方式与所需要数据的图像分割方式之间的变换，具体为：
每一视频输入模块400对应一个写控制器200，每一写控制器200对应输入图像的一个图像块，负责将相对应的视频输入模块400输入的输入数据写入到存储模块100的存储空间中。每一读控制器300对应输出图像的一个图像块，依据上述的跟随方式，从存储空间100的存储空间中读取输出数据。
具体地，写控制器200使用数据突发的方式将输入图像的输入数据写入存储器中，每次突发传输一行像素的数据；同样，读控制器300使用数据突发的方式将图像帧由存储器100中读出，每次突发传输一像素行的输出数据。其中，具体地数据写入和数据读出的具体方式与实施方式一相同，在此不再详细说明。
采用该实施方式，举例说明，如图7所示，以写入第4帧图像为例，写控制器将图像块A写入帧地址为4的子存储空间，将图像块B和图像块C写入帧地址为3的子存储空间，将图像块D写入帧地址为5的子存储空间。读控制器300跟随写控制器的帧地址，假设跟随地址所相差的预设固定数量个帧地址值s为2，则读控制器A’和B’在读取上半部分图像时跟随写控制器A的帧地址为4-2＝2，读取下半部分图像时跟随写控制器C的帧地址为3-2＝1；则读控制器C’和D’在读取上半部分图像时跟随写控制器B的帧地址为3-2＝1，读取下半部分图像时跟随写控制器D的帧地址为5-2＝3。读写都是使用突发的方式，每次突发对应写入或读取一行的像素数据，每完成一行的突发，突发的行地址加一，直到整帧图像读写完成。因此，读控制器300读取的图像帧比对应写控制器200输入图像的图像帧少2帧，即输出图像帧的各图像块对应输入的第2 帧图像，且同时实现了图像帧分割方式的变换。
该实施方式中，能够实现多接口视频数据输入时的帧率变换，具体为：
该实施方式中，因为采用读控制器300从存储器100中读取图像帧的帧地址跟随写直接存储器存取模块200的写入存储器100的帧地址的方式，进行数据写入和读取，因此能够实现帧率变换的自动完成。
本公开实施例中，读控制器300还被配置为：获取存储器100中为第二帧地址的数据后，再次从存储器100获取数据时，若与读控制器300相关联的写控制器200当前获取的输入数据在存储器100中的帧地址仍保持为第一帧地址，则重复获取为第二帧地址的数据。
具体地，跟随地址所相差的预设固定数量个帧地址值为s，当写入图像的帧率小于读取图像的帧率时，读控制器300完成一帧图像读取后，如果写控制器200写入的帧地址还没有发生变化，所以读控制器300所读取的下一帧的帧地址保持不变，以此能够完成帧的重复读取。
另一实施方式，当写入图像的帧率大于读取图像的帧率时，在读控制器300读取一帧图像的过程中，写控制器200所写入的帧地址可能已经更新多次(如为两次)；基于此，当读控制器300读取下一帧时，所读取的帧地址需要为增加预设固定数量个帧地址值s，位于中间的帧地址的输出数据被丢弃。例如，s为2时，当读控制器300读取下一帧时，所读取的帧地址增加2个帧地址，中间一帧被丢弃。
因此，根据以上原理，读控制器300从存储器100读取为第二帧地址的输出数据后，再次从存储器100读取输出数据时，若读控制器300相关联的写控制器200向存储器100所写入的输入数据的帧地址仍保持为第一帧地址时，则重复读取为第二帧地址的输出图像的输出数据。
读控制器300从存储器100读取为第二帧地址的输出数据之前，若存储器100内还包括第三帧地址的输出数据未被读取，同丢弃也即放弃获取所述第三帧地址的输出数据；其中，与读控制器300相关联的写控制器200发送第三帧地址对应的输入数据的时间在发送所述第二帧地址对应的输入数据的时间之前；也即，第三帧地址与所述第一帧地址之间帧地址的差别大于所述预设数量。
采用该实施方式，不要求写控制器200和读控制器300两端的时钟为同步，也不需要两端的时钟频率比例和帧率的比例相同。
该实施方式中，能够实现多接口视频数据输入时的数据同步，具体为：
由于读控制器300按照图像块跟随写控制器200的帧地址，所以不要求写控制器200将同一帧的不同图像块写入相同的子存储空间，因此写入的同一帧的多个图像块的帧地址可以各不相同。这样就不需要不同视频输入模块间的帧地址同步，当某一视频输入模块的视频输入停止后，帧地址也停止更新，当再次恢复时，继续在停止时的帧地址开始即可。
由于写控制器200的帧地址很可能在读控制器300读取某一帧图像期间发生变化和更新，所以读控制器300端需要在每帧图像读取开始的时候将对应写控制器200的帧地址进行锁存，然后在进行减去预设固定数量个帧地址值s的处理，根据写控制器200当前所写入的帧地址，确定所需要读取的帧地址，在整帧的图像块读取的过程中统一使用锁存后的地址，这样即使写控制器200的帧地址发生了变化，也不会影响读控制器300的帧地址。
因此，读控制器300在从存储器100读取第二帧地址的输出数据的过程中，若读控制器300相关联的写控制器200当前向存储器100所写入输入数据的帧地址由第一帧地址变更为第四帧地址，读控制器300保持读取第二帧地址的输出数据，直至所述第二帧地址的输出数据读取完毕。
本公开实施例所述图像数据处理装置，利用多个写控制器和多个读控制器，分别进行每一帧输入数据在存储器中的写入和读取，能够保证多接口视频数据输入时的数据同步、输入数据的图像分割方式与所需要数据的图像分割方式的变换以及帧率变换。
本公开实施例还提供一种显示装置，所述显示装置包括上述任一实施结构的图像数据处理装置。
其中，所述显示装置还包括显示模组，与图像数据处理装置连接，图像数据处理装置的读控制器300所读取的输出数据能够输入至显示模组，用于显示由视频输入模块所输入的视频图像。
采用本公开实施例所述图像数据处理装置的显示装置，图像数据处理装置将由视频输入模块所输入的数据转换为能够输入至显示模组的数据，并保证多接口视频数据输入时的数据同步、输入数据的图像分割方式与所需要数据的图像分割方式的变换以及帧率变换。
本公开实施例另一方面还提供一种图像数据处理方法，如图8所示，包括：
S810，多个写控制器分别获取多帧输入图像被划分的多个图像块的输入数据，其中，每一写控制器获取每一帧输入图像被划分的多个图像块中的一个图像块的输入数据，并确定所述输入数据在存储器中存储的帧地址，根据所确定的帧地址向所述存储器发送所述输入数据；
S820，多个读控制器分别确定第一帧地址，根据所述第一帧地址获取所述存储器中为第二帧地址的数据，并输出所获取的为第二帧地址的数据，其中，所述第一帧地址是与每一读控制器相关联的所述写控制器当前获取的输入数据的帧地址，所述第二帧地址与所述第一帧地址之间相差预设固定数量个帧地址；其中，每一所述读控制器与至少一所述写控制器相关联。
采用本公开实施例所述图像数据处理方法，多个写控制器的数据输入与多个读控制器的数据输出的过程中，读控制器从存储器中读取数据时跟随与之相关联的写控制器写入数据的帧地址，便可使从多个读控制器输出的各图像块属于同一图像帧，即简单地实现输出图像帧同步，并能够实现输入数据的图像分割方式与所需要数据的图像分割方式的变换以及帧率的变换。
以上所述的是本公开的优选实施方式，应当指出对于本技术领域的普通人员来说，在不脱离本公开所述原理前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (16)

  1. 一种图像数据处理装置，其中，包括：
    多个写控制器，被配置为分别获取多帧输入图像被划分的多个图像块的输入数据，其中，每一所述写控制器被配置为获取每一帧输入图像被划分的多个图像块中的一个图像块的输入数据，并确定所述输入数据在存储器中存储的帧地址，根据所确定的帧地址向所述存储器发送所述输入数据；
    多个读控制器，其中，每一所述读控制器与至少一所述写控制器相关联，每一所述读控制器被配置为确定第一帧地址，根据所述第一帧地址获取所述存储器中为第二帧地址的数据，并输出所获取的为第二帧地址的数据，其中，所述第一帧地址是与每一所述读控制器相关联的所述写控制器当前获取的输入数据在所述存储器中的帧地址，所述第二帧地址与所述第一帧地址之间相差预设固定数量个帧地址。
  2. 根据权利要求1所述的图像数据处理装置，其中，每一所述读控制器与至少两个所述写控制器相关联，所述读控制器所获取的数据相对应的图像块，包括第一子图像块和第二子图像块，且不包括第三子图像块和第四子图像块，其中，与所述读控制器相关联的第一写控制器所获取的输入数据相对应的图像块包括所述第一子图像块和第三子图像块，与所述读控制器相关联的第二写控制器所获取的输入数据相对应的图像块包括所述第二子图像块和第四子图像块。
  3. 根据权利要求1所述的图像数据处理装置，其中，所述读控制器被配置为：获取所述存储器中为第二帧地址的数据后，再次从所述存储器获取数据时，若与所述读控制器相关联的所述写控制器当前获取的输入数据在所述存储器中的帧地址仍保持为所述第一帧地址，则重复获取为所述第二帧地址的数据。
  4. 根据权利要求1所述的图像数据处理装置，其中，所述读控制器被配置为：从所述存储器获取为第二帧地址的数据之前，若所述存储器内还包括为第三帧地址的数据未被获取，则放弃获取为所述第三帧地址的数据，其中，与所述读控制器相关联的所述写控制器发送所述第三帧地址对应的输入数据的时间在发送所述第二帧地址对应的输入数据的时间之前。
  5. 根据权利要求1所述的图像数据处理装置，其中，所述图像数据处理装 置还包括：
    检测模块，被配置为检测输入至每一所述写控制器的输入数据是否为异常数据；
    第一图像填补模块，与所述检测模块和所述读控制器连接，所述第一图像填补模块被配置为：获取由每一所述读控制器输出的数据，响应于所述检测模块确定输入至所述写控制器的目标帧相对应图像块的输入数据为异常数据，将所述目标帧相对应图像块的数据以预设填补图像数据输出；或者，所述第一图像填补模块被配置为：
    响应于所述检测模块确定当前输入至所述写控制器的输入数据为异常数据，所述读控制器停止获取所述存储器中的数据，所述第一图像填补模块输出预设填补图像数据。
  6. 根据权利要求5所述的图像数据处理装置，其中，对于所述第一图像填补模块被配置为：获取由每一所述读控制器输出的数据，响应于所述检测模块确定输入至所述写控制器的目标帧相对应图像块的输入数据为异常数据，将所述目标帧相对应图像块的数据以预设填补图像数据输出的情形，
    所述第一图像填补模块还与所述写控制器连接，所述写控制器还被配置为向所述第一图像填补模块输出所述目标帧相对应图像块在所述存储器中的帧地址，所述第一图像填补模块根据所述目标帧相对应图像块在所述存储器中的帧地址，确定所述读控制器输出的所述目标帧相对应图像块的数据。
  7. 根据权利要求1所述的图像数据处理装置，其中，所述写控制器还被配置为在向所述存储器发送所述输入数据时，若确定所述输入数据为异常数据，则根据所确定的帧地址，以预设填补图像数据代替所述输入数据发送至所述存储器，或者向所述存储器发送预设字符。
  8. 根据权利要求7所述的图像数据处理装置，其中，所述图像数据处理装置还包括：
    第二图像填补模块，与所述读控制器连接，被配置为响应于所述读控制器输出的目标帧相对应图像块的输出数据为所述预设字符，将所述目标帧相对应图像块的数据以预设填补图像数据输出。
  9. 根据权利要求1所述的图像数据处理装置，其中，多个所述写控制器中，其中一所述写控制器在向所述存储器的目标帧地址发送所述输入数据后，若间 隔预设时长未接收到所述输入数据，则在重新接收所述输入数据后，从所述存储器的所述目标帧地址的下一个帧地址开始向所述存储器发送所述输入数据。
  10. 根据权利要求1所述的图像数据处理装置，其中，所述读控制器在从所述存储器获取所述第二帧地址的数据的过程中，若与所述读控制器相关联的所述写控制器当前向所述存储器所发送输入数据的帧地址变更为第四帧地址，所述读控制器保持获取所述第二帧地址的数据，直至所述第二帧地址的数据获取完毕，其中，所述第四帧地址和所述第一帧地址不同。
  11. 根据权利要求1至10任一项所述的图像数据处理装置，其中，所述图像数据处理装置还包括：
    仲裁器，与所述存储器、所述写控制器和所述读控制器分别连接，所述仲裁器用于配置每一所述写控制器向所述存储器发送所述输入数据的传输权限，以及配置每一所述读控制器从所述存储器读出数据的传输权限。
  12. 根据权利要求11所述的图像数据处理装置，其中，所述图像数据处理装置还包括所述存储器，所述存储器为双倍速率存储器，且所述双倍速率存储器通过存储器控制器与所述仲裁器连接；
    所述仲裁器还被配置为，当所述写控制器和所述读控制器被配置传输权限时，控制所述写控制器和所述读控制器与所述存储器控制器之间的数据传输通路连通，当所述写控制器和所述读控制器未被配置传输权限时，控制所述写控制器和所述读控制器与所述存储器控制器之间的数据传输通路断开。
  13. 根据权利要求1-10任一项所述的图像数据处理装置，其中，所述图像数据处理装置还包括：
    至少两个图像数据输入接口，每一所述图像数据输入接口与至少一所述写控制器连接；所述图像数据输入接口被配置为接收每一帧输入图像的部分待处理数据，并对所述部分待处理数据进行格式转换，获得发送至与其相连接的所述写控制器的所述输入数据。
  14. 根据权利要求1至10任一项所述的图像数据处理装置，其中，不同的所述写控制器将属于同一帧输入图像的输入数据，发送至所述存储器的同一帧地址中，或者发送至所述存储器的不同帧地址中。
  15. 一种显示装置，其中，包括显示模组和权利要求1至14任一项所述的图像数据处理装置。
  16. 一种图像数据处理方法，其中，包括：
    多个写控制器分别获取多帧输入图像被划分的多个图像块的输入数据，其中，每一写控制器获取每一帧输入图像被划分的多个图像块中的一个图像块的输入数据，并确定所述输入数据在存储器中存储的帧地址，根据所确定的帧地址向所述存储器发送所述输入数据；
    多个读控制器分别确定第一帧地址，根据所述第一帧地址获取所述存储器中为第二帧地址的数据，并输出所获取的为第二帧地址的数据，其中，所述第一帧地址是与每一读控制器相关联的所述写控制器当前获取的输入数据的帧地址，所述第二帧地址与所述第一帧地址之间相差预设固定数量个帧地址；其中，每一所述读控制器与至少一所述写控制器相关联。
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