US5432905A - Advanced asyncronous video architecture - Google Patents

Advanced asyncronous video architecture Download PDF

Info

Publication number
US5432905A
US5432905A US08194544 US19454494A US5432905A US 5432905 A US5432905 A US 5432905A US 08194544 US08194544 US 08194544 US 19454494 A US19454494 A US 19454494A US 5432905 A US5432905 A US 5432905A
Authority
US
Grant status
Grant
Patent type
Prior art keywords
memory
video
system
control signals
pixel data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08194544
Inventor
Minjhing Hsieh
Edward P. Hutchins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Chips and Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/395Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Abstract

An asynchronous video system provides for the appropriate pixel data to be displayed. The system maps display control signals into a memory clock while maintaining the appropriate relationship with pixel data. Therefore, the display control signals are generated using the memory clock. Hence, no synchronization circuit is necessary to ensure that the memory control circuit and display control circuit are running at the same frequency.

Description

This is a continuation of application Ser. No. 07/590,22 filed on Sep. 28, 1990, now abandoned.

The present invention relates to an asynchronous video controller system. More particularly, the present invention relates to a system for providing video and display control signals for a raster display device using asynchronous clocks.

BACKGROUND OF THE INVENTION

The present invention pertains to the environment of a raster display system. Raster display device has been the main visual information presentation device in the information industry. It is defined here as a display device in which picture elements (pixel data) are presented to the screen in a fixed scanning order. The order can be repetition of left to right for a line and top to bottom for one screen or the other combinations as long as it is fixed in a particular system. Same scanning order can also happen in several sections of the screen alternatively or simultaneously. Thus the raster display device referred to in this invention includes CRT monitor and flat panels such as liquid crystal display (LCD), electroluminant display (ELD), and plasma display. Video controller designs for raster display system use either a synchronous or asynchronous clock for the three major functions--video memory control, video pixel processing, and video display control. Using a synchronous clock--that is, the same clock for the three major functions--the memory performance is limited and, in addition, design flexibility is significantly impaired.

Hence, to improve the designs, at least two asynchronous clocks have been used. In these types of systems, the video memory runs at a different frequency than the video processing circuit and display control circuit. In all previously known asynchronous video designs, the display control signals, for example, HSYNC, VSYNC, BLANK, DISPEN (DISPLAY ENABLE) and CURSON (TEXT CURSOR ON), are on the video clock side because they need to be synchronous to video pixel processing. Video pixel information is fetched from the video memory using memory clock. The problem with previously known asynchronous systems has been the need for the synchronization circuit between the memory control circuit and the display control circuit to coordinate the complex events happening in these two circuits running at different frequencies. This type of synchronization circuit is very complex and its functional reliability has been a main design problem in the prior asynchronous video architecture. What is required is a video controller design in which the limitation above described with synchronous systems such as memory performance and design flexibility are eliminated and, at the same time, the synchronization circuit design problems associated with such asynchronous systems are removed.

SUMMARY OF THE INVENTION

The present invention comprises an asynchronous video controller system which includes a memory clock and a video clock. The system comprises of memory which contains pixel data and a video controller circuit for controlling pixel data fetched from the video memory. It also includes means for providing a plurality of raster display control signals. A First In First Out (FIFO) circuit is used for receiving the pixel data and the raster display control signals responsive to the memory clock. A video processing circuit for processing the video signals receives the video display control signals and the pixel data from the FIFO responsive to the video clock.

Through the use of this system, advanced raster display control signals are provided. By mapping the display control signals into memory clock, while maintaining the relationship with pixel data, the raster display control signals are generated on the memory side using the memory clock instead of the video clock. Hence, there is no need for a synchronization circuit as is known in the prior art for asynchronous systems. The complex design problems associated with the synchronization circuit to handshake between the raster display control circuit and the memory control circuit running at different frequencies are thus completely eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a synchronous video control system according to the prior art.

FIG. 2 is a block diagram of an asynchronous video control system according to the prior art.

FIG. 3 is a block diagram of an asynchronous video control system in accordance with the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention relates to an improvement in the generation of video signals in an asynchronous video system. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the refinements shown, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Referring now to FIG. 1, what is shown is a synchronous video system 10 which includes video memory 12, which is coupled to a memory control circuit 14, which in turn is coupled to a video processing circuit 16. Coupled to the Video processing circuit 16, also, is a display control circuit 18 which provides control signals for a raster display device 17 to operate properly. The display 17 can be of any form of raster display device including CRT monitor and a variety of flat panel devices such as liquid crystal display (LCD), electroluminant display (ELD), plasma display.

Some examples taken from the CRT display control signal are: HSYNC, VSYNC, BLANK, DISPEN and CURSON. HSYNC stands for horizontal synchronization. It is used to tell the raster scanning operation when to retrace horizontally to the beginning of the horizontal line. VSYNC stands for vertical synchronization and it tells the raster operation when to retrace vertically to the top (beginning) of the display screen. BLANK tells the display device when to turn off the display. DISPEN stands for display enable and it tells the display device when to turn on the display. CURSON stands for cursor on and it tells the video processing circuit when to generate cursor video for text character.

Together with the raster display control signals, pixel data generated from the video processing circuit 16 is sent to display device 17 to tell what pixel value to display. The video processing circuit 16 processes the pixel data fetched from the video memory 12. As is seen, a single clock signal from clock 20 is provided to the memory control circuit 14, the video process circuit 16 and the display control circuit 18 to ensure that three major functions are operating simultaneously. The relationship between the three control circuits is easily maintained by using the same clock source. As has been before described, this type of circuit, although simple in design, provides for very limited system performance because design flexibility is restricted by the single clock.

FIG. 2 describes a typical asynchronous video system 100 as known in the prior art. This system 100 contains many of the same elements as those above described--for example, video memory 112, memory control circuit 114, video process circuit 116, display control circuit 118 and a display device 117. It also includes three additional elements: a video clock 126, a FIFO 122, and a synchronization circuit 124.

There are two clocks for such a system--the memory clock 120 which is used to fetch video data from the video memory 112 via memory control circuit 114 and FIFO 122, and a video clock 126 which provides the clocking signal to display control circuit 118 and video processing circuit 116. FIFO 122 is used between memory control circuit 114 and video processing circuit 116 to temporarily buffer the pixel data. Synchronization circuit 124 is used between the memory control circuit 114 and the display control circuit 118.

A major design issue for such an asynchronous approach is the need for the synchronization circuit 124. To gain the memory performance, the memory control circuit 114 is running at different frequency than the display control circuit 118 and the video processing circuit 116. However, the relationship between the display control circuit 118 and the memory control circuit 114 needs to be maintained in order to fetch and generate the pixel data at the right time frame relative to the raster scanning position so that correct image can be generated on the display device at the right time. It is the responsibility of the synchronization circuit 124 to coordinate and maintain the right relationship between these two control circuits which run at different frequencies. The correct relationship needs to be maintained under all possible operational conditions. Reliable design of such complex synchronization circuit 124 is a major issue.

The present invention provides a completely different architecture for this asynchronous system that eliminates the need for the synchronization circuit and, therefore, entirely eliminates the design problems associated with it.

Referring to FIG. 3, as is seen, in the asynchronous video system 200 of the present invention, a video memory 204 is controlled by the memory control circuit 206, which feeds pixel data to a FIFO 208. The display control circuit 202 is now on the memory side of the FIFO 208 rather than on the video side. Hence, in this embodiment, the same clock signal 220 from memory clock 204 is used to control the information in both the display control circuit 202 and the memory control circuit 206. In the use of this system, as above described, the memory clock 220 is utilized to generate memory control signals such as RAS, CAS, WE and memory address and data bus. These signals are used to control the memory operations such as READ cycle, WRITE cycle, and REFRESH cycle, etc and get the pixel data from the memory. The video memory can be of any type, such as static RAM, dynamic RAM, or video RAM.

The memory clock signal 220 is also used to provide what is termed advanced display control signals. These advanced version of raster display control signals are generated before they are actually processed on the video side of the system. In this embodiment, the display control signals are mapped into the memory clock time frame and their relationship with the pixel data is locked by the memory cycles using the same clock signals. The pixel data and advanced display control signals together are then provided to the FIFO 208 which, in turn, feeds both of the above mentioned signals to the video process circuit 210. The video process circuit 210 then is clocked by the video clock 212 via line 222 to ensure that both the pixel data and the display control signals are sent to the display device 217 at the proper time.

Hence, through the present architecture, the design of the boundary between the memory section and the video section is simplified. Since the memory section and the video section can run independently by different clocks, the system design is very flexible and the system performance can be optimized by selecting the proper clock frequency for each section. Also, since no synchronization circuit is required, this system eliminates all the design issues associated with such a circuit.

One of ordinary skill in the art will recognize that all of the elements shown can be implemented in a variety of ways and those implementations would be within the spirit and scope of the present invention. It should also be recognized that the five advanced display control signals mentioned are not all inclusive. Hence, there could be a variety of other display control signals provided and their use would be within the spirit and scope of the present invention. The raster display controls signals can be for display devices such as CRT monitor, liquid crystal display, electroluminant display, and plasma display. Also the video memory can be static RAM, dynamic RAM, or video RAM.

It is understood that the above described embodiment is merely illustrative of but a small number of the many possible specific embodiments which can represent applications of the principles of the present invention. Numerous and various other arrangements can be readily devised in accordance with these principles by one of ordinary skill in the art without departing from the scope of the present invention. The scope of the present invention is limited only by the following claims.

Claims (22)

We claim:
1. An asynchronous video system, the system including a memory clock and a video clock, the system comprising:
a video memory containing pixel data;
means, coupled to the memory clock, for fetching pixel data within the video memory;
means coupled to the memory clock for providing a plurality of raster display control signals;
FIFO means for receiving the pixel data from the video memory and the raster display control signals from the providing means responsive to a signal from the memory clock such that the raster display control signals and pixel data are in a predetermined relationship defined by the memory clock; and
means for processing the display control signals and pixel data from the FIFO means responsive to a signal from the video clock.
2. The system of claim 1 in which the providing means is a raster display control circuit.
3. The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes a CRT monitor.
4. The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes a flat panel display device.
5. The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes a liquid crystal display device (LCD).
6. The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes an electroluminant display device (ELD).
7. The system of claim 2 in which the providing means provides control signals for a raster display device in which the raster display device includes a plasma display device.
8. The system of claim 2 in which the raster display control circuit provides advanced control signals.
9. The system of claim 8 in which the advanced control signals comprise horizontal synchronization (HSYNC), vertical synchronization (VSYNC), BLANK, display enable (DISPEN), cursor on (CURSON) signals.
10. The system of claim 2 in which the synchronization between the memory control and the display control is achieved by locking the two circuits with the memory clock.
11. The system of claim 1 in which the providing means is a CRT control circuit.
12. The system of claim 1 in which the processing means comprises a video process circuit.
13. The system of claim 12 in which the video process circuit provides at an output responsive to a video clock signal pixel data and raster display control signals.
14. The system of claim 12 in which the video process circuit provides at output responsive to a video clock signal pixel data, HSYNC control signal, VSYNC control signal, BLANK control signal, DISPEN control signal and CURSON control signal.
15. The system of claim 1 in which the pixel data fetching means is a video memory control circuit.
16. The system of claim 15 in which the providing means lacks a synchronization circuit between the video memory control circuit and the display control circuit.
17. The system of claim 15 in which the synchronization between the memory control and the display control is achieved by locking the two circuits with the memory clock.
18. The system of claim 1 in which the providing means is a flat panel control circuit.
19. The system of claim 18 in which the providing means is for split panel control giving one line of data to each section one at a time.
20. An asynchronous video system, the system including a memory clock and a video clock, the system comprising:
a video memory containing pixel data;
memory control circuit coupled to the memory clock for fetching pixel data within the video memory;
raster display control circuit coupled to the memory clock for providing advanced video control signals, the advanced control signals including HYSNC, VSYNC, BLANK, DISPEN, CURSON control signals and other raster display control signals for a flat panel display device;
a FIFO circuit for receiving the pixel data from the memory control circuit and for receiving the advanced display control signals from the raster display control circuit and responsive to a signal from the memory clock providing the pixel data and advanced control signals at an output of the FIFO circuit in a predetermined relationship defined by the memory clock; and
a video process circuit for processing the advanced display control signals and the pixel data from the FIFO circuit responsive to a signal from the video clock.
21. An asynchronous video system for placing pixel data on a display comprising:
a memory clock defining a series of memory cycles;
a video memory containing pixel data;
a memory control circuit, responsive to said memory clock, for causing pixel data to be output from said video memory synchronously with said memory clock;
a display control circuit, responsive to said memory clock, for generating a plurality of raster display control signals synchronous with said memory clock;
a first-in-first-out (FIFO) circuit, responsive to said memory clock, for receiving said pixel data from said video memory and said plurality of raster display control signals from said display control circuit synchronously with said memory clock;
a video clock defining a series of video cycles; and
a video processing circuit, coupled to said FIFO and responsive to said video clock, for receiving said pixel data and said plurality of raster display control signals from said FIFO and outputting said pixel data and said plurality of raster display control signals to said display synchronously with said video clock.
22. A method for placing pixel data stored in a video memory on a display comprising:
generating a series of memory cycles;
causing pixel data to be output from said memory synchronously with said memory cycles;
generating a plurality of raster display control signals synchronously with said memory cycles;
receiving said pixel data from said video memory and said plurality of raster display control signals from said display control circuit synchronously with said memory cycles;
generating a series of video cycles;
storing said pixel data and said plurality of raster display control signals; and
outputting said pixel data and said plurality of raster display control signals to said display synchronously with said video cycles.
US08194544 1990-09-28 1994-02-10 Advanced asyncronous video architecture Expired - Lifetime US5432905A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US59022290 true 1990-09-28 1990-09-28
US08194544 US5432905A (en) 1990-09-28 1994-02-10 Advanced asyncronous video architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08194544 US5432905A (en) 1990-09-28 1994-02-10 Advanced asyncronous video architecture

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US59022290 Continuation 1990-09-28 1990-09-28

Publications (1)

Publication Number Publication Date
US5432905A true US5432905A (en) 1995-07-11

Family

ID=24361352

Family Applications (1)

Application Number Title Priority Date Filing Date
US08194544 Expired - Lifetime US5432905A (en) 1990-09-28 1994-02-10 Advanced asyncronous video architecture

Country Status (2)

Country Link
US (1) US5432905A (en)
JP (1) JP3218567B2 (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5537128A (en) * 1993-08-04 1996-07-16 Cirrus Logic, Inc. Shared memory for split-panel LCD display systems
US5615376A (en) * 1994-08-03 1997-03-25 Neomagic Corp. Clock management for power reduction in a video display sub-system
WO1998000830A1 (en) * 1996-06-27 1998-01-08 Siemens Aktiengesellschaft Display system and process for supplying a display system with a picture signal
US5754170A (en) * 1996-01-16 1998-05-19 Neomagic Corp. Transparent blocking of CRT refresh fetches during video overlay using dummy fetches
US5821948A (en) * 1993-11-05 1998-10-13 Fujitsu Limited Image processing circuit and display unit having the image processing circuit
US5940610A (en) * 1995-10-05 1999-08-17 Brooktree Corporation Using prioritized interrupt callback routines to process different types of multimedia information
DE19807257A1 (en) * 1998-02-20 1999-09-09 Siemens Ag Display device and method for representing analog video signals
US6154202A (en) * 1994-11-17 2000-11-28 Hitachi, Ltd. Image output apparatus and image decoder
US20020033900A1 (en) * 2000-06-14 2002-03-21 Yoshihiro Honma Image signal processing apparatus
US20060066623A1 (en) * 2004-09-29 2006-03-30 Bowen Andrew D Method and system for non stalling pipeline instruction fetching from memory
US20060103659A1 (en) * 2004-11-15 2006-05-18 Ashish Karandikar Latency tolerant system for executing video processing operations
US20070203866A1 (en) * 2006-02-27 2007-08-30 Kidd Scott D Method and apparatus for obtaining and using impact severity triage data
USRE39898E1 (en) 1995-01-23 2007-10-30 Nvidia International, Inc. Apparatus, systems and methods for controlling graphics and video data in multimedia data processing and display systems
US20090037689A1 (en) * 2007-07-30 2009-02-05 Nvidia Corporation Optimal Use of Buffer Space by a Storage Controller Which Writes Retrieved Data Directly to a Memory
US20090153573A1 (en) * 2007-12-17 2009-06-18 Crow Franklin C Interrupt handling techniques in the rasterizer of a GPU
US20090153571A1 (en) * 2007-12-17 2009-06-18 Crow Franklin C Interrupt handling techniques in the rasterizer of a GPU
US20090273606A1 (en) * 2008-05-01 2009-11-05 Nvidia Corporation Rewind-enabled hardware encoder
US20090274209A1 (en) * 2008-05-01 2009-11-05 Nvidia Corporation Multistandard hardware video encoder
US20100153661A1 (en) * 2008-12-11 2010-06-17 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
CN103295551A (en) * 2013-06-09 2013-09-11 南车株洲电力机车研究所有限公司 Liquid crystal display (LCD) display control system and control method thereof
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333484B1 (en) * 2000-03-17 2001-12-25 Chromalloy Gas Turbine Corporation Welding superalloy articles
CN100445020C (en) 2003-06-10 2008-12-24 住友金属工业株式会社 Welded joint made of an austenitic steel
JP5126703B1 (en) 2011-07-06 2013-01-23 新日鐵住金株式会社 Austenitic steel welded joints
US9527162B2 (en) 2011-11-07 2016-12-27 Siemens Energy, Inc. Laser additive repairing of nickel base superalloy components
KR20180026804A (en) * 2012-05-11 2018-03-13 지멘스 에너지, 인코포레이티드 Laser additive repairing of nickel base superalloy components
CN102728950B (en) * 2012-06-16 2014-08-13 张家港富瑞特种装备股份有限公司 Laser welding method for metal sheets applied to ultra low temperature environment

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4569019A (en) * 1983-06-03 1986-02-04 Commodore Business Machines Inc. Video sound and system control circuit
US4905189A (en) * 1985-12-18 1990-02-27 Brooktree Corporation System for reading and writing information
US4991111A (en) * 1986-08-28 1991-02-05 Hughes Aircraft Company Real-time image processing system
US5148523A (en) * 1988-11-29 1992-09-15 Solbourne Computer, Inc. Dynamic video RAM incorporationg on chip line modification

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4569019A (en) * 1983-06-03 1986-02-04 Commodore Business Machines Inc. Video sound and system control circuit
US4905189A (en) * 1985-12-18 1990-02-27 Brooktree Corporation System for reading and writing information
US4905189B1 (en) * 1985-12-18 1993-06-01 System for reading and writing information
US4991111A (en) * 1986-08-28 1991-02-05 Hughes Aircraft Company Real-time image processing system
US5148523A (en) * 1988-11-29 1992-09-15 Solbourne Computer, Inc. Dynamic video RAM incorporationg on chip line modification

Cited By (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5537128A (en) * 1993-08-04 1996-07-16 Cirrus Logic, Inc. Shared memory for split-panel LCD display systems
US5821948A (en) * 1993-11-05 1998-10-13 Fujitsu Limited Image processing circuit and display unit having the image processing circuit
US5615376A (en) * 1994-08-03 1997-03-25 Neomagic Corp. Clock management for power reduction in a video display sub-system
US6154202A (en) * 1994-11-17 2000-11-28 Hitachi, Ltd. Image output apparatus and image decoder
USRE39898E1 (en) 1995-01-23 2007-10-30 Nvidia International, Inc. Apparatus, systems and methods for controlling graphics and video data in multimedia data processing and display systems
US5940610A (en) * 1995-10-05 1999-08-17 Brooktree Corporation Using prioritized interrupt callback routines to process different types of multimedia information
US5754170A (en) * 1996-01-16 1998-05-19 Neomagic Corp. Transparent blocking of CRT refresh fetches during video overlay using dummy fetches
WO1998000830A1 (en) * 1996-06-27 1998-01-08 Siemens Aktiengesellschaft Display system and process for supplying a display system with a picture signal
US6380989B1 (en) * 1996-06-27 2002-04-30 Siemens Aktiengesellschaft Display system and method for supplying a display system with a picture signal
DE19807257C2 (en) * 1998-02-20 2000-05-11 Siemens Ag Display device and method for representing analog video signals
DE19807257A1 (en) * 1998-02-20 1999-09-09 Siemens Ag Display device and method for representing analog video signals
US7136110B2 (en) * 2000-06-14 2006-11-14 Canon Kabushiki Kaisha Image signal processing apparatus
US20020033900A1 (en) * 2000-06-14 2002-03-21 Yoshihiro Honma Image signal processing apparatus
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
US20060066623A1 (en) * 2004-09-29 2006-03-30 Bowen Andrew D Method and system for non stalling pipeline instruction fetching from memory
US8624906B2 (en) 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
US8683184B1 (en) 2004-11-15 2014-03-25 Nvidia Corporation Multi context execution on a video processor
US20060176309A1 (en) * 2004-11-15 2006-08-10 Shirish Gadre Video processor having scalar and vector components
US20060176308A1 (en) * 2004-11-15 2006-08-10 Ashish Karandikar Multidimensional datapath processing in a video processor
US8493396B2 (en) 2004-11-15 2013-07-23 Nvidia Corporation Multidimensional datapath processing in a video processor
US9111368B1 (en) * 2004-11-15 2015-08-18 Nvidia Corporation Pipelined L2 cache for memory transfers for a video processor
US8698817B2 (en) 2004-11-15 2014-04-15 Nvidia Corporation Video processor having scalar and vector components
US8687008B2 (en) 2004-11-15 2014-04-01 Nvidia Corporation Latency tolerant system for executing video processing operations
US8738891B1 (en) 2004-11-15 2014-05-27 Nvidia Corporation Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions
US8736623B1 (en) 2004-11-15 2014-05-27 Nvidia Corporation Programmable DMA engine for implementing memory transfers and video processing for a video processor
US20060152520A1 (en) * 2004-11-15 2006-07-13 Shirish Gadre Stream processing in a video processor
US8416251B2 (en) 2004-11-15 2013-04-09 Nvidia Corporation Stream processing in a video processor
US8424012B1 (en) 2004-11-15 2013-04-16 Nvidia Corporation Context switching on a video processor having a scalar execution unit and a vector execution unit
US20060103659A1 (en) * 2004-11-15 2006-05-18 Ashish Karandikar Latency tolerant system for executing video processing operations
US8725990B1 (en) 2004-11-15 2014-05-13 Nvidia Corporation Configurable SIMD engine with high, low and mixed precision modes
US8493397B1 (en) 2004-11-15 2013-07-23 Nvidia Corporation State machine control for a pipelined L2 cache to implement memory transfers for a video processor
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
US20070203866A1 (en) * 2006-02-27 2007-08-30 Kidd Scott D Method and apparatus for obtaining and using impact severity triage data
US8683126B2 (en) 2007-07-30 2014-03-25 Nvidia Corporation Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory
US20090037689A1 (en) * 2007-07-30 2009-02-05 Nvidia Corporation Optimal Use of Buffer Space by a Storage Controller Which Writes Retrieved Data Directly to a Memory
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US20090153573A1 (en) * 2007-12-17 2009-06-18 Crow Franklin C Interrupt handling techniques in the rasterizer of a GPU
US20090153571A1 (en) * 2007-12-17 2009-06-18 Crow Franklin C Interrupt handling techniques in the rasterizer of a GPU
US9064333B2 (en) 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8780123B2 (en) 2007-12-17 2014-07-15 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US20090273606A1 (en) * 2008-05-01 2009-11-05 Nvidia Corporation Rewind-enabled hardware encoder
US8923385B2 (en) 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US8681861B2 (en) 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US20090274209A1 (en) * 2008-05-01 2009-11-05 Nvidia Corporation Multistandard hardware video encoder
US20100153661A1 (en) * 2008-12-11 2010-06-17 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
US8489851B2 (en) 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
CN103295551B (en) * 2013-06-09 2016-02-24 南车株洲电力机车研究所有限公司 One kind lcd display control system and control method
CN103295551A (en) * 2013-06-09 2013-09-11 南车株洲电力机车研究所有限公司 Liquid crystal display (LCD) display control system and control method thereof

Also Published As

Publication number Publication date Type
JPH05192785A (en) 1993-08-03 application
JP3218567B2 (en) 2001-10-15 grant

Similar Documents

Publication Publication Date Title
US5608418A (en) Flat panel display interface for a high resolution computer graphics system
US6195079B1 (en) On-screen user interface for a video adapter circuit
US6177922B1 (en) Multi-scan video timing generator for format conversion
US7068278B1 (en) Synchronized graphics processing units
US6535208B1 (en) Method and apparatus for locking a plurality of display synchronization signals
US5579025A (en) Display control device for controlling first and second displays of different types
US5896131A (en) Video raster display with foreground windows that are partially transparent or translucent
US7120816B2 (en) Method for testing synchronization and connection status of a graphics processing unit module
US5742788A (en) Method and apparatus for providing a configurable display memory for single buffered and double buffered application programs to be run singly or simultaneously
US4951232A (en) Method for updating pipelined, single port Z-buffer by segments on a scan line
US5404437A (en) Mixing of computer graphics and animation sequences
US4653020A (en) Display of multiple data windows in a multi-tasking system
US5345552A (en) Control for computer windowing display
US20100302214A1 (en) Method of synchronizing a driving device and display apparatus for performing the method
US5488385A (en) Multiple concurrent display system
US6262695B1 (en) Method and apparatus for phase-locking a plurality of display devices and multi-level driver for use therewith
US4569019A (en) Video sound and system control circuit
US4899139A (en) Display control device for superimposing data with a broad case signal on a television screen
US4769762A (en) Control device for writing for multi-window display
US20060208960A1 (en) Display specific image processing in an integrated circuit
US6317114B1 (en) Method and apparatus for image stabilization in display device
US6054980A (en) Display unit displaying images at a refresh rate less than the rate at which the images are encoded in a received display signal
US4700320A (en) Bitmapped graphics workstation
US5657478A (en) Method and apparatus for batchable frame switch and synchronization operations
US5434592A (en) Multimedia expansion unit

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: CHIPS AND TECHNOLOGIES, LLC, CALIFORNIA

Free format text: MERGER;ASSIGNOR:CHIPS AND TECHNOLOGIES, INC.;REEL/FRAME:011333/0503

Effective date: 19981030

AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHIPS AND TECHNOLOGIES, LLC;REEL/FRAME:011449/0081

Effective date: 20010103

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: CHIPS AND TECHNOLOGIES, LLC, CALIFORNIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBER FROM 09/207,014 TO 09/027,014 PREVIOUSLY RECORDED AT REEL: 011333 FRAME: 0503. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:CHIPS AND TECHNOLOGIES, INC.;REEL/FRAME:038824/0619

Effective date: 19981030