TW201250947A - Package structure having a micromechanical electronic component and method of making same - Google Patents
Package structure having a micromechanical electronic component and method of making same Download PDFInfo
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- TW201250947A TW201250947A TW100116620A TW100116620A TW201250947A TW 201250947 A TW201250947 A TW 201250947A TW 100116620 A TW100116620 A TW 100116620A TW 100116620 A TW100116620 A TW 100116620A TW 201250947 A TW201250947 A TW 201250947A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/094—Feed-through, via
- B81B2207/096—Feed-through, via through the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
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Description
201250947 六、發明說明: 【發明所屬之技術領域】 本發明係有關一種半導體封裝件,尤指一種具微機電 元件之半導體封裝件。 【先前技術】 微機電糸統(Micro Electro Mechanical System,MEMS) 是一種兼具電子與機械功能的微小裝置,在製造上則藉由 各種微細加工技術來達成,可將微機電元件設置於晶片的 表面上,且以保護罩或底膠進行封裝保護,而得到一微機 電封裝結構。請參閱第1A至1D圖,係習知具微機電元件 之封裝結構之各式態樣之剖視示意圖。 如第1A圖所示,係揭露於第6,809,412號美國專利 者,其係先於基板10上設置晶片14,且該晶片14上具有 微機電元件141,再將該晶片14以導線11電性連接該基 板10,最後於該基板10上設置玻璃蓋體12,以封蓋該晶 片14、微機電元件141及導線11。 如第1B圖所示,係揭露於第6,303,986號美國專利 者,其係先於具有微機電元件141之晶片14上設置玻璃蓋 體12,以封蓋該微機電元件141’再將該晶片14設於承載 用之導線架1〇’上,接著以導線11電性連接該導線架10’ 與晶片14 ’最後以封裝材15包覆導線架1〇’、導線11、 蓋體12與晶片14。
惟,上述習知之封裝結構均具有承載件(如第1A圖 之基板10與第1B圖之導線架10,)’導致增加整體結構S 4 112039 201250947 之厚度,而無法滿足微小化之需求。因此,遂發展出一種 無承載件之封裝結構。 如第ic圖所示之無承載件之封裝結構,在第 7,368,808號美國專利中,係先於具有電性連接墊14〇及微 機電元件14i之晶片14上設置具有導電通孔12〇之玻璃蓋 體12,以封蓋該微機電元件141,且該導電通孔12〇兩側 具有接觸墊122,内側之接觸墊122訝應連接該電性連接 墊140,而外側之接觸墊122上則形成有銲球16,俾該晶 片14藉由該鲜球16連接至其他電子元件。 如第1D圖所示之第6,846,725號美國專利之封裝結 構’係先於具有電性連接墊140及微機電元件141之晶片 14上設置具有導電通孔120之玻璃蓋體12’以封蓋該微機 電元件141,且該電性連接墊14〇上具有銲錫凸塊142,而 該導電通孔120兩側具有接觸塾122,令内側之接觸塾i 22 對應連接該銲錫凸塊142’使該晶片14藉由外側之該接觸 墊122連接至其他電子元件。 惟,上述習知之封裝結構雖無承載件而可滿足微小化 之需求,但於設置該蓋體12前,需先於該蓋體12中製作 導電通孔120,不僅玻璃鑽孔之成本高,且該導電通孔12〇 兩側之接觸墊122容易發生對位不精準或結合不穩固,導 致電性連接不良,進而影響該晶片14外接電子元件的品 質。 因此,如何避免上述習知技術之種種問題,實為當前 所要解決的目標。 112039 5 201250947 【發明内容】 為克服習知技術之問題,本發明提供一種具微機電元 件之封裝件,係包括:保護層,係具有相對之第一表面及 第二表面、以及複數連通該第一及第二表面之開口;形成 於該保護層之開口中的導體;形成於該保護層之第一表面 與該導體上且電性連接該導體的電性接觸墊;設於該電性 接觸墊上,且電性連接該電性接觸墊的微機電晶片;以及 形成於該保護層上方封裝膠體,以包覆該微機電晶片,令 該導體外露於該保護層之第二表面與該封裝膠體。 本發明復提供一種具微機電元件之封裝件之製法,係 包括:提供一承載板;形成具有相對之第一表面及第二表 面的保護層於該承載板上,其中,該保護層之第二表面結 合至該承載板上,且該保護層上形成有連通該第一及第二 表面以外露出該承載板之部分表面的複數開口;形成導體 於該保護層之開口中;形成電性接觸墊於該保護層之第一 表面與導體上,且該電性接觸墊電性連接該導體;設置微 機電晶片於該電性接觸墊上,且該微機電晶片電性連接該 電性接觸墊;形成封裝膠體於該保護層之第一表面上方, 令該封裝膠體包覆該微機電晶片;以及移除該承載板,令 該導體外露於該保護層之第二表面。 前述之封裝件及其製法中,可植接銲球於該導體之外 露表面上。 前述之封裝件及其製法中,可形成拒銲層於該保護層 之第一表面上,且外露該電性接觸塾。 s 112039 201250947 此外,前述之封裝件及其製法中,可形成導電凸塊於 該電性接觸墊或該微機電晶片上,令該導電凸塊連接該微 機電晶片與該電性接觸墊。 由上可知,本發明之具微機電元件之封裝件及其製 法,係藉由移除該承載板,使該封裝件中未具有如習知技 術中之基板或導線架等過厚之承載件,故可降低該封裝件 之整體厚度,而達到微小化之目的。再者,藉由該封裝膠 體取代習知蓋體,且藉由在該保護層中形成導體,可免除 於蓋體上進行鑽孔之製程,不僅製程簡單而易於實施,且 因製程步驟減少而降低製作成本。 又,本發明之製法係為晶圓級封裝(wafer-level packaging),故無需使用例如習知基板或導線架,而可減 少許多不必要的步驟,因而大幅縮短生產時程,以降低成 本0 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式,熟悉此技藝之人士可由本說明書所揭示之内容輕易地 暸解本發明之其他優點及功效。 須知,本說明書所附圖式所繪示之結構、比例、大小 等,均僅用以配合說明書所揭示之内容,以供熟悉此技藝 之人士之瞭解與閱讀,並非用以限定本發明可實施之限定 條件,故不具技術上之實質意義,任何結構之修飾、比例 關係之改變或大小之調整,在不影響本發明所能產生之功 效及所能達成之目的下,均應仍落在本發明所揭示之技術 7 112039 201250947 内容得能涵蓋之範圍内。同時,本說明書中所引用之如“上 表面“下表面上端面”、《下端面,,及‘‘一,,等之用語, 亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範 圍,其相對關係之改變或調整,在無實質變更技術内容下, 當亦視為本發明可實施之範嘴。 凊參閱第2Α至21圖,其係為本發明具微機電元件之 封裝件之製法之剖面示意圖。 如第2Α圖所示,提供一承載板2〇,接著形成一保護 層21於該承載板2〇上,該保護層21具有上表面(第一表 面)21a及下表面(第二表面)21b,且該保護層21之下 表面21b結合至該承載板2〇上。於本實施例中,該承載板 2〇係為金屬板,而形成該保護層21之材質係為非導電材 質,如:介電材、半導體材、防銲材及絕緣材。 接著,再利用圖案化製程,經阻層、曝光及顯影等步 驟’以於该保護層21上蝕刻形成複數開口 21〇以外露出該 承载板20之部分表面,而該開口 21〇係連通該上表面21& 及下表面21b。 如第2B圖所示,藉由電鍍或無電解電鍍之方式,形 成導體22於該保護層21之開口 21〇中,且該導體22具有 上端面22a與下端面22b ;於本實施例中,形成該導體22 之材質係為銅材。 如第2C圖所示,利用圖案化製程,且以電鍍或無電 解電鍍之方式,形成複數電性接觸墊23於該保護層21之 表面21a與導體22之上端面22a上,且該電性接觸墊s 112039 8 201250947 23電性連接該導體22。 如第2D圖所示,形成一拒銲層(solder mask)24於該 保護層21之第一表面21a與電性接觸墊23上,且於該拒 銲層24上形成複數開口 240,該些開口 240之形式為 SMD(solder mask defined),令該電性接觸墊23之部分上 表面外露於該拒銲·層24開口 240。 於另一實施態樣中,如第2D’圖所示,該些開口 240’ 之形式可為NSMD(non-solder mask defined),令該電性接 觸墊23之全部上表面與侧表面及其周圍之保護層21上表 面21a均外露於該拒銲層24開口 240’。 如第2E圖所示,形成導電凸塊25於該拒銲層24開 口 240中之電性接觸墊23上;於本實施例中,形成該導電 凸塊25之材質係為金材或銲錫材料。 如第2F圖所示,設置至少一微機電晶片26於該導電 凸塊25上,且該微機電晶片26藉由該導電凸塊25電性連 接該電性接觸墊23。所述之微機電晶片26可為陀螺儀 (gyroscope)、加速度計(Accelerometer)或射頻(RF)件。 如第2F’圖所示’於另一實施態樣中,可將該導電凸 塊25’先形成於該微機電晶片26上,令該微機電晶片26 藉由該導電凸塊25’接置該電性接觸墊23。 如第2F”圖所示’於上述兩實施例態樣中,亦可不形 成拒銲層(即省略第2D圖之製程),而直接將該微機電 晶片26藉由該導電凸塊25,25,接置於該電性接觸墊23上。 如第2G圖所示’形成封裝膠體27於該拒銲層24上, 112039 201250947 令該封裝膠體27包覆該微機電晶片26。 如第2H圖所示,移除該承載板20,令該導體22之下 端面22b外露於該保護層21之下表面21b。接著,視需求 沿切割線L (如第2G圖所示)進行切單製程,以取得單 一個封裝件2。 如第2H’圖所示,若經由第2F”圖之製程,將製作出 不具有拒銲層24之封裝件2’。 因此,本發明提供一種具微機電元件之封裝件2’,係 包括:具有上表面21a及下表面21b之保護層21,且該保 護層21復具有複數連通該上、下表面21a,21b之開口 210; 形成於該開口 210中之導體22 ;形成於該保護層21之上 表面21a與該導體22上且電性連接該導體22之電性接觸 墊23 ;設於該電性接觸墊23上且電性連接該電性接觸墊 23之微機電晶片26 ;以及形成於該保護層21上方以包覆 該微機電晶片26之封裝膠體27,令該導體22外露於該保 護層21之下表面21b與該封裝膠體27。 於另一實施態樣中,該封裝件2復包括拒銲層24,係 形成於該保護層21之上表面21a,且該拒銲層24具有複 數開口 240’,令該電性接觸墊23全部外露於該拒銲層24 開口 240,以接置該微機電晶片26;或者拒銲層24係形成 於該保護層21之上表面21a與電性接觸墊23上,並外露 部分電性接觸墊23。其中,該封裝膠體27係形成於該拒 銲層24上。
又,上述兩種型態之封裝件2,2’中,復包括導電凸塊S 10 112039 201250947 25,係設於該電性接觸墊23與該微機電晶片%之間,以 接置該電性接觸墊23與該微機電晶片26。 另外,如第21圖所示,可依需求植接銲球28於該導 體22之下端面22b上。 •综上所述,本發明之具微機電元件之封裝件2,2,及其 製法係藉由移除該承載板20,以降低該封裝件2,2,之整 體厚度,而達到微小化之目的。 再者,藉由該封裝膠體27包覆該微機電晶片 ™ ,· 一…% aa q 厶 υ ,且 於該保護層21中形成導體22,以免除如f知技術中之於 覆蓋件上進行鑽孔之製程,故有效降低製作成本。 上述實施例係用以例示性說明本發明之原理及其功 效,而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之㈣及料下,對上述實_進行修 改。因此本發明之權利保護範圍,應如後述之申請專利範 圍所列。 【圖式簡單說明】 第1A至1D圖係f知具微機電元件之封 態樣之剖視示意圖;以及 谷式 第2 A至21圖係為本發明具微機電元件之封裝件之製 法之剖面示意圖;其中,第2D,圖係為第2d圖:另一雜 樣,第2F,圖係為第則之另一實施方式,第2ρ,,圖係: 第2F及2F,圖之另一態樣,帛2H,圖係為第2 一 態樣。 力一 【主要元件符號說明】 112039 11 201250947 10 基板 HT 導線架 11 導線 12 蓋體 120 導電通孔 122 接觸墊 14 晶片 140 電性連接墊 141 微機電元件 142 鲜·錫凸塊 15 封裝材 16,28 鲜球 2,2, 封裝件 20 承載板 21 保護層 21a 上表面(第一表面) 21b 下表面(第二表面) 210,240,240,開口 22 導體 22a 上端面 22b 下端面 23 電性接觸墊 24 拒銲層 25,25, 導電凸塊 26 微機電晶片 27 封裝膠體 L 切割線 12 112039
Claims (1)
- 201250947 " 七、申請專利範圍: 1· 一種具微機電元件之封裝件,係包括: •保護層,係具有相對之第—表面及第二表面、以及 複數連通§亥第一及第二表面之開口; 導體,係形成於該保護層之開口中; 電性接觸塾’㈣成於該賴層之第—表面與該導 體上’且電性連接該導體; 微機電晶片,係設於該電性接觸墊上,且電性 該電性接觸墊;以及 封裝膠體,係形成於該保護層上方,以包覆該微機 =片,令該導體外露於該保護層之第二表面與該封裝 修體。 2.如申„月專利乾圍第j項所述之具微機電元件之封裝 件,其中,該保護層係為非導電材質。 ^ 3·如申明專利範圍第i項所述之具微機電元件之 件,其中,該導體係為銅材。 & •如申明專利範圍第1項所述之具微機電元件之 件,復包括銲球,係植接於該導體之外露表面上、& 5. 如申請專㈣圍第i項所述之具微機電元件 件,復包括拒銲層,係形成於該保護層之第一表面、 ,該拒鋒層具有複數開口,令該電性接觸塾外露於= 鋅層開口,以供接置該微機電晶片。 〜拒 6. ^申睛專利範圍第5項所述之具微機電元件之 其中,該封裝膠體係形成於該拒鋒層上。 ^ Π2039 1 201250947 7.如申請專利範圍第〗 此e $ 員所述之具微機電元件之封裝 曰^ &塊’係設於該電性接觸墊與該微機電 」之間’以連接該電性接觸墊與該微機電晶片。 8·如申請專利範圍第 # , 員所述之具微機電元件之封裝 、^電凸塊係為金材或銲錫材料。 9. -種具微機電元件之封裝件之製法,係包括: 提供一承载板; 了之第—表面及第二表面的保護層於 杯_板上,其_,該保護層之第二表面結合至該承裁 層场财連通财—及第二表面以外 露出该承载板之部分表㈣複數開口; 形成導體於該保護層之開口中; 形成電性接㈣於該保護層之第—表面 上,且該電性接觸墊電性連接該導體; /、导體 设置微機電晶片於該電性接觸墊 片電性連接該電性接觸塾; 且輕機電晶 形成封裝膠體於該保護層之第一表面上八 裝膠體包覆該微機電晶片;以及 ”亥封 面移除該承載板,令該導體外露於該保護層之第二表 10·如申請專利範圍第9項所述之具微機電 之製法,其中,該承載板係為金屬板。 、件 11.如申請專利範圍第9項所述之具微機電元件 之製法,其中,該保護層係為非導電材質。、'"件 s 112039 201250947 t • 12.如申請專利範圍第9項所述之具微機電元件之封裝件 • 之製法,其中,該導體係為銅材。 13. 如申請專利範圍第9項所述之具微機電元件之封裝件 之製法,復包括植接銲球於該導體之外露表面上。 14. 如申請專利範圍第9項所述之具微機電元件之封裝件 之製法,復包括於設置該微機電晶片之前,先形成拒銲 層於該保護層之第一表面上,且於該拒銲層上形成複數 開口,令該電性接觸墊外露於該拒銲層開口。 15. 如申請專利範圍第14項所述之具微機電元件之封裝件 之製法,其中,該封裝膠體係形成於該拒銲層上。 16. 如申請專利範圍第9項所述之具微機電元件之封裝件 之製法,復包括形成導電凸塊於該電性接觸墊上,以連 接該微機電晶片。 17. 如申請專利範圍第9項所述之具微機電元件之封裝件 之製法,其中,該微機電晶片上具有導電凸塊,以令該 微機電晶片藉由該導電凸塊接置於該電性接觸墊上。 18. 如申請專利範圍第16或17項所述之具微機電元件之封 裝件之製法,其中,該導電凸塊係為金材或銲錫材料。 3 112039
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TW100116620A TW201250947A (en) | 2011-05-12 | 2011-05-12 | Package structure having a micromechanical electronic component and method of making same |
CN2011101452746A CN102774804A (zh) | 2011-05-12 | 2011-05-24 | 具微机电元件的封装件及其制造方法 |
US13/170,424 US8653661B2 (en) | 2011-05-12 | 2011-06-28 | Package having MEMS element and fabrication method thereof |
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CN111003682A (zh) * | 2018-10-08 | 2020-04-14 | 凤凰先驱股份有限公司 | 电子封装件及其制法 |
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