TW201132263A - Method for manufacturing printed wiring board - Google Patents

Abstract

A printed wiring board is manufactured by a method in which an opening is formed in a substrate, and a seed layer for electrolytic plating is formed on an inner wall of the opening and a surface of the substrate. The substrate with the seed layer is placed in an electrolytic plating solution, and an insulative body is placed in the electrolytic plating solution. The substrate and the insulative body are moved relative to each other to form an electrolytic plated film on the substrate and fill the opening with the electrolytic plated film. A conductive circuit is formed on the substrate. The electrolytic plating solution includes copper sulfate, sulfuric acid, and iron ions.

Description

</ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Prior Art] In connection with a method of manufacturing a printed wiring board, the international publication WO 2006/0333 15 A1 discloses a method of filling a through hole and a non-penetrating hole with an electrolytic plating film while bringing the insulator into contact with the surface to be plated. SUMMARY OF THE INVENTION In a method of manufacturing a printed wiring board according to an embodiment of the present invention, an opening is formed in a substrate, and a seed layer for electrolytic bonding is formed on an inner wall of the opening and a surface of the substrate. The substrate having the seed layer is placed in the electrolytic key coating&apos; and the insulator is placed in the electrolytic money coating. The substrate and the insulator are moved relative to each other to form an electrolytic plating film on the substrate and to fill the opening with an electrolytic plating film. A conductive circuit is formed on the substrate. The electrolytic bond coating includes copper sulfate, sulfuric acid and iron ions. [Embodiment] A more complete understanding of the present invention, together with the appended claims. Embodiments will now be described with reference to the drawings, wherein like reference numerals refer to the &lt;First Embodiment&gt; A plating apparatus for use in a method of manufacturing a printed wiring board according to a first embodiment of the present invention is described with reference to FIG. The plating apparatus 1〇 includes a plating tank 14, a 150468.doc 201132263 ring device 16, an insulator (2〇A, 20B), a lifting rod (elevat〇r “.^ and a lifting device 24^ filled with a plating solution 12) The groove 14. The circulation device i6 circulates the plating solution 12. The insulator (2〇A) is composed of a porous material such as a porous resin (for example, a sponge). To plate the surface of the printed wiring board 30, an insulator (20A) It is placed in the plating solution 12 and brought into contact with one of the surfaces to be plated (for example, the front surface) of the printed wiring board 3. The insulator (20B) is porous by a porous resin such as a sponge. In order to plate the surface of the printed wiring board 30, the insulator (20B) is placed in the plating liquid 12 and brought into contact with another surface to be plated (for example, the rear surface) of the printed wiring board 30. The device 24 vertically moves the insulator (2〇A, 2〇B) along the printed wiring board 30. The insulators (2〇a, 20B) are moved by the lift lever 22 which is vertically moved by the lifting device 24. The printed wiring board 30 is connected To the cathode side. In the ore tank 14 'set in the picture is not shown The anode is shown, and a metal source such as a copper ball is stored in the anode. The ore coating 12 contains, for example, copper sulfate, sulfuric acid, and iron ions. The plating solution 12 before the start of plating contains ferric ions. The coating process produces 'divalent iron ions, and thus divalent iron ions and ferric iron ions are present in the plating solution 12. Regarding the iron ion source, iron sulfate is preferred. As the iron sulfate 'hydrate system, it is preferred. Preferably, iron sulfate heptahydrate (FeS〇4*7H2〇) is used. By performing dummy plating, the concentration of Fe2+ and the concentration of Fe3+ can be adjusted. Referring to Figures 13A to 13F, the following description uses plating. The coating device 10 forms a method for electrolytically coating a printed wiring board (substrate) 30. In the substrate 30 having a first surface (30A) and a second surface (30B) opposite to the first surface (30A) Openings (31a, 31b) are formed (Fig. 13A). The openings (31a, 31b) include 150468.doc 201132263 for the through holes (through hole conductor openings) and via holes of the via conductors. The middle opening (31a) is a through hole, and the opening (31b) is a non-penetrating hole (passage The body opening forms a seed layer 34 (Fig. 13B) on the inner surfaces of the first surface (3A) and the second surface (30B) and the opening (31a'3 lb) of the substrate 30. As an example of the seed layer, there may be no Electrode coating, sputter film, and vapor deposited film. Alternatively, conductive particles such as Pd or C may be disposed on the inner wall of the through hole and the surface of the substrate to form directly on the surface of the substrate and the inner wall of the opening (3 la, 31b). The electrolytic bond is coated. In this case, the conductive particles are used as a seed layer. In this example, the seed layer 34 is an electrodeless copper plating film. The substrate 30 having the seed layer 34 is placed in the plating solution 12 to form an electrolytic bond film 36. Examples of the composition of the bell coating 12 and the keying conditions are as follows. &lt;Composition of money coating 12&gt;

Copper sulfate concentration: 〇.8±〇.l m〇l/L Sulfuric acid concentration: 0.5±0.15 mol/L

Gas ion "Chenness. 5 ppm to 100 ppm Iron ion concentration: lg / L to 20 g / L * Iron ion concentration is the total value of ferric ion and ferric ion concentration. *Divalent iron ion concentration: ferric ion concentration = 1:2 to 1:4 Additive concentration: 5 ± 1 mol / L &lt; plating conditions &gt; Current Society, degree. 0.5 A/dm2 to 5 A/dm2 The insulator (20A) is pressed against the first surface (30A) of the substrate 30, and the insulator 150468.doc 201132263 (20B) is pressed against the second surface (30B) of the substrate 30 (Fig. 13C) » when the insulators (20A, 20B) are in contact In the case of the substrate 30, the insulator (2A, 20B) is preferably further advanced (for example) from 1.0 mm to 15.0 mm into the surface of the substrate after the insulator (20A, 20B) is in contact with the surface of the substrate (surface to be plated). If the amount of advancement is less than 1. 〇 mm, the result tends to be the same as that of the unused insulator (2〇a, 20B). If the amount of advancement exceeds 15.0 mm, the thickness of the coating in the openings (3 la, 31b) tends to vary because the supply of the coating 12 will be hindered. The optimum amount of advancement is 2 mm to 8 mm. The change in the coating on the surface of the substrate and in the openings (3 la, 3 lb) will be small. Further, the thickness of the electrolytic plating film formed on the surface of the substrate is lowered. When the insulators (20A, 20B) are in contact with the substrate 30, the substrate 30 and the insulators (20A, 20B) are moved relative to each other (Fig. 13C). The moving speed of the insulator (20A, 20B) with respect to the substrate 30 is preferably from U meters/minute (m/min) to 16.0 m/min. Within this range, iron ions can be appropriately fed to the surface of the substrate. As a result, the film thickness of the electrolytic plating film 36 formed on the surface of the substrate can be reduced. Further, since the plating liquid 12 can be fed into the openings (31a, 3 lb) by the insulators (2A, 20B), the plating can be filled in the openings (3u, 3 lb). In the present embodiment, the substrate 3 (see Fig. 13B) having the seed layer 34 is placed in the above plating solution 12. Next, the insulator (2〇A, 2〇B) is pressed against the substrate 30. When the insulators (20A, 20B) are pressed against the substrate 3, the insulators (20A, 20B) and the substrate 30 are moved relative to each other. While maintaining these conditions, an electrolytic plating film 36 is formed on the surface of the substrate 30 and in the openings (31a, 31b) (Fig. 13C) 〇 150468.doc 201132263 In the present embodiment, when the insulators (20A, 20B) When the substrate 30 is brought into contact with the electrolytic plating solution containing iron ions, the electrolytic plating film 36 is formed on the surface of the substrate 3 and the openings (3 la, 31b) of the substrate 3 . Therefore, the ferrous iron ions can be easily fed to the surface of the substrate to be bonded. Without wishing to be bound by any theory, it is believed that the following reaction occurs on the surface of the bell membrane. Reaction formula (1): 2Fe3++Cu=&gt;2Fe2++Cu2+ If the above reaction occurs, it is considered that deposition and dissolution of the plating film occur in a region in contact with the insulator (2〇a, 20B). It is considered that the growth rate of the plating film on the surface of the substrate will be lowered. In contrast, since the plating film in the openings (31a, 31b) is not in contact with the insulator (2A, 2B) at the starting point of the plating, it is considered that the electrolytic plating film 36 is at the opening (3 1 The growth in a, 3 1 b) will rarely be inhibited by iron ions. Since the ferric ions diffuse into the openings (31a, 3 lb) by the concentration gradient, the concentration of the ferric ions is considered to be low. Therefore, in this embodiment, when the thickness of the electrolytically plated crucible 36 on the surface of the substrate is relatively small, it is considered that the electrolytic plating film 36 can fill the openings (31a, 31b) (including the through holes and the non-penetrating holes (via holes). When the electrolytic plating film 36 in the openings (31a, 31b) is gradually thickened, the insulator (2A, 2B) starts to come into contact with the surface of the electrolytic plating film 36 of the filling opening (31a, 31b). When contacted with the insulators (20A, 20B), the electrolytic plating film % of the filling openings (3U, 31b) and the electrolytic plating film 36 on the surface of the substrate have a growth rate which is considered to be the same. Therefore, it is considered that this embodiment The electrolytic plating film 36 obtained in the film is uniform and thin. It is possible to suppress an alternative mechanism of deposition of the plating layer by the following reaction without wishing to be bound by any theory. 150468.doc 201132263 Reaction formula (2) . Fe3+ +Cu2++3e-=&gt;Fe2++Cu In the reaction formula (2), since the electrons used for depositing the copper plating film are used to reduce ferric ions to divalent iron ions, it is considered that the coating is suppressed. Growth in the reaction formula (2), since it is the same as in the reaction formula (1) The reason is that when the thickness of the key film on the surface of the substrate remains relatively small, it is considered that the plating layer is filled in the openings (31a, 31b). The above reaction (reaction formula (1) and reaction formula (2)) can be similarly different from iron ions. Ion occurs. However, in this embodiment, since it is considered that the iron ions are forcibly fed to the surface of the plating film using the insulator (20A, 20B), it is considered that iron ions are preferably used as the metal ions added to the plating solution 12. This may be because the ionization tendency of iron and copper is similar. For example, compared with the prior art, when the insulator (20 A, 20B) is in contact with the substrate 30 in the electrolytic ore coating containing iron ions, the substrate is The method of forming a clock film on the surface of the substrate 30 and in the openings (3 la, 31b) is excellent in forming fine wiring. When electrolytic plating is formed on a substrate having an opening by using the embodiments of the present invention and the prior art In the case of a film, the thickness of the electrolytic plating film obtained by using the embodiment of the present invention (the thickness of the plating film formed on the substrate) is substantially the thickness of the electrolytic plating film obtained by using a conventional technique (the plating film formed on the substrate) One-half to one-third of the degree. In the same manner as in the prior art, the filling opening may be coated in the embodiment of the present invention. By using the plating method of this embodiment, the filling opening (31a) may be plated. , 31b), and the surface of the coating exposed through the openings (31a, 3 lb) tends to be flat (see FIGS. 13D and 13E). Further, the top surface of the bonding film exposed through the openings (3la, 31b) and the surface of the substrate The top surface of the mineral film formed thereon may be at the same height, and the electrolytic plating film 36 on the surface of the substrate may be formed thinly. According to the plating method of the present embodiment, it is possible to simultaneously achieve the filling of the deep opening by the plating film and the reduction of the thickness of the plating film formed on the surface of the substrate. Thereafter, by patterning the thin electrolytic plating film 36 and the seed layer 34 on the surface of the substrate, a fine pitch conductive circuit can be formed (Fig. 13F). At the same time, the via conductor 42, the via conductor 60 and the conductive circuit 58 are completed. Further, if an insulator (20A, 20B) composed of a porous resin (e.g., sponge) or a brush is used, ferric ions tend to be fed to the surface to be plated. This may be because the plating solution 12 can be easily fed onto the surface of the substrate via the gap between the pores of the porous resin or the bristles of the brush. The plating film formed on the surface of the substrate tends to be thin. In the region where the insulators (20A, 20B) are in contact, the growth of the electrolytic ore film 36 is slowed down. That is, iron ions are forcibly fed to the plating interface by the insulator (2A, 20B), and a reaction of reducing ferric ions to divalent iron ions occurs, and deposition of copper is suppressed. In the penetration hole (3 1 a) which is not in contact with the insulator (2〇A, 2〇B), 'trivalent iron ions are not forcibly fed, but only diffuse from the concentration gradient to the mineral deposit interface. The degree of reduction of the ferric ion is low, and the electrolytic plating film 36 is grown. Therefore, the electrolytic plating film 36 on the surface of the core substrate can be thinly formed while filling the via conductor 42. According to an embodiment of the present invention, not only the opening may be filled with an electrolytic plating film, but also the electrolytic plating film formed on the surface of the substrate may be thin. Therefore, embodiments of the present invention are particularly suitable for forming electrolysis by forming an electrolytic plating film on the entire surface of a substrate, and forming a conductive circuit by etching, such as a subtractive method and a tenting method. Plating 150468.doc 201132263 Coating procedure. Embodiments of the present invention are advantageous for manufacturing highly integrated panels because of the fine pitch conductive circuitry that can be formed. <Manufacturing Method 1> A method of manufacturing a multilayer printed wiring board (manufacturing method 1) will be described with reference to Figs. 1A to 6 . Figure 6 is a cross-sectional view of a multilayer printed wiring board 1 . The multilayer printed wiring board 100 has a core substrate 30, a conductive circuit 40, a via conductor 42 and an interlayer resin insulating layer (50, 150). » The core substrate 30 has a first surface (top surface in FIG. 6) and the same A surface is opposite the second surface (the bottom surface in Figure 6). The conductive circuit 40 is disposed on the first surface and the second surface of the core substrate 30. The conductive circuit 40 is connected by a via conductor 42. An interlayer resin insulating layer 5 is formed on the core substrate 30 and the conductive circuit 40, and a via conductor 60 and a conductive circuit 58 are formed in the interlayer resin insulating layer 5?. An interlayer resin insulating layer 150 is formed on the interlayer resin insulating layer 5, and a via conductor 160 and a conductive circuit 158 are formed in the interlayer resin insulating layer 5'. A solder resist layer 70 having an opening portion 71 is formed on the via conductor 16A, the conductive circuit 158, and the interlayer resin insulating layer 15? on the via conductor and the conductive circuit 158 exposed through the opening portion 71 in the solder resist layer 70. Bumps (76U, 76D) are formed. Hereinafter, the steps of manufacturing the multi-layer printed wiring board 100 shown in Fig. 6 will be described with reference to Figs. iA to 5B. A double-sided copper clad laminate having a thickness of, for example, 〇·8 _ is prepared (Fig. 1A). The core of the double-sided copper-clad laminate and the substrate (insulating substrate) 3 Q are made of glass epoxy resin or BT (bis-synyleneimine triazine) resin and a core material such as glass cloth. Copper foil (130A, 130B) is laminated on the first surface of the core substrate 30 and the surface of the 150468.doc 201132263 opposite the first surface. A through hole 32 (Fig. 2) for a via conductor is formed on the double-sided copper clad layer using a drill or a laser. The catalyst core is attached to the surface of the double-sided copper-clad laminate and the inner wall surface of the through-hole 32 for the via-hole conductor (the core substrate 30 having the attached catalyst is not shown in the drawing is immersed in a commercially available electrodeless The copper plating solution (such as THRU-CUP manufactured by C lJyemura Co., Ltd.) is opened on the surface of the substrate and the inner wall of the penetration hole 32 to form an electrodeless copper film 34 having a thickness of 0.3 μm to 3.0 μm. (Fig. 1C) After cleaning with 50 ° C water to degrease, washing with 25 ° water and further cleaning with sulfuric acid, the core substrate 3 was immersed in electrolytic copper bath 12 having the following composition. Thereafter, By using the plating apparatus 10 described above with reference to Fig. 9, an electrolytic plating film 36 (Fig. 1D) is formed on both surfaces of the copper-clad laminate and in the penetration holes under the following conditions: &lt;Electrolytic plating solution Composition of 12&gt; Copper sulfate sulfate

0*5 mol/L 〇·8 mol/L

Iron sulfate heptahydrate (FeS〇4.7H2〇) 5g/L Leveling agent 50 mg/L Polishing agent Fe2+:Fe3 + &lt;Electroplating conditions&gt; Current density 1 A/dm2

50 mg/L 1:2 to 1:4

Time 65 minutes Temperature 22±2eC 150468.doc 201132263 Here, as described above with reference to FIG. 9, the insulator (20A, 20B) using the porous resin is vertically moved along the surface to be plated, and electrolysis is formed on the core substrate 3〇. The copper film 36 is plated while the penetration holes 32 are filled with a plating layer. The penetration hole 32 is filled with the electrolytic money copper film 36. During this period, the moving speed of the insulator (20A, 20B) is 7 m/min, the size of the insulator (20A, 20B) is 0.80 with respect to the size of the core substrate, and the pushing amount of the insulator (20A, 20B) is 8 A resist layer 38 having a predetermined pattern is formed on the electrolytic plating film 36 (FIG. 1E), and the electrolytic bond film 36, the electrodeless plating film 34, and the copper foil (130A, which are exposed by the anti-money layer 38 are removed by #etching, 130B), and a via conductor 4 and a conductive circuit 42 are formed (FIG. 2A). A roughened surface (40α) is formed on the entire surface of the conductive circuit 40 and on the top surface of the via-hole conductor 42 (Fig. 2B). &lt;Formation of Accumulation Layer&gt; A resin film (trade name: ABF-45SH, manufactured by Ajinomoto Fine-Techno Co., Inc.) for the interlayer resin insulating layer was laminated on both surfaces of the core substrate 30. Next, an interlayer resin insulating layer 50 is formed on both surfaces of the core substrate 30 by curing the resin film for the interlayer resin insulating layer (Fig. 2C). A via conductor opening (50a) having a diameter of 80 μm is formed in the interlayer resin insulating layer 50 by using a CO 2 gas laser (Fig. 2D). The substrate 30 having the via conductor opening (5〇a) was immersed in a solution containing 60 g/L of permanganic acid at 80 ° C for 1 minute, and included in the via conductor opening 150468.doc •12-201132263 (50a A roughened surface (50α) is formed on the surface of the interlayer resin insulating layer 5 of the inner wall (Fig. 2E). The substrate 30 was immersed in a neutralizing solution (manufactured by Shipley C〇mpany), and then washed with water. Further, a catalyst core (not shown) is attached to the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via conductor opening (50a). The substrate 30 having the attached catalyst is immersed in a commercially available electrodeless copper plating solution to form a thickness of 0.3 μm to 3.0 μm on the surface of the interlayer resin insulating layer 50 and the inner wall of the via conductor opening (5〇a). Electrode copper plating film 52 (Fig. 3A). After being degreased with water at 50 ° C to be degreased, washed with 25 〇c of water and further cleaned with sulfuric acid, the substrate 3 having the interlayer resin insulating layer 5 〇 is immersed in the electrolytic copper plating solution 12 having the same composition as described above. . Using the plating apparatus 1 described above with reference to FIG. 9, under the above conditions, an electrolytic copper plating film 56 (FIG. 3A) is formed on the interlayer resin insulating layer 5 and the via conductor opening (5 〇a). The electrolytic copper plating film 56 fills the via conductor opening (5〇a). Here, as described above with reference to FIG. 9, when the insulator (20A, 20B) using the porous resin is vertically moved along the surface to be plated, the plating layer is filled in the opening (50a), and in the interlayer resin insulating layer 5 An electrolytic copper plating film 56 having a thickness of 12 μm is also formed on the surface. The moving speed of the insulator (20A, 20B) is 7 m/min, the size of the insulator (20 Α, 2 〇Β) is 0.80 with respect to the size of the core substrate 3, and the pushing amount of the insulator (2 〇 α, 20 Β) is 8 Mm. Subsequently, a resist layer 54 is formed on the electrolytic copper plating film 56 (Fig. 3C). The electrolytic plating film 56 and the electrodeless plating film 52 exposed by the anti-money layer 54 are removed by etching. Next, by removing the resist layer 54, a separate upper layer conductive circuit 58 and a filled via 60 (Fig. 3D) are formed. A roughened surface (58α, 6〇α) is formed on the surface of the upper conductive circuit 58 and the filled via 6〇150468.doc •13- 201132263 (Fig. 4A). By repeating the above-described steps described with reference to Figs. 2B to 4A, an additional upper interlayer insulating layer 15?, a conductive circuit 158, and a filled via 16? are formed, and a multilayer wiring board 300 (Fig. 4B) is obtained. A commercially available resist composition (such as SR 7200 manufactured by Hitachi Chemical Co., Ltd.) 70 was applied to both surfaces of the multilayer wiring board 3〇0 to 2 μm thick (Fig. 4C). It took 20 minutes and 70 at 7 inches. (: Drying treatment was performed for 30 minutes. Thereafter, an opening 7i exposing the conductive circuit and the filled via was formed in the solder resist composition by exposure and development processing. Next, by the following conditions, respectively The heat treatment was carried out: 80 〇, 1 hour, 100 ° C for 1 hour, 12 〇 t: 1 hour and 150 ° C for 3 hours, curing the solder resist composition, and forming exposed conductive on the interlayer resin insulating layer The circuit and the solder resist layer 7 through the opening of the filled via. The conductive circuit exposed through the opening in the solder resist layer and the top surface of the filled via serve as pads for mounting electronic components and pins. A nickel layer, a palladium layer and a gold layer are sequentially formed on the exposed pads of the solder resist layer 70. Thereafter, the solder balls are supplied onto the pads and then reflowed. Therefore, solder bumps (welded bodies) are formed on the pads. (76U, 76D). The multilayer printed wiring board 100 (Fig. 6) having the solder bumps (76U, 76D) is completed. &lt;Manufacturing Method 2&gt; Hereinafter, the manufacturing steps according to the manufacturing method 2 will be described with reference to Figs. 7A to 7D. As shown in Figure 7B It is shown that a plating resist 54 is formed on the intermediate substrate in the state shown in Fig. 3A. This is different from the method 1 described above with reference to Figs. 3A to 3D, 150468.doc -14·201132263, in which the method 1 An electrolytic plating film 56 is formed on the entire surface of the electrodeless plating film 53. After degreasing with water at 50 ° C to remove the grease, the substrate 30 is immersed in the method described in Method 1 after being washed with water (25: washing with water and further cleaning with sulfuric acid). In the electrolytic copper plating solution 12 of the same composition, an electrolytic copper plating film 56 is formed on the interlayer resin insulating layer 50 and the via conductor opening under the same conditions as described above, and the via conductor opening is filled with the electrolytic copper plating film 56 (Fig. 7C) Here, as described above with reference to FIG. 9, the insulator (20A, 20B) using the porous resin is vertically moved along the surface to be ore, and electrolytic copper plating is formed on the interlayer resin insulating layer 50 and the via conductor opening. The film 56 is filled with a via conductor at the same time. The via conductor opening is filled with an electrolytic copper plating film 56. The moving speed of the insulator (20A, 20B) is 7 m/min, and the size of the insulator (2〇a, 20B) is relative to the core. The size of the substrate 3〇 is 〇·8〇, and the pushing amount of the insulator (20Α, 20Β) is 8 mm. The plating resist 54 is removed using a 5% KOH solution. Thereafter, the electrodeless plating film 52 not covered by the electrolytic plating film 56 is removed, A separate upper conductive circuit 58 and a filled via 60 are formed (FIG. 7D). Since the subsequent steps are the same as those in the manufacturing method 1, the description thereof is omitted. <Manufacturing Method 3> Hereinafter, the manufacturing according to the description will be described with reference to FIGS. 8-8 to 8F. The manufacturing step of the method 3. This method is an example relating to a method for manufacturing a printed wiring board having an hourglass-shaped through-hole conductor. Here, the hourglass-shaped via-hole conductor indicates a via-hole conductor formed by filling a plating layer into the penetration hole, the penetration hole being firstly tapered from the first surface of the core substrate 30 toward the second surface The opening and 150468.doc 15 201132263 consist of a second opening that tapers from the second surface toward the first surface. A double-sided copper-clad laminate (30C) was prepared by laminating copper matte (130A, 130B) on both surfaces of the core substrate 3. The core substrate 3 has a first surface and a second surface opposite the first surface. Copper (130A) is formed on the first surface of the core substrate 3, and a copper foil (130B) is formed on the second surface of the core substrate 3 (Fig. 8A). A c〇2 laser is applied from the first surface side of the core substrate 30. A first opening (136A) is formed which penetrates the copper braid (13A) and tapers from the first surface of the core substrate 3 toward the second surface (Fig. 8B). The taper from the first surface toward the second surface causes the diameter of the first opening (136A) to gradually decrease from the first surface toward the second surface. Regarding the diameter of the first opening (136A), when the first opening (136A) is divided by a plane parallel to the first surface, if the first opening (1) (4) is circular, the distance across the cross section is a diameter, and An opening (i36A) is elliptical 'the long axis is the diameter. Next, a CO laser is applied from the second surface side of the core substrate 30. The position illuminated by the laser is opposite to the first opening (136A). A second opening (136B) is formed which penetrates the copper box 〇3〇B) and tapers from the second surface of the core substrate 3 toward the first surface. By forming the second opening (136b), the first opening (136A) and the second opening (136B) are joined inside the core substrate 3A and the first opening (136A) and the second opening (1) are formed in the core substrate 30. a penetration hole 136 of the composition (Fig. 8C). The tapering from the second surface toward the first surface causes the diameter of the second opening (136B) to gradually decrease from the second surface toward the first surface. When the second opening is parallel to the first-division, if the second opening is circular, the distance across the cross-section is 150468.doc -16 - 201132263, and if the second opening is elliptical, it is long. The shaft is of a diameter. A seed layer 137 made of a sputter film is formed on the surface of the copper foil (130A, 130B) and the inner wall of the penetration hole 136. The seed layer 137 is made of copper, due to the first opening (136A) and The second opening (136B) is tapered, and the seed layer 137 can be easily formed by sputtering. However, the seed layer 137 can be formed by electrodeless plating. The same ore coating device as described in the manufacturing method 1 is used. 1〇, mineral coating 丨 2, plating method and plating conditions, on the core substrate 39 An electrolytic copper plating film l34 is formed on the first surface and the second surface. During this period, the through hole 丨 36 is filled with the electrolytic copper plating film 134 (Fig. 8E) ^ Although the through hole 32 in the manufacturing method is substantially straight The shape, but the penetration hole 136 in the manufacturing method 3 is hourglass-shaped. When a penetration hole is formed in the same core substrate to have the same diameter (diameter on the front surface and the rear surface of the core substrate), the hourglass The volume of the through hole is smaller than the volume of the linear through hole. Due to this difference, the thickness of the electrolytic plating film on the core substrate in the manufacturing method 3 tends to be higher than that of the electrolytic substrate on the substrate in the manufacturing method 1. The thickness of the film is thin. Thus, a fine conductive circuit can be formed by the manufacturing method 3. In the same manner as in the manufacturing method 1, an anti-surname layer is formed on the electrolytic copper plating film 134. Thereafter, the film is dissolved and removed. The electrolytic plating film 134, the sputtering film 137, and the copper foil (3〇A, 3〇B) exposed by the etching layer are formed. Therefore, an independent conductive circuit (134A) and a via conductor 142 (Fig. 8E) are formed. Forming on the core substrate in the same manner as in Manufacturing Method 1. &lt;Second Embodiment&gt; Referring to Fig. 10 and Fig. U, a mineral depositing apparatus for use in a method of manufacturing a printed circuit board according to a second embodiment of the present invention is described in Fig. 10 and Fig. U. Fig. 11 is a view showing plating. A schematic illustration of a side view of the device 210, and FIG. 10 is a schematic diagram showing the structure of a transport mechanism on one side of a plating tank in the plating apparatus 210. The plating apparatus 210 is used for a flexible printed wiring board. Plating is performed on the strip substrate. In this plating apparatus 21, electrolytic bonding is performed on the surface of one of the strip substrates (230A) pulled out from the reel (298A).条mm wide, 12〇m long strip substrate. Next, the strip substrate (230A) is wound around the reel (298B). The plating apparatus 210 has an insulating cylindrical contact body 220 that is in surface contact with a strip-shaped substrate (230A) to be plated, and a back plate that prevents warping of the strip substrate (230A) caused by the contact body (insulator) 220. 228 and anode 204 » In the anode 204, a copper ball 206 is housed to replenish the copper component in the plating solution. The total length of the plating tank 212 is 20 m. Instead of the insulating material for the contact body 220, a semiconductor contact can also be used. The contact body 220 in the second embodiment has substantially the same function as the insulator (20A, 20B) described in the first embodiment. The contact body 220 is formed by a cylindrical brush made of PVC (polyvinyl chloride) having a height of 200 mm and a diameter of 1 mm. In the contact body 22, the tip end of the brush is in contact with the printed wiring board and is bent. The contact body 220 is supported by a support rod (220A) made of stainless steel and rotated by a gear not shown in the drawing. The formation of the filled via and the conductive circuit using the plating apparatus 210 is described with reference to FIGS. 12A through 12E. Fig. 12A shows a double-sided copper-clad flexible substrate composed of a substrate 230 and copper foils (33U, 33D). A commercially available dry film is laminated on one surface of the substrate 230, and the copper foil (33U) is etched away from the region where the conductive opening 37 is formed through the 150468.doc -18-201132263 road using a known photographic method. A copper foil (33U) was used as a mask to form a via conductor opening 37 by carbon dioxide gas laser (see Fig. 12β). An electrodeless plating film 34 (Fig. 12C)' is formed on the inner wall of the copper foil (3 3U) and the via conductor opening 37, and then the electrolytic coating film 36 is formed using the plating apparatus 21 shown in Fig. 10 (Fig. 12D). The plating film 36 is formed when a portion of the contact body 220 is in contact with at least a portion of the surface of the printed wiring board. The contact body 22 is in contact with the electrodeless plating film 34 on the printed wiring board at the initial point of plating, and is in contact with the electrolytic ore film 36 once the electrolytic bond film 36 is formed. According to the second embodiment, as in the first embodiment, the plating liquid crucible 2 contains copper sulfate, sulfuric acid and iron ions. Compared with the film thickness obtained by using a key coating solution containing no high-concentration ferric ion, since the ore-covering liquid 12 contains ferric ions, the thickness of the electrolytic plating film 36 formed on the surface of the substrate is further increased. small. Further, since the mineral film 36 is formed using the contact body 220, the via conductor opening can be filled with the electrolytic ore film 36. The size of the contact body is preferably the same as or larger than the area to be plated on the strip substrate. The amount of the contact body to be pushed into the printed wiring board (after the tip of the contact body contacts the surface of the printed wiring board, The amount of the tip to be further advanced is preferably from the surface i 〇mrn to 15 〇. If the amount is less than L 〇 mm, the result may be the same as the plating method of the unused contact body. If the amount exceeds 15.0 mm, it is considered It is difficult to feed the ferric ions to the surface of the substrate. Further, the contact body tends to enter the via conductor opening and the via conductor opening, and thus the concentration of ferric ions in the openings is considered to increase. It is preferably 2 mm to 8 mm. This is because the change in the coating film can rarely occur in the monthly package. 150468.doc 201132263 For the contact body, one selected from the group consisting of a flexible brush and a spatula can be preferably used. Since it is flexible, the contact body follows the irregularities on the substrate and can form a coating having a uniform thickness on the uneven surface. A resin brush can be used as the contact body. In this case, the bristle tip and the surface to be plated Contact. Here, the diameter of the bristles is preferably larger than the diameter of the opening, because the bristle tips will not enter the opening and the coating film can be properly filled into the opening. Regarding the resin brush, resistance to the key coating can be used. PP, PVC (polyethylene) or PTFE (polytetrafluoroethylene), etc. Also, resin and rubber can be used. In addition, 'for the bristle tip, resin fabrics such as vinyl chloride woven or non-woven fabric can also be used. Manufacturing Method 4&gt; A printed wiring board manufacturing method (using, for example, subtraction method, ridge method) using a mineral coating device according to the second embodiment will be described with reference to Figs. 12A to 12E. This method is hereinafter referred to as manufacturing method 4. A laminated strip substrate (230A) was used as a starting material in which 9^^ copper foil (33U) was laminated on the front surface (first surface) of a 25 μm thick polyilylimine strip substrate 230' and 12 Μηι copper foil (33D) is laminated on the back surface (second surface) (Fig. 12A). The copper foil on the second surface is covered with a resist layer. 9 μηι copper foil (33U) on the front surface The thickness is adjusted to 7 by light touch After that, black oxidation treatment is performed on the copper mat on the first surface. By irradiating the laser from the first surface side, a through copper foil (33U) and a polyimide substrate strip 230 are formed and reach the copper foil. (33D) the via conductor opening 37 of the rear surface (Fig. 12A). Next, the palladium catalyst is attached to the surface of the strip substrate (230Α) (not shown in the figure). 150468.doc • 20· 201132263 The substrate of the catalyst is immersed in an electrodeless plating solution (Thru-Cup) manufactured by C. Uyemura Co., Ltd., and an electrodeless coating of 1〇4111 thick is formed on the first surface of the strip substrate (230A). (Seed layer) 34 (Fig. 12C) 〇 After being degreased with water at 50 ° C to be degreased, washed with 25 μc of water and further cleaned with sulfuric acid α, the strip substrate (23〇A) was immersed in the composition containing the following composition In the electroplating bath of electrolytic copper plating solution. The electrolytic plating film 36 is formed on the seed layer 34 under the following conditions using the plating apparatus 210' described above with reference to Fig. 10 (Fig. 12D) 〇 &lt;Composition of electrolytic ore coating&gt;

Sulfuric acid 0 J mol/L

Copper sulfate 0.8 mol/L

Iron sulfate heptahydrate (FeS04.7H20) 100 g/L

Leveling agent 50 mg/L

Polishing agent 5 0 mg/L

Fe : Fe 1:2 to 1:4 &lt; Electrolytic plating conditions &gt; Current agronomy 5·0 mA/cm 2 to 30 mA/cm 2 Time 10 minutes to 90 minutes Temperature 22 Soil 2 . (: Here, it is preferred to set the current density to be 5.0 mA/cm2 to 30 mA/cm2, especially 10 mA/cm2 or more, and then to have a predetermined shape on both surfaces of the strip substrate. The resist layer of the pattern is etched to form a conductive circuit (42U) and a conductive circuit (42D) (Fig. 12E is a so-called phase 150468.doc • 21·201132263 subtraction or bulging method. &lt;Manufacturing method 5&gt; The electrolytic plating composition in the production method 3 is the same as in the production method 3. The material is improved to the following group &lt;electrolytic bell coating composition&gt;

0.5 m〇l/L 0.8 m〇l/L

Iron sulfate heptahydrate (FeS04.7H2〇) 5〇g/L leveling agent 5〇mg/L polishing agent Fe2+:Fe3 + <Manufacturing method 6&gt;

50 mg/L 1:2 to 1:4 The electrolytic plating solution compound in the production method 3. The rest is the same as in the manufacturing method 3. &lt;Composition of electrolytic ore coating&gt; The conjugate was changed to the following group

Barium sulphate.5 mol/L Copper sulphate.8 mol/L Iron sulphate heptahydrate (FeS04.7H2C〇100 g/χ Leveling agent 50 mg/L Polishing agent 50 mg/L Fe2+:Fe3+ 1:2 to 1: 4 When the manufacturing method 5 and the manufacturing method 6 are compared, the coating exposed by the opening in the manufacturing method 6 tends to be concave. This is because the steel in the opening is due to the amount of ferric ions in the manufacturing method 6. Larger and slower to grow. 150468.doc •22- 201132263 The iron ion/density is 几8 to 10 g/L, and the coating exposed by the opening will exhibit a higher flatness characteristic. Therefore, it is easy to apply on the coating. The layer forms an interlayer insulating layer. The iron ions in the plating solution are divalent iron ions and ferric ions. If the concentration of divalent iron ions in the electrolytic plating solution and the ferric ions are The ratio of the ratio is in the range of 1:2 to 1:4, which will effectively inhibit the deposition of the mineral film on the surface of the substrate. Both filling the opening and reducing the film thickness of the film on the surface of the substrate tend to be achieved. (FeS04.7H20) is preferably added to the L000 mL electrolytic plating solution in an amount of 5 g to 100 g. If the iron ion concentration is from 1 g/L to 20 g/L In the range, the opening may be filled with a plating layer while reducing the thickness of the film on the substrate. <Production Method 7> The composition of the electrolytic plating solution in the production method 3 is changed to the following composition. Same as in 3. &lt;Composition of electrolytic money coating&gt; Copper sulfate sulfate

0-65 mol/L 〇·7 mol/L iron sulfate heptahydrate (Fes〇4.7H2〇) 50 g/L leveling agent 50mg&amp;

50 mg/L 1:2 to 1:4 Polishing agent Fe2+:Fe3 + &lt;Manufacturing method 8&gt; The composition of the electrolytic plating solution of φ Τ in the manufacturing method 3 was changed to the following composition. The rest is the same as in the manufacturing method 3. &lt;Composition of electrolytic plating solution&gt; 150468.doc -23- 201132263

Sulfuric acid 0.35 mol/L

Copper sulfate 0.9 mol/L

Iron sulfate heptahydrate (FeS〇4'7H20) 50 g/L

Leveling agent 50 mg/L

Polishing agent 50 mg/L

Fe2+:Fe3+ 1:2 to 1:4 In the embodiments and examples of the present invention, the insulator is in contact with the surface to be plated, and is electrolytically bonded while moving the insulator relative to the surface to be plated. On the surface to be forged in contact with the insulator, the growth of the bell film is slowed down. It is considered that the iron ions are forcibly fed to the surface to be plated by the insulator, resulting in a reduction reaction of iron ions on the surface to be plated. Therefore, it is considered that the growth of the electrolytic plating film will be suppressed. In contrast, in the region where the insulator is not in contact, since the concentration gradient causes the iron ions to diffuse onto the surface to be clocked, the reduction reaction of iron ions tends to be less likely to occur on the surface to be bonded. Therefore, it is considered that the growth rate of the electrolytic plating film will be faster. Therefore, the electrolytic plating film grows faster in the via conductor opening and the via conductor opening, but it is suppressed that the plating film on the surface to be plated other than the opening becomes too thick. That is, the via conductor opening and the via conductor opening must be filled with an electrolytic plating film, and compared with the thickness of the electrolytic plating film formed in the opening or the film thickness of the conductive circuit in the prior art, The plating film on the surface to be plated (substrate surface) can be formed relatively thin. In the embodiments and examples of the present invention, since a thin plating film is patterned, a finer conductive circuit can be formed more easily than in the conventional case. The order and content of the steps in the above-described embodiment of the present invention can be freely changed without departing from the gist of the present invention. Further, the two-step example may be omitted depending on the needs of use, etc., and correction may be made based on image presentation data different from the vector data. It will be apparent that various modifications and variations of the present invention are possible in light of the above teachings. Therefore, it is to be understood that the invention may be practiced otherwise than as specifically described herein. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1A are cross-sectional views showing steps of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. 2A through 2E are cross-sectional views showing the steps of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. 3A to 3D are cross-sectional views showing the steps of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. 4A through 4C are cross-sectional views showing the steps of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. 5A and 5B are cross-sectional views showing the steps of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. Figure 6 is a cross-sectional view of a multi-layer printed wiring board produced by a manufacturing method according to an embodiment of the present invention. 7A through 7D are cross-sectional views showing the steps of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. 8A through 8F are cross-sectional views showing the steps of a method of manufacturing a printed wiring board according to an embodiment of the present invention. Figure 9 is a perspective view schematically showing the structure of a plating apparatus used in a method of manufacturing a printed circuit board according to an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic illustration showing the structure of a conveying mechanism in a plating tank of a plating apparatus in a method of manufacturing a printed wiring board according to an embodiment of the present invention. Fig. 11 is a schematic illustration showing the structure of a conveying mechanism in a plating tank of a plating apparatus in a method of manufacturing a printed wiring board according to an embodiment of the present invention. 12A through 12E are cross-sectional views showing the steps of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. 13A through 13F are cross-sectional views showing the steps of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. [Main component symbol description]

10 12 14 16 20A 20B 22 24 30 30A 30B 30C Plating device plating solution plating tank circulation device insulator insulator lifting rod lifting device printed wiring board / core substrate first surface second surface double-sided copper layer 150468.doc • 26 - 201132263 31a Opening 3 1b Opening 32 Penetration hole 33D Brass 33U Copper H 34 Seed layer 36 Electrolytic plating film 37 Via conductor opening 38 Anti-contact layer 40 Conductive circuit 40α Roughened surface 42 Through-hole conductor 42D Conductive circuit 42U Conductive circuit 50 interlayer resin insulating layer 50a via conductor opening 50α roughened surface 52 electrodeless copper plating film 54 anti-surname 56 electrolytic copper plating film 58 conductive circuit 5 8α roughening surface 60 via conductor 60α roughening surface 150468.doc -27 - 201132263 70 solder mask 71 opening portion 76D solder bump 76U solder bump 100 multilayer printed wiring board 130A copper pig 130B copper 134 electrolytic copper plating film 134A conductive circuit 136 through hole 136A first opening 136B second opening 137 splash Coating 142 Through-hole conductor 150 Interlayer resin insulating layer 158 Conductive circuit 160 Via conductor 204 Anode 206 Copper ball 210 Plating device 212 Mine groove 220 Contact body 220A Support rod 228 Back plate 150468.doc -28 · 201132263 230 Substrate 230A Strip substrate 298A Reel 298B Reel 300 Multilayer wiring board 150468.doc -29

Claims (1)

201132263 VII. Patent application scope: 1 . A method for manufacturing a printed wiring board, comprising: forming an opening in a substrate; forming an electrolysis key on an inner wall of one of the sinuous openings and a surface of the substrate Coating a seed layer; placing the substrate having the seed layer in an electrolytic key coating; placing an insulator in the electrolytic plating solution; moving the substrate and the insulator relative to each other to be on the substrate Forming an electrolytic plating film thereon and filling the opening with the electrolytic plating film; and forming a conductive circuit on the substrate, wherein the electrolytic plating solution comprises copper sulfate, sulfuric acid and iron ions. 2. The method of claim 1, wherein one of the iron ions is derived from iron sulfate. 3. The method of claim 1, wherein the iron ions comprise divalent iron ions and divalent iron ions, and a ratio of the divalent iron ions to the ferric ions in the electrolysis bond coating is 1:2 to 1:4. 4. The method of claim 2, wherein the ferric sulphate concentration is from 5 § to 1 〇〇 g/L of FeS 〇 4.7H20. 5. The method of claim 1, wherein the insulator comprises a material selected from the group consisting of long fibers, a porous resin, a fibrous resin, and rubber. 6. The method of claim 1, wherein the insulator comprises a porous ceramic or a porous resin. 7. The method of claim 1, wherein the insulator comprises a brush, and the brush 150468.doc 201132263 has bristles comprising a resin. 8. The method of claim 1, wherein the insulator comprises a resin fiber. 9. The method of claim 1, wherein the iron ion concentration is from 1 g/L to g/L. 150468.doc