KR20110025612A - Method for manufacturing printed wiring board - Google Patents

Abstract

PURPOSE: A method for manufacturing a printed circuit board is provided to form a conductive circuit in a substrate by forming a seed layer for electroplating on the inside of an opening and the surface of a substrate. CONSTITUTION: In a method for manufacturing a printed circuit board, an opening(71) is formed in a substrate(30). A seed layer for electroplating is formed on the inside of an opening and the surface of the substrate. An electroplating film is formed on the substrate. The opening is filled with the electroplating film. A conductive circuit(158) is formed on the substrate. .

Description

Manufacturing method of printed wiring board {METHOD FOR MANUFACTURING PRINTED WIRING BOARD}

Cross Reference of Related Application

This patent application claims the benefit of priority to US Provisional Patent Application No. 61 / 239,995, filed Sep. 4, 2009, the content of which is incorporated herein by reference in its entirety.

Regarding a method of manufacturing a printed wiring board, International Publication No. WO 2006 / 033315A1 discloses a method of filling through holes and non-penetrating holes with an electrolytic plating film while the insulator is in contact with a surface to be plated.

In the method for manufacturing a printed wiring board according to one embodiment of the present invention, an opening is formed in the substrate, and a seed layer for electrolytic plating is formed on the inner wall of the opening and the surface of the substrate. The substrate with the seed layer is placed in an electrolytic plating solution and an insulator is placed in the electrolytic plating solution. The substrate and the insulator are moved relative to each other to form an electroplated film on the substrate and fill the opening with the electroplated film. A conductive circuit is formed on the substrate. The electrolytic plating solution contains copper sulfate, sulfuric acid, and iron ions.

A more complete understanding of the present invention and many of the attendant advantages of the present invention are readily attained, with better understanding with reference to the following detailed description when considered in conjunction with the accompanying drawings.
1A-1E are cross-sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board in accordance with one embodiment of the present invention.
2A-2E are cross-sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
3A-3D are cross-sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
4A-4C are cross-sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
5A and 5B are cross-sectional views showing steps of a method of manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
6 is a cross-sectional view of a multilayer printed wiring board produced by the manufacturing method according to one embodiment of the present invention.
7A-7D are cross-sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
8A-8F are cross-sectional views illustrating steps of a method of manufacturing a printed wiring board according to one embodiment of the present invention.
9 is a perspective view schematically showing the structure of a plating apparatus used in the method of manufacturing a printed wiring board according to one embodiment of the present invention.
10 is a schematic diagram showing the structure of a conveyor mechanism in a plating tank of a plating apparatus used in the method of manufacturing a printed wiring board according to one embodiment of the present invention.
Fig. 11 is a schematic diagram showing the structure of a conveyor mechanism in a plating tank of a plating apparatus used in the method for manufacturing a printed wiring board according to one embodiment of the present invention.
12A-12E are cross-sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board according to one embodiment of the present invention.
13A-13F are cross-sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board according to one embodiment of the present invention.

DETAILED DESCRIPTION Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout the several views.

≪ First Embodiment >

The plating apparatus used in the method of manufacturing a printed wiring board according to the first embodiment of the present invention will be described with reference to FIG. The plating apparatus 10 includes the plating tank 14, the circulation device 16, the insulators 20A and 20B, the lifting bar 22, and the lifting device 24. The plating tank 14 is filled with the plating solution 12. The circulation device 16 circulates the plating solution 12. Insulator 20A is made of a porous material such as a porous resin (for example, a sponge). In order to plate the surface of the printed wiring board 30, an insulator 20A is placed in the plating solution 120 and comes into contact with one of the surfaces to be plated, for example, the front surface of the printed wiring board 30. The insulator 20B is made of a porous material such as a porous resin (for example, a sponge). In order to plate the surface of the printed wiring board 30, an insulator 20B is placed in the plating solution 12 and brought into contact with another surface to be plated (eg, the back surface) of the printed wiring board 30. The elevating device 24 moves the insulators 20A, 20B vertically along the printed wiring board 30. The insulators 20A and 20B are moved by the lifting bar 22 that moves vertically by the lifting device 24. The printed wiring board 30 is connected to the cathode side. Inside the plating tank 14, an anode not shown in the figure is provided, and a metal source such as copper ball is stored at the anode. The plating solution 12 contains copper sulfate, sulfuric acid, and iron ions, for example. The plating solution 12 before the plating is started contains iron (III) ions. As the plating proceeds, iron (II) ions are produced, and therefore iron (II) and iron (III) ions are present in the plating solution 12. Regarding the iron-ion source, iron (II) sulfate is preferred. Hydrate is preferred as iron sulfate, and iron sulfate 7-hydrate (FeSO ₄ · 7H ₂ O) is preferred. By performing a dummy plating, the concentration and the concentration of Fe ^{3 +} Fe ^{2 +} in can be controlled.

13A to 13F, a method of using the plating apparatus 10 to form an electroplated film for the printed wiring board (substrate) 30 is described below. Openings 31a and 31b are formed in the substrate 30 having the first surface 30A and the second surface 30B opposite the first surface 30A (FIG. 13A). The openings 31a and 31b include through holes and via holes for the through-hole conductor (through-hole conductor opening). In this example, the opening 31a is a through hole and the opening 31b is a non-penetrating hole (via-conductor opening). The seed layer 34 is formed on the first and second surfaces 30A and 30B of the substrate 30 and the inner walls of the openings 31a and 31b (FIG. 13B). As examples of seed layers, electroless plated films, sputtered films and vacuum deposited films can be listed. Alternatively, by providing conductive particles such as Pb or C on the inner wall of the through hole and the substrate surface, an electrolytic plating film can be formed directly on the inner surface of the substrate surface and the openings 31a and 31b. In this case, the conductive particles act as seed layers. The seed layer 34 in this example is an electroless copper plated film. The substrate 30 having the seed layer 34 is positioned in the plating solution 12 to form the electroplating film 36. Examples of the composition and the plating conditions of the plating solution 12 are as follows.

<Composition of Plating Solution 12>

Copper sulfate concentration: 0.8 ± 0.1 mol / L

Sulfuric acid concentration: 0.5 ± 0.15 mol / L

Chloride ion concentration: 5-100 ppm

Iron ion temperature: 1 g / L-20 g / L

* Iron ion temperature is the total value of the concentration of iron (II) ions and iron (III) ions.

* Concentration of iron (II) ions: Concentration of iron (III) ions = 1: 2-1: 4

Additive Concentration: 5 ± 1 mol / L

Plating conditions

Current density: 0.5-5 A / dm ²

Insulator 20A is pressed against the first surface 30A of the substrate 30, and insulator 20B is pressed against the second surface 30B of the substrate 30 (FIG. 13C). When the insulators 20A, 20B are in contact with the substrate 30, preferably the insulators 20A, 20B are brought into the substrate surface, for example, 1.0-15.0 after they start to contact the substrate surface (the surface to be plated). Push further by mm If the amount to be pushed is smaller than 1.0 mm, the result tends to be the same as plating without using the insulators 20A and 20B. When the amount to be pushed exceeds 15.0 mm, the thickness of the plated film in the openings 31a and 31b tends to change because the supply of the plating solution 12 is hindered. The amount to be pushed is most preferably 2-8 mm. The variation of the plated film on the substrate surface and in the openings 31a and 31b will be small. In addition, the thickness of the electroplating film formed on the substrate surface will be reduced.

While the insulators 20A and 20B are in contact with the substrate 30, the substrate 30 and the insulators 20A and 20B move relative to each other (Fig. 13C). The moving speed of the insulators 20A, 20B relative to the substrate 30 is preferably 1.0-16.0 m / min. Within this range, iron ions are properly supplied on the substrate surface. As a result, the film thickness of the electrolytic plating film 36 formed on the substrate surface can be reduced. In addition, since the plating solution 12 can be supplied to the openings 31a and 31b by the insulators 20A and 20B, the plating can be filled in the openings 31a and 31b.

In this embodiment, the substrate 30 having the seed layer 34 (see FIG. 13B) is located in the plating solution 12 described above. Thereafter, the insulators 20A and 20B are pressed against the substrate 30. While the insulators 20A, 20B are pressed against the substrate 20, the insulators 20A, 20B and the substrate 30 move relative to each other. While these conditions are maintained, an electroplated film 36 is formed on the surface of the substrate 30 and in the openings 31a and 31b (Fig. 13C).

In the embodiment, while the insulators 20A, 20B are in contact with the substrate 30 in the electrolytic plating solution containing iron ions, the electrolytic plating film 36 is on the surface of the substrate 30 and of the substrate 30. It is formed in the openings 31a and 31b. Thus, iron (III) ions can be easily supplied onto the substrate surface to be plated. Without wishing to be bound by any theory, it is believed that the following reaction occurs on the surface of the plated film.

Scheme (1): 2Fe ^{3 +} + Cu ⇒ 2Fe ^{2 +} + Cu ^{2 +}

When the above reaction equation occurs, it is considered that deposition and dissolution of the plated film occur in the region in which the insulators 20A and 20B are in contact with each other. The growth rate of the plated film on the substrate surface is thought to be slow. On the contrary, since the plating film in the openings 31a and 31b does not contact the insulators 20A and 20B at the starting point of plating, the growth of the electrolytic plating film 36 in the openings 31a and 31b is almost caused by iron ions. It is thought that it is not suppressed. Since the iron (III) ions diffuse into the openings 31a and 31b through the concentration gradient, the concentration of the iron (III) ions is considered to be low. Therefore, in the embodiment, the openings 31a and 31b (including through holes and non-through holes (via holes)) can be filled with the electrolytic plating film 36 while the thickness of the electrolytic plating film 36 on the substrate surface is I think it's relatively small. When the electroplating film 36 in the openings 31a and 31b gradually thickens, the insulators 20A and 20B come into contact with the surface of the electroplating film 36 filling the openings 31a and 31b. When in contact with the insulators 20A and 20B, the electroplated film 36 filling the openings 31a and 31b and the electroplated film 36 on the substrate surface have a growth rate considered to be the same. Therefore, the electroplated film 36 obtained in this embodiment is considered to be uniform and thin.

Without wishing to be bound by any theory, alternative mechanisms are possible where plating is inhibited from deposition through the following reactions.

Scheme (2): Fe ^{3 +} + Cu ^{2 +} + 3e ^- ⇒ Fe ^{2 +} + Cu

In Scheme (2), since electrons for depositing a copper plated film are used to reduce iron (III) ions to iron (II) ions, it is considered that growth of the plated film is suppressed. In Scheme (2), for the same reason as in Scheme (1), it is thought that the thickness of the plated film on the substrate surface is kept relatively small while the plating is filled in the openings 31a and 31b.

The reactions (Scheme (1) and (2)) can also occur with ions other than iron ions. However, in the embodiment, since iron ions are considered to be forcibly supplied onto the plated film surface using the insulators 20A and 20B, iron is considered to be preferable as the metal ions added to the plating solution 12. This may be because iron and copper have similar ionization tendencies. Compared with the prior art, insulators 20A and 20B form a plating film in the openings 31a and 31b of the substrate 30 and on the substrate surface while contacting the substrate 30 in an electrolytic plating solution containing iron ions. The method of making is excellent in forming fine wiring, for example. When the electrolytic plating film is formed on a substrate having an opening using an embodiment of the present invention and the conventional technique, the thickness of the electroplating film obtained using the embodiment of the present invention (the thickness of the plating film formed on the substrate) is conventionally It is approximately 1/2 to 1/3 of the thickness (thickness of the plated film formed on the substrate) of the electroplated film obtained using the technique. The openings can be filled with the plating film in the embodiment of the present invention as in the prior art.

By using the plating method of the embodiment, the openings 31a and 31b can be filled with plating, and the surface of the plating film exposed through the openings 31a and 31b tends to be flat (see FIGS. 13D and 13E). Further, the upper surface of the plated film exposed through the opening and the upper surface of the plated film formed on the substrate surface may be located at the same level, and the electrolytic plated film 36 on the substrate surface may be thinly formed. According to the plating method of this embodiment, filling the deep openings with the plating film and reducing the thickness of the plating film formed on the substrate surface can be achieved at the same time. Thereafter, by patterning the thin electroplating film 36 and the seed layer 34 on the substrate surface, a fine-pitch conductive circuit can be formed (FIG. 13F). At the same time, the through-hole conductor 42, the via conductor 60 and the conductive circuit 58 are completed.

In addition, when insulators 20A and 20B made of a porous resin (for example, a sponge) or a brush are used, iron (III) ions tend to be supplied on the surface to be plated. This is because the plating solution 12 is easily supplied on the substrate surface through the space between the pores of the porous resin or the bristle of the brush. The plating film formed on the substrate surface tends to be thin.

In the region where the insulators 20A and 20B contact, the growth of the electroplated film 36 is slowed down. That is, iron ions are forcibly supplied by the insulators 20A and 20B on the plating interface, a reaction for reducing the iron (III) ions to iron (II) ions occurs, and the deposition of copper is suppressed. In the through hole 31a to which the insulators 20A and 20B do not contact, iron (III) ions are not forcibly supplied but are only diffused by concentration gradient on the plating interface, and the reduction reaction of iron (III) ions is caused. The degree is low, and the electroplated film grows. Therefore, the electrolytic plating film 36 on the surface of the core substrate can be thinly formed while the through-hole conductor 42 is filled.

According to the embodiment of the present invention, not only the opening can be filled with the electroplating film, but the electroplating film formed on the substrate surface can be kept thin. Accordingly, embodiments of the present invention are electrolytically carried out by a method (such as a subtractive method and a tenting method) in which an electrolytic plating film is formed on the entire substrate surface and a conductive circuit is formed by etching. It is especially applicable to the procedure of forming a plating film. Since fine-pitch conductive circuits can be formed, applying embodiments of the present invention is desirable for manufacturing highly integrated plates.

<Manufacturing method 1>

The method (manufacturing method 1) of manufacturing a multilayer printed wiring board is demonstrated with reference to FIGS. 1A-6.

6 is a cross-sectional view of the multilayer printed wiring board 100. The multilayer printed wiring board 100 has a core substrate 30, a conductive circuit 40, a through-hole conductor 42, and interlayer resin insulating layers 50, 150. The core substrate 30 has a first surface (top surface in FIG. 6) and a second surface (bottom surface in FIG. 6) opposite the first surface. The conductive circuit 40 is provided on the first and second surfaces of the core substrate 30. The conductive circuit 40 is connected by the through-hole conductor 42. An interlayer resin insulating layer 50 on which the via conductor 60 and the conductive circuit 58 are formed is formed on the core substrate 30 and the conductive circuit 40. The interlayer resin insulating layer 150 on which the via conductor 160 and the conductive circuit 158 are formed is formed on the interlayer resin insulating layer 50. A solder-resist layer 70 having an opening 71 is formed on the via conductor 160, the conductive circuit 158, and the interlayer resin insulating layer 150. Bumps 76U and 76D are formed on the via conductor 160 and the conductive circuit 158 exposed through the opening 71 in the solder-resist layer 70.

Next, the steps of manufacturing the multilayer printed wiring board 100 shown in FIG. 6 will be described with reference to FIGS. 1A to 5B.

For example, a double-sided copper-clad laminate having a thickness of 0.8 mm is prepared (FIG. 1A). The core substrate (insulation substrate; 30) of the double-sided copper foil laminate is made of a core material such as glass-epoxy resin or BT (bismaleimide triazine) resin and glass fabric. On the first surface of the core substrate 30 and on the second surface opposite the first surface, copper foils 130A and 130B are laminated. Through holes 32 for through-hole conductors are formed in the double-sided copper foil laminate using a drill or a laser (FIG. 1B).

A catalyst nuclei is attached to the inner wall surface of the through hole 32 for the through-hole conductor and the surface of the double-sided copper foil laminate (not shown in the figure). The core substrate 30 with the attached catalyst is immersed in a commercially available electroless copper plating solution (such as THRU-CUP manufactured by C. Uyemura Co., Ltd.) to provide substrate surface and through holes 32 An electroless copper plating film 34 having a thickness of 0.3-3.0 mu m is formed on the inner wall of the film (FIG. 1C).

After cleansing with 50 ° C. water for washing, washing with 25 ° C. water and further cleansing with sulfuric acid, the core substrate 30 is immersed in an electrolytic copper plating solution 12 having the following composition. Thereafter, by using the plating apparatus 10 described above with reference to FIG. 9, an electrolytic plating film 36 is formed on both surfaces and through holes of the copper foil laminate under the following conditions (FIG. 1D).

(Composition of Electrolytic Plating Solution 12>

Sulfuric acid 0.5 mol / L

Copper Sulfate 0.8 mol / L

Iron sulfate 7-hydrate (FeSO ₄ 7H ₂ O) 5 g / L

Leveling agent 50 mg / L

Abrasive 50 mg / L

Fe ^{2 +} : Fe ^{3 +} 1: 2-1: 4

<Electrolytic plating condition>

Current Density 1 A / dm ²

65 minutes

Temperature 22 ± 2 ℃

Here, as described above with reference to FIG. 9, the insulators 20A and 20B using the porous resin are vertically moved along the surface to be plated, and the through-hole 32 is filled with the plating to make the electrolytic copper plating film 36. ) Is formed on the core substrate 30. The through hole 32 is filled with the electrolytic copper plating film 36. During this time, the moving speed of the insulators 20A and 20B is 7 m / min, the size of the insulators 20A and 20B relative to the size of the core substrate is 0.80, and the amount to which the insulators 20A and 20B are pushed is 8 mm. to be.

Thereafter, an etching resist having a predetermined pattern is formed on the electroplating film 36 (Fig. 1E).

The electroplated film 36, the electroless plated film 34, and the copper foils 130A, 130B exposed by the etching resist 38 are removed by etching, and the through-hole conductor 40 and the conductive circuit 42 ) Is formed (FIG. 2A).

) 이 형성된다 (도 2b).Rough surface 40 on the top surface of through-hole conductor 42 and the entire surface of conductive circuit 40.

) Is formed (FIG. 2B).

<Formation of built-up layer>

On both surfaces of the core substrate 30, a resin film (brand name: ABF-45SH manufactured by Ajinomoto Fine-Techno Co., Inc.) for the interlayer resin insulating layer is laminated. Thereafter, the resin film for the interlayer resin insulating layer is cured so that the interlayer resin insulating layer 50 is formed on both surfaces of the core substrate 30 (FIG. 2C).

By using a CO ₂ gas laser, a via-conductor opening 50a having a diameter of 80 μm is formed in the interlayer resin insulating layer 50 (FIG. 2D).

) 이 비아-도전체 개구 (50a) 의 내벽을 포함하는 층간 수지 절연층 (50) 의 표면상에 형성된다 (도 2e).The substrate 30 having the via-conductor opening 50a is immersed in an 80 ° C. solution containing 60 g / L of permanganic acid for 10 minutes and has a rough surface (50

) Is formed on the surface of the interlayer resin insulating layer 50 including the inner wall of the via-conductor opening 50a (FIG. 2E).

Substrate 30 is immersed in a neutralization solution (manufactured by Shipley Company) and then washed with water. In addition, a catalyst nucleus (not shown in the figure) is attached to the surface of the interlaminar resin insulating layer 50 and the inner wall of the via-conductor opening 50a.

The substrate 30 with the attached catalyst was immersed in a commercially available electroless copper plating solution, so as to have a thickness of 0.3-3.0 mu m on the surface of the interlaminar resin insulating layer 50 and on the inner wall of the via-conductor opening 80a. An electroless copper plating film 52 having a thickness is formed (FIG. 3A).

After cleansing with 50 ° C. water for washing, washing with 25 ° C. water and further cleansing with sulfuric acid, the substrate 30 having the interlaminar resin insulating layer 50 is immersed in an electrolytic copper conductive solution 12 having the same composition as above. do. Using the plating apparatus 10 described with reference to FIG. 9, under the above-described conditions, an electrolytic copper plating film 56 is formed on the interlayer resin insulating layer 50 and in the via-conductor opening 50a ( 3b). The via-conductor opening 50a is filled with the electrolytic copper plating film 56.

Here, as described above with reference to FIG. 9, while the insulators 20A and 20B using the porous resin are moved vertically along the surface to be plated, the plating is filled in the opening 50a and has a thickness of 12 μm. An electrolytic copper plating film 56 is also formed on the surface of the interlayer resin insulating layer 50. The moving speed of the insulators 20A and 20B is 7 m / min, the size of the insulators 20A and 20B relative to the size of the core substrate 30 is 0.80, and the amount to which the insulators 20A and 20B are pushed is 8 mm. .

, 60

) 이 상위 층 도전성 회로 (58) 및 채워진 비아 (60) 의 표면상에 형성된다 (도 4a).Thereafter, an etching resist 54 is formed on the electrolytic copper plating film 56 (Fig. 3C). The electrolytic plating film 56 and the electroless plating film 52 exposed by the etching resist 54 are removed by etching. Thereafter, by removing the etching resist 54, an independent upper layer conductive circuit 58 and filled vias 60 are formed (FIG. 3D). Rough Surface (58

, 60

) Is formed on the surface of the upper layer conductive circuit 58 and the filled via 60 (FIG. 4A).

By repeating the above steps described with reference to FIGS. 2B-4A, another upper layer interlayer insulating layer 150, conductive circuit 158 and filled vias 160 are formed, and multilayer wiring board 300 is obtained (FIG. 4b).

A commercially available solder-resist composition 70 (such as SR 7200 manufactured by Hitachi Chemical Co., Ltd) was applied to both surfaces of the multilayer wiring board 300 to be 20 μm thick (FIG. 4C) and dried The treatment is carried out at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes. Thereafter, through exposure and development treatment, an opening 71 for exposing the conductive circuit and the filled vias is formed in the solder-resist composition (FIG. 5A). The solder-resist composition is then cured by subjecting the heat treatment under the conditions of 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, thereby curing the conductive circuit and the filled vias. A solder-resist layer 70 having an opening for exposing is formed on the interlayer resin insulating layer. The conductive circuit exposed through the openings in the solder-resist layer and the top surface of the filled vias serve as pads for mounting electronic components and pins.

Nickel layers, palladium layers and gold layers are formed in this order on the exposed pads through the openings in the solder-resist layer 70. Thereafter, the solder balls are supplied onto the pads and then reflowed. Thus, solder bumps (solder bodies) 76U and 76D are formed on the pads. The multilayer printed wiring board 100 having the solder bumps 76U and 76D is completed (FIG. 6).

<Manufacturing method 2>

In the following, manufacturing steps according to manufacturing method 2 will be described with reference to FIGS. 7A to 7D. As illustrated in FIG. 7B, a plating resist 54 is formed on the intermediate substrate in the state shown in FIG. 3A. This is different from the method 1 described above with reference to FIGS. 3A to 3D in which the electrolytic plating film 56 is formed on the entire surface of the electroless plating film 52.

After cleansing with 50 ° C. water for washing, washing with 25 ° C. water and further cleansing with sulfuric acid, the substrate 30 is immersed in an electrolytic copper plating solution 12 having the same composition described in Method 1. An electrolytic copper plating film 56 is formed on the interlayer resin insulating layer 50 and in the via conductor openings under the same conditions as described above, and the via conductor openings are filled with the electrolytic copper plating film 56 (FIG. 7C). .

Here, as described above with reference to FIG. 9, the insulators 20A and 20B using the porous resin are moved vertically along the surface to be plated, and the via conductor openings are filled with the plating to make the electrolytic copper plating film 56 It is formed on the interlayer resin insulating layer 50 and in the via conductor opening. The via conductor opening is filled with the electrolytic copper plating film 56. The moving speed of the insulators 20A and 20B is 7 m / min, the size of the insulators 20A and 20B relative to the size of the core substrate 30 is 0.80, and the amount to which the insulators 20A and 20B are pushed is 8 mm. .

Plating resist 54 is removed using 5% KOH solution. Thereafter, an independent upper layer conductive circuit 58 and filled vias 60 are formed by removing the electroless plating film 52 not covered by the electrolytic plating film 56 (FIG. 7D). Since the subsequent steps are the same as in the manufacturing method 1, the description is omitted.

<Manufacturing method 3>

Next, manufacturing steps according to manufacturing method 3 will be described with reference to FIGS. 8A to 8F. This method is an example of a method of manufacturing a printed wiring board having an hourglass-shaped through-hole conductor. Here, the hourglass-shaped through-hole conductor includes a first opening taping from the first surface to the second surface of the core substrate 30, and a second opening tapering from the second surface to the first surface. The through-hole conductor formed by filling the through-hole comprised with plating is shown.

The double-sided copper foil laminated board 30C formed by laminating | stacking copper foil 130A, 130B on both surfaces of the core board | substrate 30 is manufactured. The core substrate 30 has a first surface and a second surface opposite to the first surface. Copper foil 130A is formed on the first surface of the core substrate 30, and copper foil 130B is formed on the second surface of the core substrate 30 (FIG. 8A).

CO ₂ laser is applied from the first surface side of the core substrate 30. A first opening 136A penetrating through copper foil 130A and tapering from the first surface of the core substrate 30 to the second surface is formed (FIG. 8B). The tapering from the first surface to the second surface has a diameter of the first opening 136A that gradually decreases from the first surface to the second surface. With respect to the diameter of the first opening 136A, when the first opening 136A is sliced by a plane parallel to the first surface, the distance across the cross section is the diameter if the first opening 136A is a circle, and 1 If the opening is elliptical, it is long axis.

Thereafter, a CO ₂ laser is applied from the second surface side of the core substrate 30. The position to be irradiated by the laser is opposite to the first opening 136A. A second opening 136B is formed penetrating the copper foil 130B and tapering from the second surface of the core substrate 30 to the first surface. By forming the second opening 136B, the first and second openings 136A, 136B are joined inside the core substrate 30, and the through hole 136 composed of the first and second openings 136A, 136B. It is formed in this core substrate 30 (FIG. 8C). The tapering from the second surface to the first surface has a diameter of the second opening 136B that gradually decreases from the second surface to the first surface. With regard to the direct management of the second opening, when the second opening is sliced by a plane parallel to the first surface, the distance across the cross section is the diameter if the second opening is a circle and the long axis if the second opening is an ellipse.

A seed layer 137 composed of a sputtered film is formed on the surface of the copper foils 130A and 130B and on the inner wall of the through hole 136. The seed layer 137 is made of copper. Since the first and second openings 136A, 136B are tapered, the seed layer 137 is easily formed by sputtering. However, seed layer 137 may be formed by electroless plating.

An electrolytic copper plating film 134 was formed on the first and second surfaces of the core substrate 30 using the same plating apparatus 10, plating solution 12, plating method and plating conditions as described in Manufacturing Method 1 do. During this time, the through hole 136 is filled with the electrolytic copper plating film 134 (FIG. 8E). The through-hole 32 in the manufacturing method 1 is substantially linear shape, but the through-hole 136 in the manufacturing method 3 is an hourglass shape. When the through holes are formed in the same core substrate to have the same diameter (diameters on the front and back surfaces of the core substrate), the volume of the hourglass shaped through holes is smaller than the volume of the straight through holes. Due to this difference, the thickness of the electroplated film on the core substrate in the manufacturing method 3 tends to be thinner than the thickness of the electroplated film on the substrate in the manufacturing method 1. As such, a fine conductive circuit can be formed by the manufacturing method 3.

In the same manner as in Manufacturing Method 1, an etching resist is formed on the electrolytic copper plated film 134. Thereafter, the electrolytic plating film 134, the sputtered film 137, and the copper foils 30A, 30B exposed by the etching resist are dissolved and removed. Thus, independent conductive circuit 134A and through-hole conductor 142 are formed (FIG. 8E). Thereafter, a built-up layer may be formed on the core substrate in the same manner as in the manufacturing method 1.

&Lt; Second Embodiment >

The plating apparatus used in the method of manufacturing a printed wiring board according to the second embodiment of the present invention will be described with reference to FIGS. 10 and 11.

11 is a schematic diagram showing a side view of the plating apparatus 210, and FIG. 10 is a schematic diagram showing the structure of the conveyor mechanism located on one side of the plating tank in the plating apparatus 210. FIG. The plating apparatus 210 performs plating on a strip-shaped substrate with respect to the flexible printed wiring board. In this plating apparatus 210, electroplating is performed on one surface of the strip substrate 230A pulled from the reel 298A in which a strip substrate of 180 mm width and 120 m length is wound. Thereafter, the strip-shaped substrate 230A is wound on the reel 298B. The plating apparatus 210 is an insulating cylindrical contact 220 in contact with the surface of the strip substrate 230A to be plated, a bag for preventing the strip substrate 230A from twisting caused by the contact (insulator) 220. A board 228, and an anode 204. At the anode 204, copper balls 206 are received to replenish the copper component in the plating solution. The plating tank 212 is 20 m long in total. Instead of an insulating material for the contact 220, a semiconductor contact may also be used. The contact body in the second embodiment has a function substantially the same as that of the insulators 20A and 20B described in the first embodiment.

The contact 220 is formed of a cylindrical brush made of PVC (polyvinyl chloride) having a height of 200 mm and a diameter of 100 mm. In the contact 220, the tip of the brush is bent in contact with the printed wiring board. The contact body 220 is supported by a support bar 220A made of stainless steel and is rotated by a gear not shown in the figure.

Forming the filled via and the conductive circuit using the plating apparatus 210 will be described with reference to FIGS. 12A to 12E. 12A shows a double-sided copper foil flexible substrate composed of a substrate 230 and copper foil 33U, 33D. A commercially available dry film is laminated on one surface of the substrate 230, and the copper foil 33U is etched from the region where the via conductor opening 37 is to be formed using a known photographic method. Using the copper foil 33U as a mask, the via conductor opening 37 is formed by a carbon dioxide gas laser (FIG. 12B). An electroless plating film 34 is formed on the inner wall of the via conductor opening 37 and the copper foil 33U (FIG. 12C), and the electrolytic plating film 36 uses the plating apparatus 210 shown in FIG. Is formed (FIG. 12D). The plated film 36 is formed while a part of the contact body 220 is in contact with at least a part of the surface of the printed wiring board. The contact body 220 is in contact with the electroless plating film 34 on the printed wiring board at the start of electroplating, and in contact with the electroplating film 36 when the electroplating film 6 is formed.

According to the second embodiment, the plating solution 12 contains copper sulfate, sulfuric acid and iron ions, as in the first embodiment. Since the plating solution 12 contains iron (III) ions, the thickness of the electrolytic plating film 36 formed on the substrate surface was obtained using a plating solution containing no iron (III) ions at a high concentration. Smaller than that. In addition, since the plating film 36 is formed using the contactor 220, the via conductor opening can be filled with the electrolytic plating film 36. As shown in FIG.

Preferably, the size of the contact is greater than the area to be plated on the strip substrate. The amount by which the contact is pushed into the printed wiring board (the amount of tip to be pushed further after the tip of the contact comes into contact with the surface of the printed wiring board) is preferably 1.0-15.0 mm to the surface. If this amount is smaller than 1.0 mm, the result may be the same as that of the plating method without using a contact. If this amount exceeds 15.0 mm, it will be considered difficult to supply iron (III) ions on the substrate surface. Further, the contact tends to enter the via conductor opening and the through-hole conductor opening, so that the concentration of iron (III) ions in the opening is thought to increase. The amount to be pushed is preferably 2-8 mm. This is because variation in the plating film may hardly occur.

As regards the contact, one selected from a flexible brush and a spatula can be preferably used. Flexiblely, the contact member follows the nonuniformity on the substrate and can form a plated film having a uniform thickness on the nonuniform surface.

A resin brush can be used as the contact. In this case, the bristle tip is in contact with the surface to be plated. Here, preferably, the diameter of the bristles is larger than the diameter of the openings because the plating film can be appropriately filled in the openings without the bristle tips entering the openings. Regarding the resin brush, PP, PVC (polyvinyl chloride), PTFE (polytetrafluoroethylene), etc., which have resistance to plating solution, can be used. In addition, resins and rubbers may be used. In addition, with respect to the bristle tips, vinyl chloride woven or nonwoven can also be used.

<Manufacturing method 4>

A method of manufacturing a printed wiring board using the plating apparatus according to the second embodiment (for example, using the subtractive method and the tenting method) will be described with reference to FIGS. 12A to 12E. Hereinafter, this method is called manufacturing method 4.

Laminated strips in which a 9 μm copper foil 33U is laminated on the front side (first surface) of the 25 μm thick polyimide strip substrate 230 and a 12 μm copper foil 33D is laminated on the back side (second surface) The mold substrate 230A is manufactured as a starting material (FIG. 12A). The copper foil on the second surface is covered with a resist. The thickness of the 9 micrometer copper foil 33U on the front surface is adjusted to 7 micrometers by photoetching. Thereafter, black-oxide treatment is performed on the copper foil on the first surface. By irradiating a laser from the first surface side, a via conductor opening 37 penetrating the copper foil 33U and the polyimide strip substrate 30 and reaching the back surface of the copper foil 33D is formed (FIG. 12B). The palladium catalyst is then attached to the surface of the strip substrate 230A (not shown in the figure).

The substrate having the attached catalyst was immersed in an electrolytic plating solution (Thru-Cup) manufactured by C. Uyemura Co., Ltd, and the electroless plating film (seed layer) 34 having a thickness of 1.0 μm was applied to the strip substrate 230A. Is formed on the first surface of Fig. 12C.

After cleansing with 50 ° C water for washing, washing with 25 ° C water and further cleansing with sulfuric acid, strip substrate 230A is immersed in a plating tank containing an electrolytic copper plating solution having the following composition. Using the plating apparatus 210 described above with reference to FIG. 10, an electrolytic plating film 36 is formed on the seed layer 34 under the following conditions (FIG. 12D).

<Composition of Electrolytic Plating Solution>

Sulfuric acid 0.5 mol / L

Copper Sulfate 0.8 mol / L

Iron sulfate 7-hydrate (FeSO ₄ 7H ₂ O) 100 g / L

Leveling agent 50 mg / L

Abrasive 50 mg / L

Fe ^{2 +} : Fe ^{3 +} 1: 2-1: 4

<Electrolytic plating condition>

Current Density 5.0-30 mA / cm ²

10-90 minutes

Temperature 22 ± 2 ℃

Here, the current density is preferably 5.0-30 mA / cm ² , in particular 10 mA / cm ² The above is set. Thereafter, resists having a predetermined pattern are formed on both surfaces of the strip substrate and subjected to etching to form the conductive circuit 42U and the conductive circuit 42D (Fig. 12E). This is the so-called subtractive method or tenting method.

<Manufacturing method 5>

The composition of the electrolytic plating solution in Manufacturing Method 3 is changed to the following composition. The rest is the same as in the preparation method 3.

<Composition of Electrolytic Plating Solution>

Sulfuric acid 0.5 mol / L

Copper Sulfate 0.8 mol / L

Iron sulfate 7-hydrate (FeSO ₄ 7H ₂ O) 50 g / L

Leveling agent 50 mg / L

Abrasive 50 mg / L

Fe ^{2 +} : Fe ^{3 +} 1: 2-1: 4

<Manufacturing method 6>

The composition of the electrolytic plating solution in Manufacturing Method 3 is changed to the following composition. The rest is the same as in the preparation method 3.

<Composition of Electrolytic Plating Solution>

Sulfuric acid 0.5 mol / L

Copper Sulfate 0.8 mol / L

Iron sulfate 7-hydrate (FeSO ₄ 7H ₂ O) 100 g / L

Leveling agent 50 mg / L

Abrasive 50 mg / L

Fe ^{2 +} : Fe ^{3 +} 1: 2-1: 4

Comparing the manufacturing methods 5 and 6, the plated film exposed through the opening tends to be recessed in the manufacturing method 6. This is considered to be because the plating growth inside the opening is slow due to the large amount of iron (III) ions in the manufacturing method 6. When the concentration of iron ions is 1 g / L-10 g / L, the plated film exposed through the opening shows higher flatness characteristics. Therefore, the interlayer resin insulating layer may be easily formed on the plated film. Iron ions in the plating solution are iron (II) ions and iron (III) ions. When the ratio of the concentration of iron (II) ions to the concentration of iron (III) ions in the electrolytic plating solution is in the range of 1: 2-1: 1, the deposition of the plating film on the substrate surface is effectively suppressed. . Both filling the openings and reducing the film thickness of the plated film on the substrate surface tends to be achieved. Preferably, iron sulfate 7-hydrate (FeSO ₄ .7H ₂ O) is added in an amount of 5-100 g relative to 1,000 mL of electrolytic plating solution. If the concentration of iron ions is in the range of 1 g / L-20 g / L, the opening may be filled with plating while the thickness of the plating film on the substrate surface is reduced.

<Manufacturing method 7>

The composition of the electrolytic plating solution in Manufacturing Method 3 is changed to the following composition. The rest is the same as in the preparation method 3.

<Composition of Electrolytic Plating Solution>

Sulfuric acid 0.65 mol / L

Copper Sulfate 0.7 mol / L

Iron sulfate 7-hydrate (FeSO ₄ 7H ₂ O) 50 g / L

Leveling agent 50 mg / L

Abrasive 50 mg / L

Fe ^{2 +} : Fe ^{3 +} 1: 2-1: 4

<Manufacturing method 8>

The composition of the electrolytic plating solution in Manufacturing Method 3 is changed to the following composition. The rest is the same as in the preparation method 3.

<Composition of Electrolytic Plating Solution>

Sulfuric acid 0.35 mol / L

Copper Sulfate 0.9 mol / L

Iron sulfate 7-hydrate (FeSO ₄ 7H ₂ O) 50 g / L

Leveling agent 50 mg / L

Abrasive 50 mg / L

Fe ^{2 +} : Fe ^{3 +} 1: 2-1: 4

In embodiments and examples of the present invention, the insulator is in contact with the surface to be plated, and electroplating is performed while moving the insulator relative to the surface to be plated. On the surface to be plated in contact with the insulator, the growth of the plated film is slowed down. It is believed that iron ions are forcibly supplied by an insulator on the surface to be plated, resulting in a reduction reaction of iron ions on the surface to be plated. Therefore, it is thought that growth of the electroplating film is suppressed. In contrast, in the region where the insulator does not contact, since iron ions diffuse on the surface to be plated due to the concentration gradient, the reduction reaction of the iron ions is less likely to occur on the surface to be plated. Therefore, it is thought that the growth rate of an electroplating film is faster. Thus, the electrolytic plating film grows faster in the via conductor opening and the through-hole conductor opening, but the plating film on the surface to be plated except the opening is suppressed from becoming too thick. That is, the via conductor openings and through-hole conductor openings are securely filled with an electrolytic plating film, and the plating film on the surface (substrate surface) to be plated is compared with the thickness of the electrolytic plating film formed in the openings or the film of the conductive circuit in the prior art. It can be formed relatively thin compared to the thickness. In embodiments and examples of the present invention, since the thin plated film is patterned, a finer conductive circuit can be formed more easily than in the conventional case.

The order and contents of the procedure in the above embodiment may be changed freely without departing from the gist of the present invention. In addition, some steps may be omitted depending on usage requirements. For example, correction may be made based on image rendering data other than vector data.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Accordingly, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

Claims (9)

Forming an opening in the substrate;
Forming a seed layer for electroplating on the inner wall of the opening and the surface of the substrate;
Positioning the substrate with the seed layer in an electrolytic plating solution;
Placing an insulator in the electrolytic plating solution;
Moving the substrate and the insulator relative to each other to form an electroplating film on the substrate and filling the opening with the electroplating film; And
Forming a conductive circuit on the substrate,
Wherein said electrolytic plating solution comprises copper sulfate, sulfuric acid, and iron ions. The method of claim 1,
Wherein said source of iron ions is iron (II) sulfate. The method of claim 1,
The iron ions include iron (II) ions and iron (III) ions, and the ratio of the iron (II) ions to the iron (III) ions in the electrolytic plating solution is 1: 2 to 1: 1. 4 person, method of manufacturing a printed wiring board. The method of claim 2,
The iron sulfate is FeSO ₄ · 7H ₂ O contained in a concentration of 5-100 g / L, a method for producing a printed wiring board. The method of claim 1,
And the insulator comprises a material selected from the group consisting of long fibers, porous resins, fibrous resins, and rubbers. The method of claim 1,
Wherein the insulator comprises a porous ceramic or a porous resin. The method of claim 1,
And the insulator comprises a brush having bristles comprising a resin. The method of claim 1,
And the insulator comprises resin fibers. The method of claim 1,
The iron ions are included in a concentration of 1 g / L-20 g / L, a method for manufacturing a printed wiring board.

Images