CN1059982C - Method for automatically welding package of ball array integrated circuit by coil belt - Google Patents
Method for automatically welding package of ball array integrated circuit by coil belt Download PDFInfo
- Publication number
- CN1059982C CN1059982C CN97117545A CN97117545A CN1059982C CN 1059982 C CN1059982 C CN 1059982C CN 97117545 A CN97117545 A CN 97117545A CN 97117545 A CN97117545 A CN 97117545A CN 1059982 C CN1059982 C CN 1059982C
- Authority
- CN
- China
- Prior art keywords
- dry type
- base material
- type film
- integrated circuit
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The present invention discloses an automatic welding bead array type integrated circuit packaging method. The surface layer of a polyimide film with copper on a single surface is defined to form a first dry film, copper/nickel/gold /nickel (or nickel /gold and copper/nickel) are electroplated, the first dry film is removed, the polyimide film is etched to form pores, the pores are electrolytically electroplated to form convex contact points, the thin copper is etched, the nickel is peeled, and chip installing holes and peripheral through holes are formed by laser drill. Therefore, the external contact points have fine effect, a chip is welded in an individual spot welding mode, and the packaging area can be shortened.
Description
The present invention relates to a kind of method of integrated circuit dimensional packaged circuit board, especially make the method for integrated circuit dimensional packaged circuit board.
The method for making of TAB-BGA type integrated circuit dimensional packaged circuit board now, roughly shown in Fig. 4 A～I, be the typical processing procedure of 3M company, at first be to form thin (cathode) sputtering copper 91 by (cathode) sputtering mode (PVD or CVD) in polyimide film 90 (POLYIMIDE) the base material top of Fig. 4 A, to form a polyimide film that contains thin copper layer, be then shown in Fig. 4 B, the surface covers a thin electro-coppering 92 with plating mode, afterwards, shown in Fig. 4 C, in the top, the bottom surface is located the pressing dry type film and is passed through exposure and step of developing, and on the top, the bottom surface forms the block dry type film 93 of several tool breach, secondly, then be shown in Fig. 4 D, carry out the step of electro-coppering in tip position, to be formed on the thicker electro-coppering 94 between each dry type film 93, secondly, then be shown in Fig. 4 E, polyimide film 90 is carried out etched step, and form for the follow-up tapered hole 97 of implanting the tin ball, then, be shown in Fig. 4 F, carry out the step of metallide nickel and metallide chromium, make the thicker electro-coppering 94 of upper surface and tapered hole 97 places of bottom form metallide nickel and electrodeposited chromium layers 96, afterwards, be to remove the dry type film 93 of top bottom and form pattern as Fig. 4 G, and through the step of etched copper, electro-coppering 92 and 91 etchings of (cathode) sputtering copper to the inner interlayer position of Fig. 4 G, and change kenel into as Fig. 4 H, at last, it then is the step of each tapered hole 97 position of bottom being implanted the tin ball, and form for external tin ball 98 in the region of interest shown in Fig. 4 I, as for metallide nickel and electrodeposited chromium layers 96 one places in the evagination of surperficial appropriate location is for adhesion chip 40, and simultaneously with chip 40 each pin by routing (interconnection) machine (BONDER) with metal wire 41 cross-over connections to the relevant position place.But the method for making of above-mentioned existing TAB-BGA integrated circuit dimensional packaged circuit board has following shortcoming: at first, polyimide film 90 tops are to form thin (cathode) sputtering copper 91 in the employed (cathode) sputtering of manufacture of semiconductor (SPUTTERING) mode, though forming Copper Foil by the (cathode) sputtering mode can reach evenly and the thickness that approaches, but because this (cathode) sputtering processing procedure is not only comparatively expensive, and be to carry out large-area (cathode) sputtering operation on this polyimide film surface, so it is high that cost more belongs to, and can't meet the requirement of economy.Secondly, its external contact is to use plants tin ball mode and reaches, for tin ball size certain limitation is arranged, and the corresponding tapered hole of implanting for the tin ball also must design suitable admissible error, therefore cause the size of external contact and spacing distance significantly to reduce, cause outer shortcoming that can't granular, and the mode of implanting the tin ball is to make the tin ball roll on circuit board and fall into each tapered hole, and then form with the melts combine of tapered hole inside by high temperature, this measure more has the phenomenon of setting accuracy deficiency, that is can't guarantee that each tin ball can all aim at, so, then have no way of reaching if desire to reach more high precision and littler contact.Moreover, because it is to form metal for the contact that connects chip, carry out wire jumper (jumper) and be connected so must use gold thread welding manner (Au Wire Bonding) with between the chip contact, the packaged type that this kind connects chip by wire jumper (jumper) also has and takies board area, cause the size of whole dimensional packaged circuit board bigger, can't meet the shortcoming that high density requires.
The object of the present invention is to provide a kind of each external contact precision positioning that makes, form more tiny external contact, and can suitably dwindle the method for the manufacturing integrated circuit dimensional packaged circuit board of dimensional packaged circuit board area.
The object of the present invention is achieved like this, and a kind of method of making the integrated circuit dimensional packaged circuit board is characterized in that it comprises the following steps: to take the polyimide film that contains the thin copper of single face is base material; The base material upper surface is carried out pressing, exposure and the development of first dry type film; The place carries out multilayer plating layers such as electro-coppering, electronickelling, electrogilding and electronickelling in regular turn at the unlapped upper surface of first dry type film; Remove first dry type film; Laser-induced thermal etching is carried out at polyimide film position to base material, and utilization approaches the control of stopping of copper and laser energy, to form non-through hole figure; At base material upper surface pressing second dry type film, with protection upper surface electrodeposited coating; Implement metallide and form the metallide contact that fills up each hole and omit evagination at each hole of polyimide film; Remove second dry type film; The etching position is being the thin copper that exposes between each multilayer plating layer, and adjacent electrodeposited coating is spaced from each other, and an etching removal electroless nickel layer at the multilayer plating laminar surface, and the electrogilding layer is exposed; And, laser drill is carried out at position central to base material and that need to form perforation, chip installing hole and peripheral laser perforation to form base material central authorities respectively form by the formed contact cantilever of multilayer plating layer so that chip installing hole position is peripheral, can supply the solder bond chip.
Purpose of the present invention can also realize by following method, and a kind of method of making the integrated circuit dimensional packaged circuit board is characterized in that comprising the following steps: to take the polyimide film that contains the thin copper of single face is base material; The base material upper surface is carried out pressing, exposure and the development of first dry type film; Carry out electronickelling, and the double-deck electrodeposited coating of the formation of electrogilding in regular turn at the unlapped upper surface of first dry type film place; Remove first dry type film; Laser-induced thermal etching is carried out at polyimide film position to base material, and utilization approaches under the control of stopping of copper and laser energy, to form non-through hole figure; At base material upper surface pressing second dry type film, with protection upper surface electrodeposited coating; Implement metallide and form the metallide contact that fills up each hole and omit evagination at each hole of polyimide film; Remove second dry type film; The etching position is being the thin copper that exposes between each multilayer plating layer, and adjacent electrodeposited coating is spaced from each other; And, laser drill is carried out at position central to base material and that need to form perforation, with chip installing hole and the peripheral laser perforation that forms base material central authorities respectively,, can supply the solder bond chip so that periphery, chip installing hole position is to form by the formed contact cantilever of multilayer plating layer.
Purpose of the present invention can also realize by following method, and a kind of method of making the integrated circuit dimensional packaged circuit board is characterized in that comprising the following steps: to take the polyimide film that contains the thin copper of single face is base material; The base material upper surface is carried out pressing, exposure and the development of first dry type film; Carry out electro-coppering and electronickelling in regular turn and form double-deck electrodeposited coating at the upper surface place that is not covered by first dry type film; Remove first dry type film; Dry type film pressing, exposure and step of developing are carried out in polyimide film position to base material, form most non-through hole figures with the etching polyimide film; At base material upper surface pressing second dry type film, with protection upper surface electrodeposited coating; Implement metallide and form the metallide contact that fills up each hole and omit evagination at each hole of polyimide film; Remove second dry type film; Implement pressing, exposure and the development of the 3rd dry type film on upper and lower surface, and only form breach for the relevant position that chip is installed at upper surface; This gap position is electroplated the gold-plated salient point of formation; Remove the 3rd dry type film; The etching position is being the thin copper that exposes between each double-deck electrodeposited coating, and adjacent electrodeposited coating is spaced from each other; And, to base material central authorities and need to form the position that connects and carry out laser drill, with chip installing hole and the peripheral laser perforation that forms base material central authorities respectively, so that the electrodeposited coating of periphery, chip installing hole position top be to should there being gold-plated salient point, can be in conjunction with chip.
In the FEOL of various embodiments of the present invention, owing to be that the Polyimide film of directly taking pressing in advance or being bonded with thin copper is as base material, it is cheap that the cost of base material obviously carries out the step of the thin copper of (cathode) sputtering than aforementioned conventional mode, so the advantage that reduces cost is arranged, and form in the step of hole 12 and formation metallide contact 17 by polyimide film 10 being carried out laser-induced thermal etching or chemical etching, promptly make each contact can aim at (SELF-ALIGN) automatically in each hole 12, and unlikely generation skew or undue error, so pinpoint advantage is provided, and can make the spacing phase shape between each plating contact 17 be controlled at quite narrow degree (20 Mill), the characteristic that more can meet trickle contact, in addition, N figure for Fig. 1, the chip installing hole 22 positions formed cantilevered construction of formed multilayer plating layer that supplies joint chip 40 places of the N figure of Fig. 2 or the O of Fig. 3 scheme the structure of formed gold-plated salient point 20, form especially and a kind ofly can be directly be followed chip 40 by single-point welding (SINGLEPOINT BOND) mode, need not to link by jumper connection gold thread mode, this measure, also make TAB-BGA dimensional packaged circuit board overall dimensions dwindle, so really be one to have more the densification effect and external contact is more become accurately and tiny method for making than traditional TAB-BGA method for making.
The present invention is further illustrated below in conjunction with accompanying drawing.
Fig. 1 is a first embodiment of the present invention method for making generalized section.
Fig. 2 is a second embodiment of the present invention method for making generalized section.
Fig. 3 is a third embodiment of the present invention method for making generalized section.
Fig. 4 is the generalized section of traditional TAB-BGA processing procedure.
The present invention has three kinds of different embodiment; and only the material of the electrodeposited coating of each processing procedure is different and cause processing procedure slightly to change therebetween; below promptly illustrate with regard to various embodiments of the present invention successively; at first shown in A～N figure of Fig. 1; in the A of Fig. 1 figure; the present invention directly uses pressing or is bonded with single face to approach the polyimide film 10 of copper 11 as base material of the present invention; and need not must spatter copper-plated step to additional cathode on the polyimides film base material earlier as conventional process; carry out operation complexity and the too high problem of base material cost that (cathode) sputtering is derived so can exempt thin copper metal needs; and in the B of Fig. 1 figure; be to carry out pressing first dry type film 13 in thin copper 11 tops and expose/step of developing; the pattern that is first dry type film 13 of most bulks with formation; be then shown in the C figure of Fig. 1; electroplate in regular turn and form electro-coppering 141; electronickelling 142; multiple field electrodeposited coatings such as electrogilding 143 and electronickelling 144; after removing aforementioned first dry type film 13; promptly shown in the D figure of Fig. 1; thereafter; be shown in the E figure of Fig. 1; by the laser-induced thermal etching mode etching is carried out in polyimide film 10 bottoms; and utilize this thin copper 11 as backstop layer and the control by laser energy; make polyimide film 10 etchings form most holes 12 that do not run through (these holes are the contacts that form downward extension for follow-up metallide); be then shown in the F figure of Fig. 1; to upper surface pressing second dry type film 16 so that preceding rheme protected at each figure of upper surface; afterwards; carry out carrying out the step (nickel plating or copper facing) of metallide again as each hole 12 position of the G figure of Fig. 1 to polyimide film 10; and fill up at each hole place and the outer end is the metallide contact 17 (forming the external contact of this dimensional packaged circuit board) of evagination pattern; then; it is second dry type film 16 (as the H figure of Fig. 1) of removing the surface that is incumbent on; afterwards; be I figure as Fig. 1; shown in the J figure of Fig. 1; in regular turn the bottom surface is covered a diaphragm 18; carry out 19 pressings of the 3rd dry type film again; exposure and step of developing; then in the step of the K of Fig. 1 figure; remove the position at the electronickelling 144 at electrodeposited coating top and the thin copper 11 between each electrodeposited coating; and carry out as aforementioned the 3rd dry type film 19 of removal of the L figure of Fig. 1 and the step of diaphragm 18; at last; then be shown in the M figure of Fig. 1; step to middle position and other positions enforcement laser drill; to form chip installing hole 22 and the laser perforation 21 of position in central authorities and peripheral position; so far promptly finish the processing procedure of dimensional packaged circuit board; and the mode that chip is installed; be shown in the N figure of Fig. 1; whole dimensional packaged circuit board is spun upside down; and since the position roughly form as the cantilever at the multilayer plating layer of chip installing hole 22 position sides; and the position, top layer that the N of Fig. 1 schemes the electrodeposited coating of lower position is the material of electrogilding 143; therefore can be directly through the single spot welding connection technology, directly in conjunction with chip 40.
And another embodiment of the present invention is shown in A～N figure as Fig. 2, difference place therebetween only is to electroplate in regular turn to form electronickelling 145 and 143 liang of prong materials of electrogilding at the material of the electrodeposited coating of the C of Fig. 2 figure only, and the thin copper 11 that only needs etching to remove between each electrodeposited coating in the K of Fig. 2 figure gets final product, all the other are all identical, and above-mentioned two kinds of processing procedures all can reach identical effect.
And the third embodiment of the present invention is shown in A～O figure as Fig. 3, the difference place of itself and aforementioned first and second embodiment mainly also is aspect the material of electrodeposited coating, that is in the C of Fig. 3 figure the double layer material that plating formation one electro-coppering 14 and an electronickelling 15 are constituted, and be the material of electronickelling 15 in view of the top layer, then in the pressing of enforcement the 3rd dry type film of the J of Fig. 3 figure, in exposure and the step of developing, be to be formed with the 3rd upper strata dry type film 191 and the 3rd lower floor's dry type film 192 that covers upper strata and lower floor position simultaneously, and be formed with breach 193 at the 3rd upper strata dry type film 191 places, make it can be in the step of the K of Fig. 3 figure, electroplate the gold-plated salient point 20 of formation corresponding to breach 193 positions, after the step of the removal dry type film of the L of Fig. 3 figure, promptly be formed with gold-plated salient point 20 to upper process in electronickelling 15 surfaces of the nearly middle position of this drawing, so can be shown in the O figure of Fig. 3, reach for chip 40 each contact place and carry out the single-point solder bond, in addition, the step that forms holes 12 in the etching polyimide film 10 of the E of Fig. 3 figure is changed into and is adopted the chemical etching mode to carry out.
And its detailed recipe step aspect; among the A figure as Fig. 3; the present invention directly uses pressing or is bonded with single face to approach the polyimide film 10 of copper 11 as base material of the present invention; and need not must spatter copper-plated step to additional cathode on the polyimides film base material earlier as conventional process; carry out operation complexity and the too high problem of base material cost that (cathode) sputtering is derived so can exempt thin copper metal needs; and in the B of Fig. 3 figure; be to carry out pressing first dry type film 13 in thin copper 11 tops and expose/step of developing; the pattern that is most block first dry type films 13 with formation; be then shown in the C figure of Fig. 3; electroplate in regular turn and form a thicker electro-coppering 14 and the two-layer electrodeposited coating of electronickelling 142; and the height of this electrodeposited coating height with first dry type film 13 approximately is suitable; and after removing aforementioned first dry type film 13; promptly shown in the D figure of Fig. 3; thereafter; be shown in the E figure of Fig. 3; by dry type film definition and etching mode chemical etching is carried out in polyimide film 10 bottoms; make polyimide film 10 etchings form most holes 12 that do not run through (these holes are the contacts that form downward extension for follow-up metallide); be then shown in the F figure of Fig. 3 to upper surface pressing second dry type film 16 so that preceding rheme protected at each figure of upper surface; afterwards; carry out carrying out the step (nickel plating or copper facing) of metallide again as each hole 12 position of the G figure of Fig. 3 to polyimide film 10; and fill up at each hole place and the outer end is the metallide contact 17 (forming the external contact of this dimensional packaged circuit board) of evagination pattern; then; it is second dry type film 16 (as the H figure of Fig. 3) of removing the surface that is incumbent on; afterwards; be I figure as Fig. 3; shown in the J figure; in regular turn the bottom surface being covered a diaphragm 18 reaches in upper and lower surface pressing the 3rd simultaneously; lower floor's dry type film 191; 192; through exposure/step of developing; what then only make the 3rd upper strata dry type film 191 is to form breach 193 near centre; then in the K of Fig. 3 figure; the step that goldleaf is electroplated at breach 193 places; and form gold-plated salient point 20 at this gap position; thereafter; by peeling off together on the 3rd; lower floor's dry type film 191; after the step of 192 (as the L figure of Fig. 3); promptly carry out shown in the M figure of Fig. 3; the thin copper 11 of removal between each electrodeposited coating; so that each adjacent electro-coppering 14 of upper surface is spaced from each other; and shown in the N figure of Fig. 3; step to middle position and other positions enforcement laser drill; to form the position behind the chip installing hole 22 and laser perforation 21 of central authorities and peripheral position; so far promptly finish the processing procedure of dimensional packaged circuit board; and the mode that chip is installed; be shown in the O figure of Fig. 3; gold-plated salient point 20 places that are both sides above corresponding to chip installing hole 22 are directly through the single spot welding connection technology, and welding chip 40 thereon.
Claims (10)
1. a method of making the integrated circuit dimensional packaged circuit board is characterized in that comprising the following steps:
Taking the polyimide film that contains the thin copper of single face is base material;
The base material upper surface is carried out pressing, exposure and the development of first dry type film;
The place carries out multilayer platings such as electro-coppering, electronickelling, electrogilding and electronickelling in regular turn at the unlapped upper surface of first dry type film;
Remove first dry type film;
Laser-induced thermal etching is carried out at polyimide film position to base material, and utilization approaches the control of stopping of copper and laser energy, to form non-through hole figure;
At base material upper surface pressing second dry type film, with protection upper surface electrodeposited coating;
Implement metallide and form the metallide contact that fills up each hole and omit evagination at each hole of polyimide film;
Remove second dry type film;
The etching position is being the thin copper that exposes between each multilayer plating layer, and adjacent electrodeposited coating is spaced from each other, and an etching removal electroless nickel layer at the multilayer plating laminar surface, and the electrogilding layer is exposed; And
Laser drill is carried out at position central to base material and that need to form perforation, with chip installing hole and the peripheral laser perforation that forms base material central authorities respectively, form by the formed contact cantilever of multilayer plating layer so that chip installing hole position is peripheral, can supply the solder bond chip.
2. the method for manufacturing integrated circuit dimensional packaged circuit board according to claim 1 is characterized in that: should be with single-point welding manner and chips incorporate by the formed contact cantilever of multilayer plating layer.
3. the method for manufacturing integrated circuit dimensional packaged circuit board according to claim 1 is characterized in that: this metallide contact is to constitute with nickel or copper product.
4. a method of making the integrated circuit dimensional packaged circuit board is characterized in that comprising the following steps:
Taking the polyimide film that contains the thin copper of single face is base material;
The base material upper surface is carried out pressing, exposure and the development of first dry type film;
Carry out electronickelling, and the double-deck electrodeposited coating of the formation of electrogilding in regular turn at the unlapped upper surface of first dry type film place;
Remove first dry type film;
Laser-induced thermal etching is carried out at polyimide film position to base material, and utilization approaches under the control of stopping of copper and laser energy, to form non-through hole figure;
At base material upper surface pressing second dry type film, with protection upper surface electrodeposited coating;
Implement metallide and form the metallide contact that fills up each hole and omit evagination at each hole of polyimide film;
Remove second dry type film;
The etching position is being the thin copper that exposes between each multilayer plating layer, and adjacent electrodeposited coating is spaced from each other; And
Laser drill is carried out at position central to base material and that need to form perforation, with chip installing hole and the peripheral laser perforation that forms base material central authorities respectively, so that periphery, chip installing hole position is to form by the formed contact cantilever of multilayer plating layer, can supply the solder bond chip.
5. the method for manufacturing integrated circuit dimensional packaged circuit board according to claim 4 is characterized in that: should be with single-point welding manner and chips incorporate by the formed contact cantilever of multilayer plating layer wherein.
6. the method for manufacturing integrated circuit dimensional packaged circuit board according to claim 4 is characterized in that: wherein this metallide contact is to constitute with nickel or copper product.
7. a method of making the integrated circuit dimensional packaged circuit board is characterized in that comprising the following steps:
Taking the polyimide film that contains the thin copper of single face is base material;
The base material upper surface is carried out pressing, exposure and the development of first dry type film;
Carry out electro-coppering and electronickelling in regular turn and form double-deck electrodeposited coating at the upper surface place that is not covered by first dry type film;
Remove first dry type film;
Dry type film pressing, exposure and development are carried out in polyimide film position to base material, form most non-through hole figures with the etching polyimide film;
At base material upper surface pressing second dry type film, with protection upper surface electrodeposited coating;
Implement metallide and form the metallide contact that fills up each hole and omit evagination at each hole of polyimide film;
Remove second dry type film;
Implement pressing, exposure and the development of the 3rd dry type film on upper and lower surface, and only form breach for the relevant position that chip is installed at upper surface;
This gap position is electroplated the gold-plated salient point of formation;
Remove the 3rd dry type film;
The etching position is being the thin copper that exposes between each double-deck electrodeposited coating, and adjacent electrodeposited coating is spaced from each other; And
To base material central authorities and need to form the position that connects and carry out laser drill, with chip installing hole and the peripheral laser perforation that forms base material central authorities respectively, so that the electrodeposited coating of periphery, chip installing hole position top is to gold-plated salient point should be arranged, can be in conjunction with chip.
8. the method for manufacturing integrated circuit dimensional packaged circuit board according to claim 7 is characterized in that: this electro-coppering is the kenel of a higher caliper.
9. the method for manufacturing integrated circuit dimensional packaged circuit board according to claim 7 is characterized in that: this each gold-plated salient point is with single-point welding manner and chips incorporate.
10. the method for manufacturing integrated circuit dimensional packaged circuit board according to claim 7 is characterized in that: this metallide contact is to constitute with nickel or copper product.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97117545A CN1059982C (en) | 1997-08-28 | 1997-08-28 | Method for automatically welding package of ball array integrated circuit by coil belt |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97117545A CN1059982C (en) | 1997-08-28 | 1997-08-28 | Method for automatically welding package of ball array integrated circuit by coil belt |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1210363A CN1210363A (en) | 1999-03-10 |
| CN1059982C true CN1059982C (en) | 2000-12-27 |
Family
ID=5174491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97117545A Expired - Fee Related CN1059982C (en) | 1997-08-28 | 1997-08-28 | Method for automatically welding package of ball array integrated circuit by coil belt |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1059982C (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433954C (en) * | 2004-12-27 | 2008-11-12 | 淳华科技(昆山)有限公司 | Technological process for selective plating copper on through holes of flexible multiple layered printing circuit board |
| CN100392852C (en) * | 2006-04-12 | 2008-06-04 | 江苏长电科技股份有限公司 | Electronic component plane button ultra-thin packed substrate and making method thereof |
| CN100392851C (en) * | 2006-04-12 | 2008-06-04 | 江苏长电科技股份有限公司 | Semiconductor component plane button type ultra-thin packed substrate and making method thereof |
| US20110056838A1 (en) * | 2009-09-04 | 2011-03-10 | Ibiden, Co., Ltd. | Method of manufacturing printed wiring board |
| CN102281721B (en) * | 2011-05-20 | 2013-01-09 | 深圳市崇达电路技术股份有限公司 | Manufacture method of printed circuit board with surface-pressure covering film |
| CN102723282B (en) * | 2012-06-09 | 2013-10-09 | 江苏长电科技股份有限公司 | Etching-first and packaging-later manufacturing method for chip formal double-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit |
| CN102723284B (en) * | 2012-06-09 | 2014-02-26 | 江苏长电科技股份有限公司 | Method for manufacturing front-mounted three-dimensional line on single side of chip by using first etching and later packaging and packaging structure of three-dimensional line |
| CN103582323B (en) * | 2012-07-20 | 2017-04-26 | 华为技术有限公司 | Method for making circuit pattern on multilayer PCB |
| CN103957668B (en) * | 2014-05-06 | 2016-10-05 | 东莞生益电子有限公司 | The manufacture method of circuit board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0559384A2 (en) * | 1992-03-04 | 1993-09-08 | AT&T Corp. | Devices with tape automated bonding |
-
1997
- 1997-08-28 CN CN97117545A patent/CN1059982C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0559384A2 (en) * | 1992-03-04 | 1993-09-08 | AT&T Corp. | Devices with tape automated bonding |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1210363A (en) | 1999-03-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100279036B1 (en) | Method of forming raised metallic contacts on electrical circuits for permanent bonding | |
| KR100346630B1 (en) | Lead frame and manufacturing method | |
| TWI607531B (en) | Package-on-package semiconductor assembly having bottom device confined by dielectric recess | |
| US6753208B1 (en) | Wafer scale method of packaging integrated circuit die | |
| CN101887874B (en) | Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package | |
| CA1259425A (en) | Balltape structure for tape automated bonding, multilayer packaging, universal chip interconnection and energy beam processes for manufacturing balltape | |
| US20050173788A1 (en) | Semiconductor package having wire bonded die and multi layer metal bumps | |
| CN100521124C (en) | Carrier and its making method | |
| CN101409238A (en) | Method for preparing seedless layer package substrate | |
| TW201711149A (en) | Interconnect substrate having cavity for stackable semiconductor assembly, manufacturing method thereof and vertically stacked semiconductor assembly using the same | |
| CN1059982C (en) | Method for automatically welding package of ball array integrated circuit by coil belt | |
| US6465886B1 (en) | Semiconductor device having circuit pattern and lands thereon | |
| US5843806A (en) | Methods for packaging tab-BGA integrated circuits | |
| CN1971865A (en) | Chip electric connection structure and its manufacturing method | |
| CN109003959B (en) | A kind of high thermal conductivity encapsulating structure that bonding wire is preforming and its manufacturing method | |
| KR100339252B1 (en) | Semiconductor device with solder bumps and manufacturing method thereof | |
| CN1980538A (en) | Method for forming circuit-board electric connection end | |
| KR100431307B1 (en) | Capacitor embedded chip size package and manufacturing method thereof | |
| CN100442465C (en) | Producing process for chip packaging body without kernel dielectric layer | |
| CN1068710C (en) | Method for automatically welding package of ball array integrated circuit by coil belt | |
| CN1050930C (en) | Method for automatically welding package of ball array integrated circuit by coil belt | |
| JP2000216185A (en) | Semiconductor wafer fitted with columnar electrode and its manufacture, and semiconductor device and its manufacture | |
| CN1072397C (en) | Winding automatic-welding spherical-array type integrated circuit packing method | |
| CN1088968C (en) | Method for manufacturing grain dimensional packaged circuit board | |
| CN101982876A (en) | Semiconductor packaging part and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |