CN1088968C

CN1088968C - Method for manufacturing grain dimensional packaged circuit board

Info

Publication number: CN1088968C
Application number: CN97119238A
Authority: CN
Inventors: 蔡维人
Original assignee: HUATONG COMPUTER CO Ltd
Current assignee: HUATONG COMPUTER CO Ltd
Priority date: 1997-09-26
Filing date: 1997-09-26
Publication date: 2002-08-07
Anticipated expiration: 2017-09-26
Also published as: CN1213265A

Abstract

The present invention relates to a method for manufacturing grain dimensional packaged circuit boards. A thick copper sheet is used as a base material; the steps of the lamination, the exposure and the development of the upper surface for the first film drying are carried out; a notch of the dry film is electroplated to form a three-layer electroplating circuit of electroplating gold/electroplating copper/electroplating gold; then, a polyimide film is covered on the surface for protection; secondly, the second film drying and the etching operation are carried out on the bottom surface of a copper base material for etching and removing the copper base material; finally, the polyimide film on the top surface is drilled by laser to form a hole embedding hole and a contraposition hole. In a whole manufacturing process, only two times of film drying operation are needed for achieving the efficacy of simplifying operation processes.

Description

The chip size packages method of manufacturing circuit board

The present invention relates to a kind of chip size packages method of manufacturing circuit board.

Integrated circuit encapsulation is now developing towards compact day by day trend, the stretch out encapsulation kenel of pin of traditional type, because package area is big, do not meet highdensity requirement, therefore develop the encapsulation kenel of utilization tin ball after as the BGA of pin, though this measure has the advantage that reduces package area, so its area size is still greater than the wafer actual size.And then research and develop out chip size packages (CSP) again, the area size of this encapsulation approximates the chip size size, because this packaged type is the integrated circuit encapsulation that belongs to the most small-sized, so industry is all towards the research and development of CSP aspect.Shown in Fig. 2 A～H, be the manufacture method of the CSP dimensional packaged circuit board of company of Sony (SONY).Shown in Fig. 2 A, the Copper Foil 60 of taking thickness and be 6 Mills (mil) is as base material, thereon through the pressing of first dry film, exposure and step of developing (figure does not show), and do not electroplated formation one thin nickel 61 (2 micron thickness) and a thin copper 62 (2 micron thickness) in regular turn by the upper surface place of dry film pattern covers, because this drawing only represents to be formed with the position of thin nickel and thin copper, so do not demonstrate dry film, and after removing first dry film, promptly carry out shown in Fig. 2 B, pressing by second dry film, exposure and step of developing, again electroplating surface is formed an electro-coppering 63, after removing second dry film, be shown in Fig. 2 C, carry out the pressing of the 3rd dry film, exposure and step of developing, and two side position etchings are formed the registration holes 64 of up/down perforation, subsequently, shown in Fig. 2 D, cover polyimide film 65, again by the relevant operation of the 4th dry film, and to polyimide film 65 etchings, has the pattern of most breach 651 and form, then, for shown in Fig. 2 E, again by the 5th dry film operation, each breach 651 positions of aforementioned polyimide film 65 are electroplated the electronickelling 652 of about 4 Mills of formation thickness and formed electrogilding 653 in its surperficial re-plating, form the external contact as the similar tin ball according to this, other is with the operation of the 6th dry film, Copper Foil 60 to Fig. 2 F lower position carries out etched step, before be formed at the thin nickel 61 of Copper Foil 60 tops as etching stopping layer (ETCH STOP) and utilize, and make Copper Foil 60 remove (etched thickness is 6 Mills) fully, and then peel off this thin nickel 61 and thin copper 62 successively, and only the bottom surface stays the electro-coppering 63 with circuit pattern, and in the step of Fig. 2 G figure, step by a covering sputtering mask, in the step of implementing the Electroplating Aluminum material, and make, the lower surface place forms sputtering aluminum 661,662, so promptly finish the manufacturing of CSP circuit board, and when desiring in conjunction with wafer or chip, then shown in Fig. 2 H, only need to carry out spot welding at bottom surface adhesion chip 68 and each the contact place and the circuit board corresponding site that give chip 68, and the position cut off in the registration holes 64 of this peripheral position of Fig. 2 G, promptly form the integrated circuit of CSP encapsulation pattern.By the method for making of described existing CSP circuit board, it has the big shortcoming of dry film use amount, that is in its whole processing procedure, needs six road dry film processing procedures to reach altogether, and this measure promptly causes processing procedure particularly complicated and consuming time, so necessity of being improved is arranged.

Thereby main purpose of the present invention is to provide a kind of processing procedure of simplifying promptly to reduce the chip size packages method of manufacturing circuit board that process complexity is increased work efficiency.

The object of the present invention is achieved like this, and a kind of chip size packages method of manufacturing circuit board is characterized in that comprising the following steps: to take Copper Foil as base material; Substrate surface is carried out pressing, exposure and the development of first dry film, and utilize the dry film that develops to define the line pattern breach; The line pattern breach is carried out plating mode insert the multilayer plating layer; Remove first dry film; To upper surface pressing polyimide film with as the protection; Implement pressing, exposure and the development of second dry film, and only base material is carried out an etching removal and an etching formation registration holes in both sides; And, the polyimide film on surface is carried out laser-induced thermal etching, so that multilayer plating layer part exposed or formed pass through openings.Form a kind of chip size packages circuit board that can adhere in the bottom and connect semiconductor chip by spot welding or gold thread thus.

Owing to adopted above-mentioned technical solution, from processing procedure of the present invention, it only needs twice dry film step, needs six road dry films to compare with aforementioned existing CSP processing procedure, and the present invention has simplified the processing procedure of CSP circuit board significantly, has improved operating efficiency.

Further specify specific structural features of the present invention and purpose below in conjunction with accompanying drawing.

Figure 1A～H is a method for making generalized section of the present invention.

Fig. 2 A～H figure is the method for making generalized section of existing CSP circuit board.

The present invention can make dry film job step be reduced to only to need two road dry films; shown in Figure 1A～H; in the step of Figure 1A; at first be take thickness about the Copper Foil 10 of 6 Mills as base material; then; shown in Figure 1B; implement the pressing of first dry film 11; exposure and step of developing; the dry film 11 that has pattern with formation; and between each block dry film 11, be formed with the pattern of breach 111; then; sentence plating mode in aforementioned each breach 111 and insert formation one electrogilding 12 in regular turn; the three-layer type electrodeposited coating that one electro-coppering 13 and an electrogilding 14 are formed; and after removing aforementioned first dry film 11; promptly form the plated pattern loop that separates and be the evagination pattern each other as Fig. 1 C; and in Fig. 1 D; the upper surface place is carried out pressing polyimide film 15 as protection; be then shown in Fig. 1 E; pressing by second dry film 16; exposure and step of developing; and only form the second block dry film 16 at dual-side place, the bottom surface of this Copper Foil 10; and with this second dry film 16 as shade; carry out shown in Fig. 1 F, Copper Foil 10 being carried out the step of etching removal; in the step of this etching Copper Foil 10; then utilize this original position formed electrogilding 12 above Copper Foil 10 to reach with polyimide film 15 as etching stopping layer (ETCH STOP); the selectivity of utilization erosion copper solution; so that Copper Foil 10 complete etchings are removed; and only stay up layers of material of position; and in the step of Fig. 1 G; it is utilization laser drill mode; the polyimide film 15 on top layer is carried out etching form the position in the registration holes 17 of both sides and make the appropriate location of aforementioned multilayer plating layer be the state of exposing (the suitable control by laser energy is reached); so far; promptly finish the basic appearance of CSP circuit board of the present invention; and the CSP circuit board that this makes is in subsequent step; also can give downstream producer and carry out step shown in Fig. 1 H; adhered in the bottom surface; and form by single-point welding (singlepoint bond) and with chip 18 and to electrically connect; or can form opening connects chip 18 for gold thread wire jumper (wire bond) each contact terminal at the periphery or the middle position of substrate; and the cut-out position is in the registration holes 17 of Fig. 1 G two side positions; implant steps such as tin ball 19 and printing oxidation-resistant film at the upper surface place, to form the integrated circuit of CSP pattern.

Claims

1. a chip size packages method of manufacturing circuit board is characterized in that comprising the following steps:

Take Copper Foil as base material;

Substrate surface is carried out pressing, exposure and the development of first dry film, and utilize the dry film that develops to define the line pattern breach;

The line pattern breach is carried out plating mode insert the multilayer plating layer;

Remove first dry film;

To upper surface pressing polyimide film with as the protection;

Implement pressing, exposure and the development of second dry film, and only base material is carried out an etching removal and an etching formation registration holes in both sides; And

Polyimide film to the surface carries out laser-induced thermal etching, so that multilayer plating layer part expose or form pass through openings,

Form a kind of chip size packages circuit board that can adhere in the bottom and connect semiconductor chip by spot welding or gold thread thus.

2 a kind of chip size packages method of manufacturing circuit board according to claim 1 is characterized in that: described multilayer plating layer is to constitute with electrogilding, electro-coppering and electrogilding trilaminate material by lower floor to upper strata in regular turn.

3 a kind of chip size packages method of manufacturing circuit board according to claim 1, it is characterized in that: the thickness of described Copper Foil is about 6 Mills.

4 a kind of chip size packages method of manufacturing circuit board according to claim 1 is characterized in that: can implant the tin ball in the upper surface position that described multilayer plating layer exposes, to form the external contact of dimensional packaged circuit board.