TW201117291A - Method for processing semiconductor device - Google Patents

Method for processing semiconductor device Download PDF

Info

Publication number
TW201117291A
TW201117291A TW099100923A TW99100923A TW201117291A TW 201117291 A TW201117291 A TW 201117291A TW 099100923 A TW099100923 A TW 099100923A TW 99100923 A TW99100923 A TW 99100923A TW 201117291 A TW201117291 A TW 201117291A
Authority
TW
Taiwan
Prior art keywords
film
insulating film
gas
processing
etching
Prior art date
Application number
TW099100923A
Other languages
English (en)
Chinese (zh)
Inventor
Tetsuo Ono
Tetsu Morooka
Original Assignee
Hitachi High Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi High Tech Corp filed Critical Hitachi High Tech Corp
Publication of TW201117291A publication Critical patent/TW201117291A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H10P50/285—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means of materials not containing Si, e.g. PZT or Al2O3
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H10P72/0421—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching
    • H10P72/0422—Apparatus for fluid treatment for etching for wet etching

Landscapes

  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW099100923A 2009-11-05 2010-01-14 Method for processing semiconductor device TW201117291A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009253910A JP2011100822A (ja) 2009-11-05 2009-11-05 半導体素子加工方法

Publications (1)

Publication Number Publication Date
TW201117291A true TW201117291A (en) 2011-05-16

Family

ID=43925879

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099100923A TW201117291A (en) 2009-11-05 2010-01-14 Method for processing semiconductor device

Country Status (4)

Country Link
US (1) US8501608B2 (https=)
JP (1) JP2011100822A (https=)
KR (1) KR101133697B1 (https=)
TW (1) TW201117291A (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104053626B (zh) * 2011-10-28 2017-06-30 意法半导体股份有限公司 用于制造针对氢氟酸蚀刻的保护层的方法、设置有该保护层的半导体器件及制造该半导体器件的方法
JP6163446B2 (ja) * 2014-03-27 2017-07-12 株式会社東芝 半導体装置の製造方法
IT202100022511A1 (it) 2021-08-30 2023-03-02 St Microelectronics Srl Procedimento di fabbricazione di un sistema integrato includente un sensore di pressione capacitivo e un sensore inerziale, e sistema integrato

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6800326B1 (en) * 1997-01-14 2004-10-05 Seiko Epson Corporation Method of treating a surface of a surface of a substrate containing titanium for an ornament
US6245684B1 (en) * 1998-03-13 2001-06-12 Applied Materials, Inc. Method of obtaining a rounded top trench corner for semiconductor trench etch applications
JP2000252259A (ja) 1999-02-25 2000-09-14 Sony Corp ドライエッチング方法及び半導体装置の製造方法
JP4152271B2 (ja) 2003-07-24 2008-09-17 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
WO2005013374A1 (ja) * 2003-08-05 2005-02-10 Fujitsu Limited 半導体装置および半導体装置の製造方法
US20050081781A1 (en) * 2003-10-17 2005-04-21 Taiwan Semiconductor Manufacturing Co. Fully dry, Si recess free process for removing high k dielectric layer
US20050260804A1 (en) * 2004-05-24 2005-11-24 Tae-Wook Kang Semiconductor device and method of fabricating the same
JP2007115732A (ja) * 2005-10-18 2007-05-10 Renesas Technology Corp エッチング液およびそれを用いた半導体装置の製造方法
KR20080018711A (ko) 2006-08-25 2008-02-28 삼성전자주식회사 반도체 소자 및 그 제조 방법
US7820552B2 (en) * 2007-03-13 2010-10-26 International Business Machines Corporation Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack
JP5329294B2 (ja) * 2009-04-30 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
KR101133697B1 (ko) 2012-04-06
JP2011100822A (ja) 2011-05-19
US20110104882A1 (en) 2011-05-05
KR20110049619A (ko) 2011-05-12
US8501608B2 (en) 2013-08-06

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