TW200952106A - Test system - Google Patents
Test system Download PDFInfo
- Publication number
- TW200952106A TW200952106A TW098118028A TW98118028A TW200952106A TW 200952106 A TW200952106 A TW 200952106A TW 098118028 A TW098118028 A TW 098118028A TW 98118028 A TW98118028 A TW 98118028A TW 200952106 A TW200952106 A TW 200952106A
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- semiconductor wafer
- test
- semiconductor
- alignment mark
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2891—Features relating to contacting the IC under test, e.g. probe heads; chucks related to sensing or controlling of force, position, temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Tests Of Electronic Circuits (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2008/060171 WO2009147719A1 (ja) | 2008-06-02 | 2008-06-02 | 試験システム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200952106A true TW200952106A (en) | 2009-12-16 |
| TWI379369B TWI379369B (enExample) | 2012-12-11 |
Family
ID=41397810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW098118028A TW200952106A (en) | 2008-06-02 | 2009-06-01 | Test system |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP5368440B2 (enExample) |
| TW (1) | TW200952106A (enExample) |
| WO (1) | WO2009147719A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI656350B (zh) * | 2017-08-07 | 2019-04-11 | 日商泰克霍隆公司 | 探測站 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6471401B1 (ja) * | 2017-10-31 | 2019-02-20 | 合同会社Pleson | 半導体ウエハーの試験ユニット |
| CN114779034A (zh) * | 2022-04-13 | 2022-07-22 | 苏州晶睿半导体科技有限公司 | 一种基于半导体晶圆的测试设备和map图偏移检测方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07105432B2 (ja) * | 1986-10-09 | 1995-11-13 | タツモ株式会社 | 基板の自動位置合せ装置 |
| JPH11274252A (ja) * | 1998-03-19 | 1999-10-08 | Mitsubishi Electric Corp | 半導体装置の検査装置及びその検査方法 |
| JP2000164655A (ja) * | 1998-11-24 | 2000-06-16 | Matsushita Electric Ind Co Ltd | アライメント装置及びアライメント方法 |
| JP4423991B2 (ja) * | 2003-02-18 | 2010-03-03 | Jsr株式会社 | 異方導電性コネクターおよびプローブ部材並びにウエハ検査装置およびウエハ検査方法 |
| JP4867219B2 (ja) * | 2005-07-14 | 2012-02-01 | 株式会社デンソー | 検査装置及び検査装置の位置決め方法 |
-
2008
- 2008-06-02 JP JP2010515689A patent/JP5368440B2/ja not_active Expired - Fee Related
- 2008-06-02 WO PCT/JP2008/060171 patent/WO2009147719A1/ja not_active Ceased
-
2009
- 2009-06-01 TW TW098118028A patent/TW200952106A/zh not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI656350B (zh) * | 2017-08-07 | 2019-04-11 | 日商泰克霍隆公司 | 探測站 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2009147719A1 (ja) | 2011-10-20 |
| JP5368440B2 (ja) | 2013-12-18 |
| TWI379369B (enExample) | 2012-12-11 |
| WO2009147719A1 (ja) | 2009-12-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |