TW200952106A - Test system - Google Patents

Abstract

A test system is provided, which tests several semiconductor chips formed on a semiconductor wafer. The test system includes a chamber, in which the semiconductor wafer is moved; a testing wafer, fixed in the chamber and provided with several bumps conductively connected with the pads of several semiconductor chips; a wafer stage which moves the semiconductor wafer to a position opposite to the testing wafer by carrying and moving the semiconductor wafer in the chamber; a decison portion, installed at a specified position relative to the wafer stage, and detects the position of an alignment mark installed on the semiconductor wafer by scanning at least a portion of the surface of the semiconductor wafer when the semiconductor wafer is carried on the wafer stage and moved relatively to the wafer stage; and a position control portion which regulates the position of the semiconductor wafer carried on the wafer stage according to the position of the alignment mark detected by the decision portion.

Description

200952106 J J J 丄 .doc VI. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The present invention relates to a system. In particular, a plurality of semi-conductors formed on a wafer of a test wafer in which a conductor wafer is subjected to a test: [Prior Art] As a device for testing semiconductors, it is known that the right A plurality of semiconductor wafers, 隹J clothes 1 are known to have a plurality of pad electrodes on the circle by using a probe card, and the n-pin card can be used in the circle. In the device, the inspection of the patent document "Japanese Patent Publication" is carried out in the case of the inspection of the patent document. The Japanese Patent Publication No. 173503 (JP-A-2006-1995), however, in the above-mentioned apparatus, The circle and the probe card are moved from the inspection device. After the inspection, the test wafer is adsorbed on the _ needle card 3: the needle card to be inspected must be removed from the inspection device. 2. Break the test wafer and probe the alignment and inspection between the tested wafer and the probe card; test:, = adjust, this 'test transfer needle is reached. Moreover, the subordinate item stipulates the invention: Advantageously, i.doc 200952106^ In order to solve the above problems, a first aspect of the present invention provides a test system. A test system for testing a plurality of semiconductor wafers formed on a semiconductor wafer, comprising: a chamber body carrying a semiconductor wafer; a test wafer fixed in the chamber and provided with a plurality of semiconductor wafers a plurality of bumps electrically connected in a unified manner; the wafer stage moves the semiconductor wafer to a position facing the test wafer by placing and moving the semiconductor wafer in the chamber; The measuring unit is provided at a predetermined position on the wafer stage, and when the semiconductor wafer is moved to the wafer stage in order to mount the semiconductor wafer on the wafer stage, at least the surface of the semiconductor wafer is scanned a portion, wherein the alignment is set at a position on the semiconductor wafer; and a position control unit that mounts the semiconductor crystal on the wafer stage according to the position of the alignment target measured by the measuring portion Adjustment of the position of the circle. The second opening of the present invention provides a test system for testing a plurality of semiconductor wafers formed on a semiconductor wafer, a chamber for transporting a semiconductor wafer; a test wafer fixed in the chamber; a plurality of bumps integrally connected to the pads of the plurality of semiconductor wafers; and a wafer stage The semiconductor wafer is placed in the chamber and moved to move the semiconductor wafer to the position of the test wafer. The measuring unit is disposed on the movement path of the wafer stage, and the wafer stage is scanned by Locating at least two portions of the surface of the semiconductor wafer on which the semiconductor wafer is mounted, and detecting the position of the alignment mark provided on the semiconductor wafer and the position control portion, according to the position of the alignment mark measured by the measuring portion, The position of the semiconductor wafer is adjusted. •doc 200952106 In addition, the summary of the above invention does not enumerate the essential features of the invention. The entire β's 4 inch group of sub-community groups (sub_combinati〇n) may also be invented. [Embodiment] The present invention will be described below with reference to the embodiments of the invention. However, the following embodiments do not limit the invention of the claims. Further, all of the combinations of the features described in the embodiments are not necessarily required for the solution of the invention. FIG. 1 shows an overview of a test system 400 in accordance with an embodiment. Test system 400 tests a plurality of semiconductor wafers formed on semiconductor wafer 300. Moreover, the test system 4 can test a plurality of semiconductor wafers 300 side by side. The test system 4 has a control device 1A, a plurality of chamber bodies 20, a transport portion 4A, and a cassette (cassetie). The control device 10 controls the test system 4〇〇. For example, the control device 1 can control the chamber body 20, the transport portion 40, and the wafer cassette 60. The chamber body 20 sequentially receives the semiconductor wafer 3' to be tested and tests the semiconductor wafer 300 inside the chamber body 20. Each of the chambers 2 can independently test the semiconductor wafer 300. That is, each of the chamber bodies 2 can be tested on the semiconductor wafer 300 without being synchronized with the other chambers. The wafer cassette 60 stores a plurality of semiconductor wafers 3A. The transport unit 4 sequentially transports the plurality of semiconductor wafers 300 to be tested to the respective chambers. For example, the transport unit 40 transports the respective semiconductor wafers 3 stored in the wafer cassette 60 to a certain chamber 2 that is free. Inside. Further, the transport unit 4 can carry out the test-completed semiconductor wafer 300 from the chamber body 2 and store it in the wafer cassette 6〇-•aoc 200952106. FIG. 2 is a test summary of the test system 4〇〇. The wafer wafer 310 of the semiconductor wafer is tested by wafer cutting. : 卜 十 谷 + 导 仃 贝 贝 贝 贝 贝 贝 贝 贝 贝 贝 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The same (10) of the port 1 can be formed by the semiconductor wafer of the test object. For example, semiconductor wafer 300 can be a round semiconductor wafer. More specifically, the semiconductor wafer can be a semiconductor wafer or the like. Moreover, the test crystal 100 can have substantially the same diameter as the semiconductor wafer 3 of the test object. The semiconductor wafer 300 is mounted in the chamber body 20 at a predetermined position facing the wafer 100. Then, by moving the bulk wafer to coincide with the test wafer, the plurality of wafer side connection pads 112 of the test wafer 100 and the plurality of semiconductor wafers 310 are uniformly welded for inspection. Make electrical connections. For example, the 'semiconductor wafer lion is placed on the wafer stage ° in the chamber 2Q' and moved to the position facing the test cassette 1 100 by the wafer stage. The relative positions of the test wafer 100 and the wafer stage are adjusted in advance. Therefore, the test system 400 can align the semiconductor wafer 300 with a predetermined position by testing the wafer 1 by placing the semiconductor crystal lens 3 at a predetermined position on the surface of the wafer stage. . On the surface of the test wafer 100 that faces the semiconductor wafer 300, a plurality of solder pads corresponding to the respective pads of the half-paste-day wafer 310 can be formed. In addition, the test wafer 100 and the semiconductor wafer 3 (8) can be directly contacted by 200952106.

'X / V / L / H..d〇C is electrically connected, and it can also be electrically connected by a combination of electrostatic bonding, induction bonding, or the like. Further, the test wafer 100 and the +conductor wafer 300 can transmit and receive signals via the optical transmission path. The wafer 100 can be electrically connected to the semiconductor wafer 300 of the test object to transmit a signal between the control device G and the semiconductor wafer. For example, the semiconductor wafer 3 (8) can supply control test signals to the respective semiconductor wafers of the semiconductor wafer 300. ^Send===The surface of the signal output is more than two: = The crystal wafer 310 is selected for the body crystal, and the wafer (10) can be generated and supplied to the bank. =, = circuit portion 110. Oh, and the corresponding semiconductor wafer 3 can also be processed. Each of the circuit units 110 can independently support the output of the surface, the control signal, and the like. The power supply to the path portion H0 is shown in Fig. 3 as an example of a method of aligning the positions of the semiconductor wafer 3A with the crystal plate 41(). _ 4H) and the top of the semiconductor wafer H is shown as the wafer stage. Right, the target... The test system 400 of this example has a test portion 406'_疋4〇6 for the first two relative positions. Further, an alignment mark, 226 is formed in the semiconductor dome such as the n 囫 carrier port 4]. In the predetermined position of the 曰曰〇〇〇, the measurement unit is biased in order to mount the semiconductor wafer 300 on the wafer stage 200952106 4/0, and the semiconductor wafer 300 is moved to the wafer stage 4]0. By scanning at least a portion of the surface of the semiconductor wafer 300, the position of the alignment on the semiconductor wafer 3 is measured. For example, the portion 406 can capture the semiconductor wafer. And arranging at least a portion of the surface of the semiconductor wafer 300 by passing the semiconductor wafer 3 through the scanning position. For example, In the semiconductor wafer 300, if an alignment mark or 226 is formed on a surface facing the wafer stage 410, the strip is measured and the I-day yen: two ft-conductor wafers 3〇0, such as The alignment mark 226' is formed on the moon opposite to the wafer stage 410. The measurement unit 406 玎5·罟:&曰

Ports, ..., sub-pairs are imaged by the upper semiconductor wafer 300. The = portion 406 is set at the alignment with the coordinates of the cliff / go. Gu, ': 日il 士士七4...

The position corresponding to the position of 226 is roughly adjusted before the semiconductor wafer 300 and the wafer wafer 300 of the semiconductor wafer 300 are transported into the chamber body 丄.doc 200952106. Therefore, as shown in FIG. 3, the measuring unit 4〇6 can set the imaging range in the direction in which the traveling direction of the semiconductor wafer 3 (hereinafter referred to as the γ direction) is perpendicular (hereinafter referred to as the X direction). It is smaller than the diameter of the semiconductor wafer. For example, the imaging range of the measuring unit 406 in the X direction is about 2 to 3 times that of the alignment target 226. The measuring unit 4〇6 has a plurality of imaging elements arranged at a predetermined pitch along the x-direction in order to detect the position of the alignment mark 22〇 in the x-direction. Further, the position of the measuring unit 406 in the X direction is changeably provided. The test system can change the position of the measuring unit 406 in the X direction based on the position data of the alignment mark 226 which the user first assigned. Further, the measuring unit 4G6 is provided at a plurality of positions on the axis in the X direction at different positions. In this case, the position of the plurality of alignment targets can be detected, so that the position of the semiconductor wafer can be detected with higher precision. Fig. 4 shows a part of the image of the measurement of the lesion. As described above, σ06 has a plurality of image pickup elements 4〇7 along the X direction, so that the resolution of the image pickup element can be commensurate with the resolution of the image pickup element, and the position of the alignment mark 226 in the χ direction can be detected. It is preferable that the pitch of the image pickup element is smaller than the width in the Χ direction of the alignment mark 226. Moreover, the imaging element 4〇7 has a smaller tolerance range, and the tolerance range of the alignment error is based on the semi-guided S circle 1 (10), the Λ20-牛日日 0 300, and the test. The wafer terminal 测试 terminal test system 400 horizontally measures the position of each of the alignment keys 226 in the X direction from the map taken by each measurement unit 406. Further, the position control unit of the test system 4 can determine the position in the Y direction of the time 226 when each of the alignment marks 226 is detected by each measurement unit "•doc 200952106 40. For example, the position calibration is performed for each alignment calibration. After the portion 406 detects the alignment mark 226, the portion is moved on the semiconductor wafer only in the Y direction in each measurement, to detect that the semiconductor wafer 300 is placed on the right-hand Japanese yen stage. 410 is aligned with the Y-direction position of the index 226. After the round-shaped stage is mounted, the position control unit of the test system 400 can detect the X-squares of each of the alignment marks 22ό. The position is calculated by the rotation of the semiconductor wafer 300: the amount of rotation of the circle 300 in the position and the Y direction, which is the amount of rotation of the wafer 2, for example, the position of the test system, and the amount of rotation is controlled. Alignment mark 226

See the corner of the position. The rotation angle can be determined by the χ direction and Y

(J alignment target 226 _ measurement position and alignment mark 22 (four) positive touch difference =, and the distance from the center of the semiconductor wafer to the alignment mark =. The position control unit for the test secret _ The distance between the center of the semiconductor wafer 300 and the alignment mark 226. The position control unit of the test system 400 can be based on the position in the X direction, the position in the γ direction, and the rotation of the alignment 226 by the above-described square measurement. The amount 'to control the wafer stage 41 〇. The crystal stage has a horizontal stage in which the χ direction, the γ direction, and the rotation amount can be entered in the state in which the semiconductor wafer is placed. Moreover, the position control of the test system is complete. The unit can adjust the current position according to the offset measured by the measuring unit 406 to control the horizontal stage of the 200952106 _> i ^> / wjjii.doc, and adjust the semiconductor mounted on the wafer stage 4] 0 The position of the wafer 300 in the X direction and the Y direction and the amount of rotation. Fig. 5 shows an example of the internal structure of the chamber body 2. The semiconductor wafer 300 to be tested is sequentially transported to the chamber body 20, and the chamber The test wafer fixed in the body 20 is electrically connected to the inside of the chamber body 20. A test wafer 1 , a performance board 404 , a mother board 402 , a wafer tray 4 8 , a wafer stage 41 , a guide measurement unit 406 , and a position control unit 450 are provided. 100 is fixed in the chamber body 20. In this example, the test wafer 100 is fixed on the performance board 404 in the chamber body 2. The performance board 404 can be, for example, a printed board on which wiring is formed. The 404 can be fixed on the motherboard 402 in the chamber body 20. The motherboard 4G2 transmits signals between the control device 1A and the test wafer via the performance board 404. A thin film of bumps (bUmP) is used for the surface of the semiconductor wafer 300. The test wafer 100 utilizes the plurality of bumps, and the solder bumps of the wafer 300 are ==300 The plurality of semiconductors formed above are electrically connected first. The Japanese yen carrier 4] is moved in the palace. In this example, the semiconductor wafer is placed on the wafer carrier 408, and The wafer 300 is fixed by adsorption or the like, and the wafer stage == 410 is placed on the wafer carrier 4〇8, and is connected to the guiding portion 418 and the guiding portion 420. For example, the guiding unit 4 causes the connection of the semiconductor wafer 300 to be mounted on the stage 410' from the transport unit 4A and the test wafer (8) to "the specified position of the doc 200952106 direction only + 0a". The sample can be moved along the path of the path. The guide is set to follow the path of the rule.

After the day Bayo 410 moves to the test wafer 1〇〇A, β is placed, and the semiconductor wafer 100 is electrically aligned with the predetermined test wafer 100;:: moving in the straight direction and perpendicular to the measurement The stage 41 Γ aB® stage 4 〗 G has a horizontal staged table 2: wafer holder 4 〇 8 ′ and adjusts the position of the semiconductor wafer 3 . 0 semiconductor wafer 300 . Water = Load: 412 The direction of the χ in the plane and the surface of the surface, such as Λαα / 干岭虹日日® 300, by means of semiconductor ==;==: Adjustment. Then: (4)·"pad and test_ wafer 1 (8) are connected to each other. The horizontal stage 412 is placed on the horizontal surface of the horizontal stage 412, and the position of the horizontal stage 412 is controlled. For example, the vertical stage 416 can be used for the test wafer 1. At the opposite position, the horizontal stage 412 in which the semiconductor 曰曰: the state of the circle is placed is close to the test crystal (10), thereby electrically connecting the semiconductor wafer 3GG and the test wafer (10). = vertical load ~ stage 416 can decompress the semiconductor wafer and the test wafer after the semiconductor wafer 3 is connected to the test wafer, and then the semiconductor wafer and the test wafer are decompressed. It is electrically connected to the test with 曰曰0 100. Moreover, the support portion 418 can be mounted on the vertical stage 41. As described in connection with FIG. 4, the position control unit 450 performs the measurement of the image taken by the 200952106 j 丄"/upu_.doc portion 406 to the position of the wafer stage 4i. The position control unit 45G adjusts the position of the horizontal stage 412, and adjusts the position of the crystal so that each of the semiconductor wafers 3 is placed on each of the bumps of the test wafer 1()(). The location. Further, the test wafer position debt measuring unit 422 is fixed to the wafer stage. The position of the test wafer 1 is measured in advance. For example, the measurement wafer position forming unit 422 can preliminarily compare the relative position of the test wafer 1 〇〇 in the wafer stage 410 disposed on the predetermined bit i B . The horizontal stage 412 is preferably disposed on the vertical stage 6 because the horizontal plane === 'interaction'. The position control unit 450 can connect the test wafer cassette (8) and the terminal of the semiconductor wafer 300 with high precision, and can also determine the position of the test wafer 1〇〇 measured by the test wafer position detecting unit 422. Come to level the stage 412. With this configuration, the position of the semiconductor wafer 3 (8) to the test wafer 100 can be adjusted, and a plurality of terminals of the semiconductor wafer 3 can be electrically connected to the terminal of the test a circle. Moreover, since the position of the test wafer 100 of this example is fixed in the chamber body 20, the test wafer position detecting unit 422 may not replace the test wafer 1 when the semiconductor wafer 3 is replaced. The position is measured. The test wafer position detecting unit 422 may measure the position of the test wafer 1GG for each predetermined period. Therefore, a plurality of semiconductor wafers can be efficiently tested. In the above description, the measuring unit 406 is the position of the alignment mark 226 of the wafer 300 during the movement of the semiconductor wafer 200952106udoc 300 on the wafer stage 410. In another example, portion 406 may also be used to place semiconductor wafer 300 on wafer stage 41 and move wafer stage 410 from position A to position B. The position of the standard mark and 226 is carried out. The body measuring unit 406 is placed on the moving path of the wafer stage 41, and the semiconductor wafer 3 placed on the lower wafer stage 410 is partially scanned. At least FIG. 6 of the clothing surface is not an illustration of an example of the detection 226 during the movement of the wafer stage 4. As an example, the mother board 402 of this example is fixed at a predetermined position, and the portion of the ^ 〇 6 conductor wafer 300 is imaged. In this example, 3 = the traveling direction of the stage 410 is Α γ ancient one t day and day «the direction of the direction of the X direction is perpendicular to the direction of the traveling direction. Even in this example, the measuring unit 4Q6 is also shown. 3 to the measurement section of the figure is called the same _ image. ^, _ = according to the image detected by the measuring unit 406, the horizontal stage 412 is controlled. The position control unit 450 can detect the alignment of the wafer on the basis of the measurement unit 406. The position of the pair is detected by the γ square of the table 41 and the upward position ' in the Υ direction of the standard 226. The difference between the position B in the Y direction of the wafer stage 41 and the position B in the Y direction when the wafer stage 41 is aligned with the measurement unit 40 6 is detected from the measuring unit 40 6 , and the position on the H is in the direction shown in FIG. 5 . position. The 丫 position control unit 450 of the debt-measuring index 226 measures the position of the X-direction and the Y-direction of the 200952106 D 1 J> / upn-doc 226 according to the respective alignments thus detected, and the horizontal stage 4] The position of the 乂 and Y directions and the amount of rotation are adjusted. Thus, even in the movement of the wafer stage 410, the position of the alignment mark 226 in the X direction and the γ direction can be detected, and the position of the semiconductor wafer 3 进行 can be adjusted: FIG. 7 shows the wafer carrier. An illustration of another example of detecting the alignment mark 226 while the stage 41 is moving. The test system 4 (8) of this example has a measuring unit 406. Further, even in the case where the alignment mark is detected while the wafer stage 410 is transporting the semiconductor wafer 300 as described with reference to FIG. 3, the same can be detected by using one measuring unit 4〇6. In this case, a plurality of alignment marks 226 may be provided on the semiconductor wafer 3 as shown in FIG. 7 at substantially the same position on the axis in the X direction. The measuring unit 406 is disposed in such a manner as to detect the position of the alignment marks 226. With such a configuration, the positional deviation and the amount of rotation in the X direction and the Y direction of the semiconductor wafer 3 can be detected. Further, in Figs. 3 to 7, a rectangular alignment mark 226 is shown as an example, but the shape of the alignment mark 226 is not limited to this shape. The alignment mark 226 may have a prescribed shape such as a cross. Moreover, the alignment mark 226 may have a plurality of pads arranged in a predetermined shape. FIG. 8 shows an example of a cross-sectional view of the test wafer 100. The test wafer 100 of this example transmits a signal between the control device and the semiconductor wafer 300 as described above. The test wafer 1 has a wafer side connection pad m, a device side connection pad 114, a through hole n6, an intermediate pad, and a wiring 117. iLdoc 200952106 曰: As shown in FIG. 8, the wafer connection surface 102 and the device connection surface 104 are 9/, and the semiconductor wafer 300 faces the surface. Further, a plurality of wafer side-mounted "electrical (four) circular connection faces K) 2h^ are formed in the test wafer 100, and the wafer pads 112 can be connected to each of the half wafer sides. That is, in the case of the = terminal, a plurality of each of the wafer side connector tabs 310 are provided. For each semi-conductor, each wafer side connection pad U2 is placed at the same interval at the same interval, and each wheel and the terminal are electrically connected. In addition, the 匕+^ body wafer Ο:: "2 and semi-conducting = two = state. The connection. The crystal splicing, row 2 in J: ί: the output of the conductor wafer 310 eight terminals - Figure 10 The soul, the special edition has a connection with the position of each pad, and the wafer side is connected to the pad 112 and the half: ' can also be combined with the f capacity (electrostatic combination = 3iq - combined), etc. In the non-contact state, the center of the core 1 and the semiconductor wafer 31 are connected. The core of the core is transferred to the portion of the line L.doc 200952106, which can also be an optical transmission line. The device side connection pad 114 of the 00 is formed on the test straight connection surface 104 and is electrically connected to the performance board 404 $. The connection pad 114 is connected to the plurality of wafer sides 12 One-to-one milk correspondingly, set. Here, the terminal of the device side connection pad Hi and the performance board 4〇4 are disposed at the same interval. Therefore, as shown in FIG. 8, the device side connection #mat 114 can be combined with the crystal. The round side connection pads are provided at different intervals. The bucket 116, the intermediate pad 150 and the wiring 170 are formed in the test m. The round side connection pad η 〗 and the device side connection connection surface are connected. For example, the intermediate pad 150 is disposed at the position where the device hole m is connected to the side of the bonding pad 112. The through welding 2 ==, The other end and the intermediate wiring 117 are formed on the device connection surface 丨〇4, and the connection pads are electrically connected. The ": 蝉 pad 15 〇 and the device side are connected to different device side connection pads. 114 =, into, can electrically connect the array. For example, the wafer side connection pads 112 are electrically connected to each input terminal, and each J/, semiconductor wafer 3] is arranged. Therefore, the wafer side connection pads = terminals are disposed at the same interval on each of the semiconductor wafers 310, and are disposed on the pre-stones, for example, as shown in Fig. 2. The area of the germanium and the germanium are connected at a small interval, and the connection pads 4 of the respective devices can be connected to the plurality of wafer sides corresponding to the semiconductor wafers 200952106 ^ ± ^ / v / ^ / a1.c1 〇 c f0 The welding 塾 is separated by a large interval and 5 is placed again. For example, the device side connection pads U4 are disposed at equal intervals in the plane of the device connection surface 104 so that the device side connection pads 1 are substantially equal. Since the test wafer 1〇〇 and the semiconductor wafer 3〇〇 are formed of the same f-conductor material, the test wafer 1 is well maintained even when the ambient temperature fluctuates. Electrical connection to the semiconductor wafer 3〇〇. Therefore, even in the case of heating the semiconductor wafer 300 and performing the test, the semiconductor wafer 300 can be accurately tested. Further, since the test wafer 1 (10) is formed of a semiconductor material or the like, a plurality of wafer side bonding pads U2 and the like can be easily formed on the test wafer (10). For example, the wafer side connection pad 2, the device side connection pad 114, the through hole Π6, and the wiring in can be easily formed by a semiconductor process such as exposure. Therefore, a plurality of wafer side connection pads 112 and the like corresponding to the plurality of semiconductor wafers 310 can be easily formed on the test wafer 1A. Further, the test wafer 1 is formed by applying an electric ore, a vapor-conducting conductive material or the like to the final circle 100. On the collection date, Fig. 9 shows an example of the configuration of the circuit unit 110. The circuit unit n〇 includes a diagram f generation unit 122, a waveform shaping unit 130, a driver 132, a comparator 134, a sequence generation unit 136, a logic comparison unit 38, a characteristic measurement unit 140, and a lightning source supply unit, and a circuit unit uo Each of the pins of the output pin that can be connected: half =, 310 has the configuration shown in FIG. The pattern generation unit I22 generates a logical pattern of the test signal. The pattern generating unit 122 of this example has a pattern memory 124, an expected value memory, and 19

200952106^ j) 1 j / u}Jii-.d〇C Failure memory m. The pattern generating unit 122 can write a pre-stored logical pattern to the pattern. The pattern memory 124 can store the logic pattern assigned from the control device = at =. Moreover, Tuan ° = 122 can also be generated according to a pre-assigned algorithm (alg〇rithm): a logic two pattern. The waveform forming unit 130 forms a waveform of the test signal based on the pattern given from the pattern generating unit 122. For example, the waveform shaping unit 13〇3 outputs a waveform of a test signal by outputting a voltage 'of each of the logic patterns every predetermined period of time. The drive driver 32 outputs a test signal that is nicknamed from the wave given from the waveform shaping unit 13A. The driver 132 can output a test signal according to a timing signal from the timing generating unit. For example, the driver 132 can output a test signal of the same period as the sequence k. The test signal output by the driver 1% is supplied to the corresponding semiconductor terminal 310 via the switching portion or the like. The stencil is compared to 134 to determine the response signal output by the semiconductor wafer 310. For example, the comparator 134 can detect the logical value of the response signal by sequentially detecting the logical value of the response signal according to the strobe signal from the timing generating unit 136. The ', & sound logic comparing unit 8 functions as a determining unit to determine the quality of the corresponding semiconductor die 310 based on the logical pattern of the response signal measured by the guard 134. For example, the logic comparing unit 138 can determine whether or not the semiconductor wafer 31 is good or bad based on whether or not the expected value pattern given from the solid=generating unit 122 and the comparator 134 match the pattern. The pattern ^ 20 丄 doc 200952106 ^ section 22 can supply the expected value memory %% to the logic comparison unit 138. The expected value map stored first, stored in the control device] 〇 = = body m can be tested = generating part 22 can also be based on her pre-pattern. Moreover, the graph is a value pattern. The algorithm of M is used to generate the period, and the memory ratio of the memory is compared with the result of the comparison of =38 on the semiconductor wafer 31G. For example, the failed memory 128 can be tested in the semi-conductor=product domain, and each address of the comparison m is judged, and the memory of the memory is 128. Reading out the missing mat ι14 can be invalidated = fruit. For example, the device side is connected, and the result is judged by (4) (10), and the shape is transmitted or forgiven. 2%;:::;, the voltage output by the actuator 132 is based on whether the waveform of the voltage exerted from the fixed portion of the driver is full or not. The regulation (10) pattern 1 determines the swivel wafer 310 310. Example i Source power, used to drive semiconductor wafers, to the power phase test from the control device]. Further, the power supply unit 142 also gives "to the semiconductor wafer 310. Give drive power. Since each component of the circuit unit 110 is provided with the configuration of the control unit 110, it is possible to realize a test system capable of reducing the scale of Μ10. For example, 200952106 DID/wpu.doc 10, which can utilize a general-purpose personal computer or the like. Fig. 10 shows an example of a configuration in which the test wafer 100 and the semiconductor wafer 300 are electrically connected. In the test system 400 of this example, the test wafer 100 and the semiconductor wafer 300 are disposed in a sealed space, and the pressure is reduced in the sealed space, so that the test wafer 1 and the semiconductor wafer 300 are close to each other. And make electrical connections. More specifically, a sealed space is formed between the performance board 404 on which the test wafer 100 is fixed and the wafer holder 408 on which the semiconductor wafer 300 is placed. Further, an anisotropic conductive sheet is provided between the performance board 404, the test wafer 100, and the semiconductor wafer 300, respectively. Then, by decompressing the inside of the sealed space, the test wafer 100 or the like is pressed to press the anisotropic conductive sheet, and the test wafer 100 or the like is electrically connected. Therefore, the test wafer 100 is fixed to the performance board 404 in a form movable in the vertical direction. Further, it is preferable that the test wafer 100 is within the allowable range of the alignment error between the test wafer 100 and the semiconductor wafer 300 in the horizontally movable range. For example, the range in which the test wafer 1 is movable in the horizontal direction is preferably sufficiently small as compared with the pad width of the test wafer 1 (8) and the semiconductor wafer 3 (8). The test wafer 100 is fixed to the performance board 404 by the support portion 204. The support unit 204 fixes the device-side anisotropic conductive sheet 212, the device-side sealing portion 214, the test wafer 00, the wafer-side anisotropic conductive sheet 218, the film 222, and the fixing ring 220 to the performance board 404. The device side anisotropic conductive sheet 212 is disposed on the test wafer 100 丄doc 200952106 and the performance board 404; 5丨丨4 anti-electrode and performance board _ test ^ day yen (10) pressing device side anisotropic conduction Piece $Electrical: Connection/Test Wafer _ ;= ί: The position in the vertical direction below the 4能4 of the Na Neng board; supported by the displacement of the dry circumference of the gauge. _ ί ί side seal portion 214 along the side of the performance plate 4G4 side of the film 222

C and sealing between the peripheral films 22/4 of the surface of the film 222 on the side of the performance plate 4〇4. The device-side sealing portion 214 can be formed by: providing a laterally anisotropic conductive sheet 212 and having a flexible elasticity (4). The next day, the conductive sheet 218 is placed on the test wafer and the thin support; 3: the round-side anisotropic conductive sheet 218 presses the side connection terminal and the thin (four) bump terminal into the second The cymbal 218 and the semiconductor crystal are electrically connected to the crystal-cut terminal of the test crystal. The fixing ring 220 fixes the film 222 to the device side sealing portion 214. For example, the fixing ring 22A may be provided in a ring shape along the periphery of the semiconductor of the film Μ2. The inside of the fixing ring 22〇 can be larger than the diameter of the crystal-oriented conductive sheet 218 and the semiconductor wafer. The 222 and the ankle ring 22G have substantially the same circular shape and are positioned on the fixed ring 22''. The device side anisotropic conductive sheet 212, the reduction and subtraction crystal ffl 1GG, and the wafer side anisotropic conductive sheet 218 are disposed between the domain film 200952106 JJJ / upu.doc 222 and the performance board 4G4, and utilize the film 222 (four) performance board. 4〇4保# In the position of the gauge h, as shown in Fig. 1Q, on the device side, the anisotropic conductive sheet zl2, the j test, the round circle]00 and the wafer side anisotropic conductive sheet training and device side sealing A gap may be provided between the portions 214. With such a configuration, the thin film melon is pressed by the semiconductor wafer 3GG, whereby the semiconductor wafer 300 and the test wafer 1O0 can be electrically connected. The support unit 204 supports the film 222 and the like by supporting the fixed ring 22〇. The support portion 204 can contact the underside of the performance board 4〇4, which is close to the specified range, and supports the wafer (10). For example, the support portion 2〇4 can fix the lower end of the ring 22〇 from the lower side of the performance inverse 404 without leaving the 敎 distance, and at the lower end of the fixed ring 22 at a position away from the lower side of the performance plate 404 by a predetermined distance. Support. When the wafer carrier # 408 is placed at a predetermined position, it is provided in a form in which a disk space = 04 forms a sealed space. In the wafer holder 4 of the present example, the wafer side sealing portion 224 is formed on the surface of the sealed space side, the performance side, the device side hole portion 214, and the wafer side sealing portion 224. On the surface of the wafer carrier 4〇8, the peripheral portion of the 222 is disposed corresponding to the area, and the white portion of the peripheral portion of the surface on the side of the thin bracket and the wafer carrier is white-crystallized. The round side sealing portion 224 can be formed on the surface of the wafer carrier; Γ Γ, the wafer side sealing portion 224 is formed to have a large lip, and the distance of the surface of the circular bracket 4 (10) is increased, and the diameter of the ring is === 24 200952106ldoc When the sealing portion 224 is pressed against the cage/on the skin 222, the distance between the film 222 and the semiconductor wafer 3 is close to two according to the pressing force of the pressing force, and the wafer side is sealed. The height of the portion 224 from the surface of the wafer carrier 4G8 that is not pressed against the film is still high. The vertical load 416 described in connection with Fig. 5 causes the wafer carrier tip to move 'until the upper end portion of the wafer side seal portion 224 is in close contact with the film 222. With such a configuration, the performance board 4〇4, the wafer carrier 408, the device side sealing portion 214, and the wafer side sealing portion 224 can be used to form the sealing film for storing the test wafer 100 and the semiconductor wafer 3 space. Further, the horizontal stage 412 preferably moves the wafer carrier 408 in the vertical direction on the vertical stage 416, and the position and inclination in the horizontal plane of the semiconductor wafer 300 are preferably adjusted. The decompression unit 234 decompresses the sealed space between the performance board 404 and the wafer holder 4〇8, which is composed of the performance board 404, the wafer holder 4〇8, the device side sealing unit 214, and the wafer side. The sealing portion 224 is formed. The decompression unit 234 decompresses the sealed space after the wafer stage 410 moves the wafer dry frame 408 to form the above-described cold-closed buckle. Thereby, the pressure reducing portion 234 brings the wafer carrier 408 close to the predetermined position of the performance board 4〇4. The wafer carrier 408 is placed at the predetermined position to apply a pressing force to the device-side anisotropic conductive sheet 212 and the wafer-side anisotropic conductive sheet 218, so that the performance board 404 and the test wafer 1 are folded. The electrical connection is made, and the test wafer 100 and the semiconductor wafer 3 are electrically connected. 200952106

o ij> / wpu.doC Moreover, the wafer side seal is in contact with the film 222. On the side of this = can be "ff20 (four) side" and divided into the side of the performance board 404 饴 饴 才 才 才 才 才 才 才 才 222 222 222 222 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Further, 222 is placed in the through hole 242 for connecting these spaces. Further, on the test wafer 1 圆 $ circular side: the directional conductive sheet / 8, the through hole 2 is also provided with two sheets = 13 and a passhole 219. The car is like a film, the test crystal, the conductive conductive sheet 2U and the wafer-side anisotropic conductive sheet 218', the beacon hole' is uniformly dispersed in each plane, and the composition is In the process of depressurizing the closed space, "a plurality of through holes are used to disperse the flow. Further, the through holes such as the holes 24, the through holes 213, and the through holes 219 may be disposed at corresponding positions, and may be disposed at positions different from each other. Therefore, in the process of depressurizing the sealed space, the pressing 2 applied to the conductive conductive sheet 212 and the wafer-side anisotropic conductive sheet 218 can be dispersed in the respective surfaces, and is greatly reduced. Small decompression = stress skew. Therefore, it is possible to prevent the crack of the test wafer 1 、, the skew of the directional conductive sheet, and the like. With this configuration, the space between the performance plate 404 and the film 222 and the space between the film 222 and the semiconductor wafer 300 can be decompressed by the pressure reduction 234. force. Further, the decompression portion 234 allows the semiconductor wafer 300 to be adsorbed on the wafer stub 408. The pressure reducing portion 234 of this example has a pressure reducer 236 for a sealed space and a pressure reducer 238 for a semiconductor wafer. Further, on the wafer carrier 4'8, 26 200952106 "i"/uyi丄.doc forms an intake path 232 for the sealed space and an intake path 230 for the semiconductor wafer. With this configuration, the test wafer 100 fixed on the performance board 404 and the semiconductor wafer 300 can be electrically connected. As described above, since the test wafer 100 is fixed to the performance board 404, alignment between the test wafer 1 (8) and the semiconductor wafer 300 can be easily performed. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows an outline of a test system 400 according to an embodiment. 2 is a schematic illustration of a test of test system 400. FIG. 3 is an example of a method of aligning the semiconductor wafer 300 with a predetermined position of the wafer stage 410. FIG. 4 shows a part of an image scanned by the measuring unit 406. Ο FIG. 5 shows an example of the internal structure of the chamber body 20. FIG. 6 is an explanatory diagram showing an example of detecting the alignment mark 226 while the wafer stage 410 is moving. FIG. 7 is an explanatory diagram of another example of detecting the alignment mark 226 during the movement of the wafer stage 410. FIG. 8 is an example of a cross-sectional view of the test wafer 100. FIG. 9 is not an example of the configuration of the circuit 110. Fig. 10 shows an example of a configuration in which the test wafer 100 and the semiconductor wafer 300 are electrically connected to each other. [Explanation of main component symbols] 1 A 丄U aV, T tH: ancestral 帀丨" clothing: 20 chamber body 40 transport unit 60 wafer cassette 100. Test wafer 102: wafer connection surface 104: device connection surface 110 : circuit portion 112 : wafer side connection pad 114 : device side connection pad 116 : through hole 117 : wiring 122 : pattern generation portion 124 : pattern memory 126 : expected value memory 128 : failure memory 130 : wave shape Unit 132: Driver 134: Comparator 136: Timing generation unit 138: Logic comparison unit 140: Characteristic measurement unit 28. i.doc 200952106 142: Power supply unit 150: Intermediate pad 204: Support portion 212: Device side anisotropy Conductive sheet 213: through hole 214: device side sealing portion 218: wafer side anisotropic conductive sheet 219: through hole

220: fixing ring 222: film 224: wafer side sealing portion 226: alignment mark 230: suction path 232: suction path 234: pressure reducing portion 236: pressure reducer 238: pressure reducer 240: through hole 242: Through hole 300: semiconductor wafer 310: semiconductor wafer 400: test system 402: mother board 404: performance board 29 200952106

^ XIV/^/AX.Ci〇C 406 : Measurement unit 407 : Imaging element / 1 AQ · 曰Γ ^ Ι Upper / Force H-UO · IEJ < TG 糸 410 : Wafer stage 412 : Horizontal stage 416 : vertical stage 418 : stage support portion 420 : guide portion 422 : test wafer position detecting portion 450 : position control portion 30

Claims (1)

200952106 VII. Patent application scope: 1. A test system for testing a plurality of semiconductor wafers formed on a semiconductor wafer, including a chamber body, carrying the semiconductor wafer; testing wafer, Fixed in the chamber body, and provided with a plurality of bumps electrically connected to the plurality of pads of the semiconductor wafer; the wafer stage is mounted on the semiconductor wafer and moved Moving the semiconductor wafer to a position facing the test wafer; and the measuring unit is disposed at a predetermined position on the wafer stage, and is configured to mount the semiconductor wafer on the wafer stage The semiconductor wafer detects the position of the alignment mark provided on the semiconductor wafer by scanning at least a portion of the surface of the semiconductor wafer when moving the wafer stage; and the position control unit according to the foregoing The position of the alignment mark measured by the measuring unit, and the position of the semiconductor wafer placed on the wafer stage To adjust. 2. The test system according to claim 1, wherein the measuring unit has a plurality of image pickup elements arranged in a vertical direction substantially perpendicular to a traveling direction of the wafer stage, and the image is captured according to the alignment mark. And detecting a position of the alignment mark in the vertical direction, wherein the position control unit is in the vertical direction of the semiconductor wafer according to a position of the alignment mark measured by the measurement unit Location 31 200952106 J 丄一, / V/pil .doc Make adjustments. 3. The test system according to claim 2, wherein the position control unit detects the timing of the alignment mark based on the timing of the detection unit on the semiconductor wafer mounted on the wafer carrier The position in the direction of travel is adjusted. 4. The test system according to claim 3, wherein the measuring units are respectively disposed at different positions on the axis in the vertical direction. 5. The test system according to claim 1, wherein the position control unit is configured to mount the semiconductor crystal on the wafer stage according to a timing difference when the measurement unit detects the alignment mark. Adjust the circle rotation 罝. 6. The test system according to claim 5, wherein the position control unit is previously provided with a distance between a center of the semiconductor wafer and the alignment mark, and then adjusts a rotation of the semiconductor wafer according to the distance. the amount. 7. A test system for testing a plurality of semiconductor wafers formed on a semiconductor wafer, comprising: a chamber body carrying the semiconductor wafer; and a test wafer fixed in the chamber Providing a plurality of bumps electrically connected to the plurality of pads of the semiconductor wafer; the wafer stage moves the semiconductor wafer by placing and moving the semiconductor wafer in the chamber a position facing the test wafer; i.doc 200952106, the measuring unit is disposed on the moving path of the wafer stage, and scanning at least the surface of the semiconductor wafer mounted on the wafer stage And detecting a position of the alignment mark provided on the semiconductor wafer; and the position control unit adjusts a position of the semiconductor wafer based on a position of the alignment mark measured by the measurement unit. 8. The test system according to claim 7, wherein the position control unit detects the position of the wafer stage in the traveling direction when the measuring unit detects the alignment mark, and the semiconductor wafer is The position in the aforementioned traveling direction is adjusted. 9. The test system according to claim 8, wherein the position control unit senses the semiconductor wafer at each position in the traveling direction when the alignment unit detects the alignment mark The amount of rotation of the wafer is adjusted.