JP2000164655A - Method and device for alignment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately align a probe terminal provided at a probe seat with an inspection electrode formed at a semiconductor wafer. SOLUTION: A wafer tray 10 for holding a semiconductor wafer 1 is placed on a Z/θ table 21 which is movable in a Z-axis direction and a θ direction, while the Z/θ table 21 is held tightly by an X/Y table 22 movable in X and Y-axis directions, with the semiconductor wafer 1 being movable in the Z-axis θ-, X-axis, and Y-axis directions. A wiring board is held by a holding board 23 comprising two through-holes 23a. A device main body 25 is provided with two camera holding arms 26, extending toward each through hole 23a of the holding board 23, and a CCD camera 23 is fixed to the tip part of each camera- holding arm 26, which reads each image of a first alignment mark of the semiconductor wafer 1 and a second alignment mark of a probe seat positioned near each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alignment for aligning a first alignment mark formed on a semiconductor wafer with a second alignment mark formed on a probe sheet having optical transparency. For the apparatus and the alignment method, specifically, each probe terminal of a probe sheet is connected to each inspection electrode of a plurality of semiconductor integrated circuit elements formed on a semiconductor wafer, and electrical characteristics of the plurality of semiconductor integrated circuit elements are measured. The present invention relates to an alignment apparatus and an alignment method used when performing a batch inspection in a wafer state.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device, after a semiconductor integrated circuit element and an inner lead of a lead frame are electrically connected by a bonding wire, the semiconductor integrated circuit element and the inner lead are sealed with resin or ceramic. It was supplied in a state where it was mounted on a printed circuit board.

However, due to the demand for miniaturization and cost reduction of electronic equipment, a method of mounting a semiconductor integrated circuit element on a circuit board in a bare chip state as cut out from a semiconductor wafer has been developed, and the quality has been guaranteed. It is desired to supply bare chips at a low price.

In order to perform quality assurance on bare chips, it is desirable to perform burn-in on the electrical characteristics of the semiconductor integrated circuit elements in a wafer state (at a wafer level) in terms of cost reduction. So, for example, NIKKEI MIC
RODEVICES As described in the July 1997 issue, a wafer tray holding a semiconductor wafer on which a plurality of semiconductor integrated circuit elements are formed, and a semiconductor wafer provided to face the semiconductor wafer held on the wafer tray. There has been proposed an inspection method performed by using an inspection apparatus for a semiconductor integrated circuit provided with an inspection substrate having a probe terminal connected to an inspection electrode of the semiconductor integrated circuit element.

Hereinafter, the inspection apparatus and the inspection method of the semiconductor integrated circuit will be described with reference to FIGS. FIG. 6 is an enlarged sectional view of a main part in FIG.

As shown in FIGS. 5 and 6, a large number of test electrodes 2 are provided on the surface of a plurality of semiconductor integrated circuit elements formed on a semiconductor wafer 1, respectively. Is covered with a passivation film 3.

An inspection substrate 4 is provided so as to face the semiconductor wafer 1, and the inspection substrate 4 has a wiring layer 5a.
And a probe sheet 7 made of, for example, a polyimide sheet whose peripheral edge is fixed to the wiring board 5 by a rigid ring 6, and provided at a portion of the probe sheet 7 corresponding to the inspection electrode 2 of the semiconductor wafer 1. Anisotropic conductive rubber that is provided between the probe terminal 8 having the hemispherical shape and the wiring board 5 and the probe sheet 7 and electrically connects one end of the wiring layer 5 a of the wiring board 5 to the probe terminal 8. And a seat 9.

The semiconductor wafer 1 is held by a wafer holding portion 10a of a wafer tray 10.
Around the wafer holding portion 10a, an annular seal member 11 made of an elastic body is provided. An annular concave groove 12 is formed between the wafer holding portion 10 a and the seal member 11 in the wafer tray 10.
Numerals 2 also communicate with each other by a communication passage 13 formed below the wafer holding portion 10a. Wafer tray 10
On one side, a pressure reducing valve 14 is provided, and the pressure reducing valve 14 is connected to a vacuum pump 16 via a pressure reducing supply path 15.

The other end of the wiring layer 5a of the wiring board 5 is
An inspection device 17 that supplies an inspection voltage such as a power supply voltage, a ground voltage, or a signal voltage is connected via the connector 5 b of the wiring board 5.

Hereinafter, an inspection method performed using a wafer cassette including the inspection substrate 4 and the wafer tray 10 will be described.

A wafer tray 10 holding a semiconductor wafer 1 is placed on a movable table (not shown) movable in the horizontal and vertical directions.
After the inspection substrate 4 is placed on the inspection substrate 4, the movable stage is moved in the horizontal direction to align the semiconductor wafer 1 held on the wafer tray 10 with the probe sheet 7 of the inspection substrate 4, and thereafter, The movable stage is moved upward to bring the semiconductor wafer 1 and the probe sheet 7 closer to each other.

Next, when the inside of the depressurizing groove 12 is depressurized by driving the vacuum pump 16, the probe sheet 7 and the tip of the seal member 11 come into contact with each other.
A sealed space 18 is formed by the sealing member 11 and the probe sheet 7. Thereafter, when the inside of the depressurized concave groove 12 is further depressurized to depressurize the sealed space 18, each probe terminal 8 provided on the probe sheet 7 comes into contact with each inspection electrode 2 of the semiconductor wafer 1.

Next, after the connector 5b of the wiring board 5 is connected to the inspection apparatus 17, each of the inspection electrodes 2 on the semiconductor wafer 1 is connected.
In addition to applying a test voltage to the semiconductor integrated circuit device 1 and receiving an output signal from each test electrode 2, the electrical characteristics of each semiconductor integrated circuit element formed on the semiconductor wafer 1 are evaluated.

Incidentally, the alignment step of positioning the semiconductor wafer 1 with respect to the probe sheet 7 is performed as follows.

First, after moving the first CCD camera provided on the inspection substrate 4 side to the recognition position provided on the semiconductor wafer 1, the image of the inspection electrode 2 on the semiconductor wafer 1 is transferred to the first CCD camera. And the wafer tray 10
The second CCD camera provided on the side
After moving to the recognition position provided in the probe sheet 7
The image of the probe terminal 8 provided on the second CCD camera is taken into the second CCD camera.

Next, the movable stage on which the wafer tray 10 is mounted is moved along the horizontal X-axis so that the image captured by the first CCD camera and the image captured by the second CCD camera correspond to each other. In the direction and the Y-axis direction by a predetermined amount.

Next, the movable stage on which the wafer tray 10 is mounted is moved upward to bring the semiconductor wafer 1 and the probe sheet 7 closer to each other.
Is reduced to bring each probe terminal 8 provided on the probe sheet 7 into contact with each inspection electrode 2 of the semiconductor wafer 1.

[0018]

As described above, each probe terminal 8 provided on the probe sheet 7 of the inspection substrate 4 and each inspection electrode of the semiconductor wafer 1 held on the wafer tray 10 as described above. In order for the semiconductor wafer 1 and the probe sheet 7 to come into contact with each other reliably, the accuracy of the alignment between the semiconductor wafer 1 and the probe sheet 7 is very important.

However, according to the conventional alignment method, the image of the inspection electrode 2 of the semiconductor wafer 1 and the probe terminal 8 of the probe sheet 7 which are spaced apart in the vertical direction.
Error occurs between the image of the inspection electrode 2 and the image of the probe sheet 7,
Since the movement amount of the semiconductor wafer is calculated based on the image captured by the CCD camera and the image captured by the second CCD camera, a calculation error occurs in the movement amount, and Reduce pressure and probe sheet 7
When the probe sheet 7 and the semiconductor wafer 1 are brought close to each other, the probe sheet 8 and the semiconductor wafer 1 are displaced, for example, because the probe terminals 8 and the inspection electrode 2 are displaced. There is.

In view of the above, it is an object of the present invention to enable accurate alignment between a probe terminal provided on a probe sheet and an inspection electrode formed on a semiconductor wafer.

[0021]

In order to achieve the above-mentioned object, an alignment apparatus according to the present invention comprises a first device provided on a semiconductor wafer having a plurality of semiconductor integrated circuit elements having test electrodes formed thereon. The present invention is directed to an alignment apparatus for aligning an alignment mark and a second alignment mark provided on a light-transmitting probe sheet having a probe terminal at a position corresponding to an inspection electrode. A through hole at a position corresponding to the second alignment mark, a holding substrate for holding the probe sheet, a vertical moving means for vertically moving the semiconductor wafer, and a horizontal moving means for horizontally moving the semiconductor wafer; Direction moving means, a first alignment mark and a second alignment mark located near each other in a plane An optical device that captures each image through the through hole of the holding substrate; and a first alignment mark and a second alignment mark based on each image of the first alignment mark and the second alignment mark captured by the optical device. The moving means for calculating the moving amount of the horizontal moving means for moving the semiconductor wafer in the horizontal direction and the moving means for moving the semiconductor wafer in the vertical direction are provided.

According to the alignment apparatus of the present invention, an optical device for capturing the images of the first alignment mark and the second alignment mark located near each other in a plane through the through hole of the holding substrate, and the optical device for capturing the images. A moving amount for moving the semiconductor wafer in the horizontal direction and a moving amount in the vertical direction so that the first alignment mark and the second alignment mark overlap each other, based on the images of the first alignment mark and the second alignment mark. Since the calculation means for calculating the amount of movement to be moved is provided, each image of the first alignment mark and the second alignment mark which are located close to each other in a plane can be taken in. It is no longer necessary to measure the relative position with respect to It is possible to capture the first alignment mark and the image of the second alignment mark of the probe sheet body wafer, error is unlikely to occur between the video and the probe sheet image of the semiconductor wafer,
Further, the amount of movement for moving the semiconductor wafer can be calculated based on the images of the semiconductor wafer and the probe sheet taken into the same optical device, so that errors in the calculation of the amount of movement hardly occur.

In order to achieve the above object, an alignment method according to the present invention comprises a first alignment mark provided on a semiconductor wafer on which a plurality of semiconductor integrated circuit elements having inspection electrodes are formed; The present invention is directed to an alignment method for aligning a second alignment mark provided on a light transmissive probe sheet having a probe terminal at a position corresponding to an electrode.
Holding the second alignment mark on a holding substrate having a through hole at a position corresponding to the first alignment mark and the second alignment mark so that the second alignment mark faces the through hole; Arranging the semiconductor wafer so as to be located in the vicinity of the alignment mark in plan view, and the images of the first alignment mark and the second alignment mark located in proximity to each other in plan view A step of taking in the optical device through the through hole, and based on each image of the first alignment mark and the second alignment mark taken in the optical device, so that the first alignment mark and the second alignment mark overlap with each other. Moving the semiconductor wafer in the horizontal and vertical directions.

According to the alignment method of the present invention, the first
After moving the semiconductor wafer so that the first alignment mark is positioned near the second alignment mark, in order to capture the images of the first alignment mark and the second alignment mark, the relative position between the semiconductor wafer and the probe sheet is previously determined. There is no need to measure the position, and the images of the first alignment mark and the second alignment mark located near each other are taken into the optical device. In addition, since the semiconductor wafer is moved based on the images of the semiconductor wafer and the probe sheet taken into the same optical device, an error in the calculation of the movement amount is less likely to occur.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An alignment method according to one embodiment of the present invention will be described below with reference to FIGS.

As in the prior art, as shown in FIGS. 5 and 6, a large number of test electrodes 2 are provided on the surface of a plurality of semiconductor integrated circuit elements formed on a semiconductor wafer 1, respectively. The periphery of each test electrode 2 is covered with a passivation film 3. The inspection board 4 includes a wiring board 5 having a wiring layer 5 a, a light-transmitting probe sheet 7 made of, for example, a polyimide sheet whose peripheral edge is fixed to the wiring board 5 by a rigid ring 6, and a semiconductor in the probe sheet 7. A hemispherical probe terminal 8 provided at a portion of the wafer 1 corresponding to the inspection electrode 2, provided between the wiring board 5 and the probe sheet 7, and one end of a wiring layer 5 a of the wiring board 5 and the probe terminal And a light-transmissive anisotropic conductive rubber sheet 9 for electrically connecting the conductive rubber sheet 8 to the conductive rubber sheet 8.

As shown in FIG. 1, the wafer tray 10 is placed on a Z.theta. Table 21 as a vertical moving means capable of moving in a vertical direction (Z-axis direction) and a tilting method (.theta. Direction). At the same time, the Z · θ table 21 is fixed to an XY table 22 as a horizontal moving means capable of moving in the left-right direction (X-axis direction) and the front-back direction (Y-axis direction). The held semiconductor wafer 1 is movable in the Z-axis direction, the θ-direction, the X-axis direction, and the Y-axis direction.

As shown in FIGS. 1 and 2A and 2B, the wiring board 5 of the inspection board 4 is held by a holding board 23 having, for example, two through holes 23a. Reference numeral 23 is held by a substrate holding means (not shown) provided in the alignment apparatus.

As shown in FIG. 1, the alignment apparatus is provided with, for example, two camera holding arms 26 extending from the apparatus main body 25 toward the respective through holes 23a of the holding substrate 23. At the tip,
CCD cameras 27 as optical devices each having a lens 27a for focusing are fixed.

As shown in FIGS. 2 (b) and 3 (a) and 3 (b), for example, two first
Are formed, and, for example, two second alignment marks 7a are also formed at positions corresponding to the first alignment marks 1a on the periphery of the probe card 7.

As the first alignment mark 1a, a pattern of a semiconductor integrated circuit element formed on the semiconductor wafer 1 can be used, and as the second alignment mark 7a, a pattern on the probe sheet 7 can be used. Although the provided probe terminal 8 can be used, in any case, it is preferable that the first alignment mark 1a and the second alignment mark 7a are formed at substantially corresponding positions. Also, the holding substrate 23
Are formed at positions corresponding to the positions of the first alignment mark 1a and the second alignment mark 7a.

Hereinafter, an alignment method performed using the above-described alignment apparatus will be described.

First, the wiring board 5 of the inspection board 4 is held by the holding board 23 at a position where the second alignment mark 7a of the probe sheet 7 can be recognized by the CCD camera 27 through the through hole 23a of the holding board 23 in advance. Keep it.

Next, as shown in FIG.
The semiconductor wafer 1 is placed on the wafer tray 10 so that the first alignment mark 1a can be recognized by the CCD camera 27 through the through hole 23a of the holding substrate 23. That is, the semiconductor wafer 1 is arranged on the wafer tray 10 such that the first alignment mark 1a and the second alignment mark 7a are located close to each other in a plane. As described above, since the probe sheet 7 and the anisotropic conductive rubber sheet 9 are optically transparent, the first alignment mark 1a of the semiconductor wafer 1 can be recognized by the CCD camera 27 through the through hole 23a of the holding substrate 23. Can be.

Note that the first alignment mark 1a and the second
When the first and second alignment marks 7a are not positioned close to each other in the plane, the XY table 22 is moved in the X-axis direction and the Y-axis direction, respectively. May be located close to each other in a plane.

Next, the semiconductor wafer 1 is connected to the probe sheet 7.
The Z · θ table 21 is moved upward so as to approach in a range where it does not contact the.

Next, first planarly-located first proximity members
After the CCD camera 27 recognizes the alignment mark 1a and the second alignment mark 7a through the through holes 23a of the holding substrate 23, the image of the first alignment mark 1a and the second alignment mark 7a
Capture the video of a.

Next, the amount of movement in the Z-axis direction, the angle in the θ direction, the angle in the θ direction, so that the image of the first alignment mark 1a and the image of the second alignment mark 7a captured by each CCD camera 27 overlap each other. After calculating the amount of movement in the X-axis direction and the amount of movement in the Y-axis direction, the Z · θ table 21 is set so that the image of the first alignment mark 1a and the image of the second alignment mark 7a overlap each other.
The XY table 22 is moved by a predetermined amount in the axial direction and tilted by a predetermined angle in the θ direction.
Move by a predetermined amount in the axial direction.

According to one embodiment of the present invention, after the semiconductor wafer 1 is moved so that the first alignment mark 1a is positioned near the second alignment mark 7b, the first alignment mark 1a and the second Since the image of the alignment mark 7b is captured, it is not necessary to measure the relative position between the semiconductor wafer and the probe sheet in advance.

Further, since the images of the first alignment mark 1a and the second alignment mark 7a located near each other are captured by the same CCD camera 27, the image of the semiconductor wafer 1 and the image of the probe sheet 7 are interposed. Error is less likely to occur.

Furthermore, since the semiconductor wafer 1 is moved based on the image of the semiconductor wafer 1 and the image of the probe sheet 7 captured by the same CCD camera 27, an error in the calculation of the amount of movement hardly occurs.

[0042]

According to the alignment apparatus or the alignment method according to the present invention, it is not necessary to previously measure the relative position between the semiconductor wafer and the probe sheet.
Since the alignment process can be simplified and speeded up, the efficiency of the inspection process for inspecting the electrical characteristics of a plurality of semiconductor integrated circuit elements formed on a semiconductor wafer collectively in a wafer state is improved.

Further, since the image of the semiconductor wafer and the image of the probe sheet are captured by the same optical device, an error between the image of the semiconductor wafer and the image of the probe sheet hardly occurs, and the image is captured by the same optical device. Since the semiconductor wafer is moved on the basis of the images of the semiconductor wafer and the probe sheet, the calculation error of the amount of movement is less likely to occur, so that the inspection electrode and the probe sheet formed on the semiconductor wafer are provided. Positioning with the probe terminal can be performed with high accuracy of, for example, about ± 3 μm.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an alignment apparatus and an alignment method according to an embodiment of the present invention.

FIG. 2A is a plan view of a holding substrate in the alignment apparatus according to one embodiment of the present invention, and FIG. 2B is a cross-sectional view illustrating an alignment method according to one embodiment of the present invention.

FIG. 3A is a plan view of a semiconductor wafer used in an alignment apparatus and an alignment method according to an embodiment of the present invention, and FIG. 3B is used in an alignment apparatus and an alignment method according to an embodiment of the present invention; It is a top view of a probe sheet.

FIG. 4 is a plan view showing one step of an alignment method according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view of an alignment apparatus according to the related art and an inspection apparatus for a semiconductor integrated circuit to which the alignment method is applied according to an embodiment of the present invention.

FIG. 6 is an enlarged sectional view of a main part of an alignment apparatus and an inspection apparatus for a semiconductor integrated circuit which is an object of the alignment method according to the related art and one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a First alignment mark 2 Inspection electrode 3 Passivation film 4 Inspection board 5 Wiring board 5a Wiring layer 5b Connector 6 Rigid ring 7 Probe sheet 7a Second alignment mark 8 Probe terminal 9 Anisotropic conductive rubber sheet DESCRIPTION OF SYMBOLS 10 Wafer tray 10a Wafer holding part 11 Sealing member 12 Concave groove 13 Communication path 14 Pressure reducing valve 15 Pressure reducing supply path 16 Vacuum pump 17 Inspection device 18 Sealed space 21 Z / θ table 22 XY table 23 Holding substrate 23a Through hole 25 Device body 26 Camera holding arm 27 CCD camera 27a Lens

Continued on the front page (72) Inventor Tomoyuki Nakayama 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term (reference) 2G011 AA16 AA21 AB06 AB08 AC06 AC14 AE03 2G032 AA00 AF02 AF04 AL03 4M106 AA01 BA01 BA14 CA70 DD03 DD09 DD10 DD13 DG26 DJ03 DJ04 DJ05 DJ06 DJ07 5F031 CA02 JA04 JA38 JA50 MA33 9A001 BB06 KK31

Claims (2)

[Claims] A first semiconductor integrated circuit device having a plurality of semiconductor integrated circuit devices having inspection electrodes;
An alignment device for aligning a second alignment mark provided on a light-transmitting probe sheet having a probe terminal at a position corresponding to the inspection electrode, wherein the first alignment mark and the second alignment mark are provided. A through hole at a position corresponding to the alignment mark and the second alignment mark, a holding substrate for holding the probe sheet, a vertical moving means for vertically moving the semiconductor wafer, A horizontal moving means for moving in a horizontal direction, an optical device for taking in images of the first alignment mark and the second alignment mark which are positioned close to each other in a plane through a through hole of the holding substrate, and the optical device Each of the first alignment mark and the second alignment mark captured in Based on the,
The horizontal moving means moves the semiconductor wafer in the horizontal direction and the vertical moving means moves the semiconductor wafer in the vertical direction so that the first alignment mark and the second alignment mark overlap. An alignment device comprising: a calculating unit that calculates a moving amount to be moved. 2. A semiconductor device comprising: a first semiconductor wafer having a plurality of semiconductor integrated circuit devices having test electrodes formed thereon;
An alignment method for aligning a second alignment mark provided on a light transmissive probe sheet having a probe terminal at a position corresponding to the inspection electrode, wherein the probe sheet comprises: Holding the second alignment mark on a holding substrate having a through hole at a position corresponding to the first alignment mark and the second alignment mark so that the second alignment mark faces the through hole; and the first alignment mark. Arranging the semiconductor wafer so that the first alignment mark and the second alignment mark are located near each other in a plane with respect to the second alignment mark. Capturing each image into an optical device through a through hole in the holding substrate; Based on the images of the first alignment mark and the second alignment mark inserted,
Moving the semiconductor wafer in the horizontal and vertical directions so that the first alignment mark and the second alignment mark overlap with each other.