1379369 31570pifl 爲第98118028號中文說明書無劃線修正本 修正日期101年8月1〇日 六、發明說明： 【發明所屬之技術領域】 晶片進行測試的測試系統 【先前技術】 本發明是有關於-種對半導體晶月進 統。特別是關於-種對半導體晶圓上所的j = 2糸 作為對在半導體晶圓上所形成的多個 測試的f置:已知有姻探針卡的裝置，該探針 圓上的多個谭塾(pad)電極統-接觸（例如 1)。在該農置中，是在使探針卡和被測試曰圓二=文獻 狀態下投人至檢查裳置中，進行高溫中的^查。-附的 獻1〕曰本專利早期公開之特開2〇〇6_ 圓及後:r試晶 =吸r探針卡上。亦即=== 針卡也必須從檢查裝置搬出。因此，在下—職中，必= 圓及探針卡間的對準和檢查裝置内的探針卡： 對準以者進仃調整。因此的效率會下 【發明内容】 因此’本發明的目的是提供一種能夠解決上述課題的 測試糸統。本發暇#㈣請糊麵_立韻記述= 特徵的組合輯成。而且，從屬魏定本發 的I艚彻早。 1379369 31570pifl 爲第98118028號中文說明書無劃線修正本 修正曰期101年8月10日 為了解決上述課題，本發明的第1形態提供一種測試 系統’為一種對半導體晶圓上所形成的多個半導體晶片進 行測試之測試系統，包括：反應室，其搬運半導體晶圓； 測試用晶圓，其固定在反應室内，設置有與多個半導體晶 片的焊墊統一進行電氣連接的多個凸塊；晶圓載台，其= 由在反應室内載置半導體晶圓並進行移動，而使半導體^ 圓移動到與測試用晶圓對向的位置上；測定部，其對晶^ •載台設置在規定的位置上，當為了將半導體晶圓載置在晶 圓載台上而使半導體晶圓對晶圓載台進行移動時，藉由掃 描半導體晶圓的表面的至少一部分，而偵測半導體晶圓上 所設置的對準標誌的位置；以及位置控制部， 其根據測定 部所測定的對準標誌的位置，對晶圓載台上所載置的半導 體晶圓的位置進行調整。 本發明的第2形態提供一侧試系統，為一種對半 體晶圓上所形成的多個半導體晶片進行測試之測試系统， 包括：反應室，其搬運半導體晶圓；測試用晶圓，其固 •在反應室内，設置有與多個半導體晶片的焊魏m1379369 31570pifl is the Chinese manual of No. 98118028. There is no slash correction. This revision date is August 1st, 2011. Description of the invention: [Technical field of invention] Test system for testing wafers [Prior Art] The present invention is related to - Kinds of semiconductor crystals. In particular, regarding j = 2 半导体 on a semiconductor wafer as a set of f for a plurality of tests formed on a semiconductor wafer: a device having a marriage probe card is known, and the probe has a large number of circles A pad electrode system-contact (for example, 1). In this farm setting, the probe card and the test probe are placed in the test state, and the test is performed in the high temperature. - Attached 1] 曰 This patent discloses the special opening 2〇〇6_ circle and rear: r test crystal = suction r probe card. That is, the === needle card must also be removed from the inspection device. Therefore, in the next job, you must = the alignment between the circle and the probe card and the probe card in the inspection device: Align the adjustment. Therefore, the efficiency is lowered. [Explanation] Therefore, an object of the present invention is to provide a test system capable of solving the above problems.本发暇#(四)Please paste _ Li Yun description = combination of features. Moreover, I was subordinate to Wei Dingben. 1379369 31570pifl is the Chinese manual of No. 98118028. There is no slash correction. This amendment is in addition to the above-mentioned problem. In order to solve the above problems, the first aspect of the present invention provides a test system which is a plurality of pairs formed on a semiconductor wafer. A test system for testing a semiconductor wafer, comprising: a reaction chamber for carrying a semiconductor wafer; and a test wafer fixed in the reaction chamber and provided with a plurality of bumps electrically connected to the pads of the plurality of semiconductor wafers; In the wafer stage, the semiconductor wafer is placed and moved in the reaction chamber to move the semiconductor wafer to a position facing the test wafer; and the measurement unit is provided on the crystal table. Positioning, when the semiconductor wafer is moved to the wafer stage in order to mount the semiconductor wafer on the wafer stage, the semiconductor wafer is detected by scanning at least a portion of the surface of the semiconductor wafer a position of the alignment mark; and a position control unit for the semiconductor guided on the wafer stage according to the position of the alignment mark measured by the measuring unit Position of the wafer can be adjusted. According to a second aspect of the present invention, there is provided a test system for testing a plurality of semiconductor wafers formed on a semiconductor wafer, comprising: a reaction chamber for transporting a semiconductor wafer; and a test wafer. Solid in the reaction chamber, set with a plurality of semiconductor wafers
日-日圓的位置進行調整。 5 1379369 31570ρϊΠ 爲第9811_號中文說明書無劃線修正本 修正日期101年8月1〇曰 另外，上述發明的概要並未列舉發明的必要特徵的全 部’它們的特徵群的子集(sub-combination)也可又形成發 明。 【實施方式】 以下，通過發明的實施形態來對本發明進行說明，但 以下的實施形態並不對關於申請專利範圍的發明進行限 定。而且，實施形態中所說明之特徵的組合的全部也未必 是發明的解決方法所必須者。 圖1所示為關於一實施形態的測試系統400的概要。 測試系統400對半導體晶圓300上所形成的多個半導體晶 片進行測試。而且，測試系統4〇〇可並列地對多個半導體 晶圓300進行測試。測試系統400具有控制裝置1〇、多個 反應至20、搬運部4〇及晶圓盒(cassette)6〇。 控制裝置10控制該測試系統400。例如，控制裝置1〇 可控制反應室20、搬運部40及晶圓盒6〇。反應室20依次 接收應測試的半導體晶圓300,並在反應室20的内部對半 導體晶圓300進行測試。各個反應室2〇可獨立地測試半導 體晶圓300。亦即，各個反應室2〇可不與其它的反應室2〇 同步地，對半導體晶圓300進行測試。 晶圓盒60存儲多個半導體晶圓300。搬運部40將應 測5式的多個半導體晶圓3〇〇依次搬運到各個反應室2〇(>例 如’搬運部40將晶圓盒60所存儲的各個半導體晶圓300， 搬運到空閒的某個反應室2〇内。而且，搬運部4〇可將測 5式結束的半導體晶圓300,從反應室20搬出並存儲在晶圓 31570pifl 修正曰期101年8月10曰 爲第98118028號中文說明書無劃線修正本 盒60中。 圖2為測試系統400的測試概要的說明圖。測試系統 400利用測試用晶圓100來對半導體晶圓3〇〇的各個半導 體晶片310進行測試。測試用晶圓1〇〇預先設置在圖i所 示的各個反應室20内。 測試用晶圓100可由與測試對象的半導體晶圓3〇〇相 同的半導體材料形成。例如，半導體晶圓可為圓盤狀 的半導體晶圓。更具體地說，半導體晶圓3〇〇可為矽、化 合物半導體等其它的半導體晶圓。 而且，測試用晶圓100可與測試對象的半導體晶圓3〇〇 具有大致相同的直徑。半導體晶圓3〇〇在反應室2〇内與測 試用晶圓100所對向的規定的位置對準。然後，藉由&半 導體晶1]進行義以與賴用晶UJ⑽4合，從而使測試 用晶圓100的多個晶圓侧連接焊墊J12和多個半導體晶片 310的檢查用的焊墊統一地進行電氣連接。 △例如，半導體晶目300在反應室2〇内被載置在晶圓載 台上，並利用晶圓載台而移動到與測試用晶圓⑽對向的 位置上。測試用晶圓100及晶圓載台的相對位置預先進行 ，整。因此，測試系統400可藉由將半導體晶圓獅載置 在晶圓載台表面的規定的位置上，而對測試用晶圓漏來 將半導體晶圓300與規定的位置進行對準。 在測試用晶圓100的與半導體晶圓3〇〇對向的面上， 可形成與半導體晶片31〇的各個料姆應㈣個焊塾。 另外，測試用晶圓100及半導體晶圓3〇〇可藉由直接接觸 1379369 31570pifl 修正日期101年8月10日 爲第98118028號中文說明書無劃線修正# 而進行電氣連接，而且，也可利用靜電結合、感應接合等 非接觸的結合而進行電氣連接。而且，測試用晶圓1〇〇及 半導體晶圓300也可經由光傳送路而收發信號。 測試用晶圓1〇〇可藉由與測試對象的半導體晶圓3〇〇 進行電氣連接，而在控制裝置1〇和半導體晶圓3〇〇之間傳 送信號。例如，半導體晶圓300可將控制裝置1〇所生成的 測試信號，供給到半導體晶圓300的各個半導體晶片31〇。 而且，測試用晶1〇〇可將各個半導體晶片31〇所輸出的信 號傳送到控制裝置10。 而且，測試用晶圓1〇〇可具有與多個半導體晶片310 相對應的多個電路部。例如，測試用晶圓可與多 個半導體晶片310 —對一對應地而具有多個電路部11()。 各個電路部110可生成供給到對應的半導體晶片31〇的信 號，而且’也可處理對應的半導體晶片31〇所輪出的信號二 各個電路部11〇可獨立地測試對應的半導體晶片31〇。在 逆種情況下，控制装置10可對各個電路部11〇供給電源電 力及控制信號等。 圖3所示為將半導體晶圓3⑻與晶圓載台41〇的對應 的位置進行對準之方法的-個例子。圖3所示為晶圓載台 410及半導體晶圓3〇〇的上面圖。本例的測試系統4⑻具 有測定部406，該敎部條預先確定對晶圓載台41〇的 相對位置。而且，在半導體晶圓細的預先確定的位置上 形成了對準標誌226。 測定部406在為了將半導體晶圓3〇〇載置在晶圓載台 1379369 31570pifl 修正日期101年8月1〇日 爲第981丨臟獅麵鴨罐線修正本 ^10 並使半導體晶圓300對晶圓載台41〇進行移動時， 藉，掃為半導體晶圓300的表面的至少一部分，從而偵 在半導體晶圓3GG上所設置的對準標誌的位置。例如，測 定部406能以拍攝半導體晶圓300所通過的區域的預先確 定的固定掃描位置之形態而設置，並藉由使半導體晶圓 300通過该掃描位置，從而掃描該半導體晶圓3㈨的表 的至少一部分。 两 例如，在半導體晶圓3〇〇令，如在與晶圓载台4ι〇對 向的面上形成對準標誌226，則測定部4〇6可設置在晶圓 載台410上，並對通過上方的半導體晶圓3〇〇進行攝像。 而且，在半導體晶圓300中，如在與晶圓載台41〇對向的 面的背面上形成對準標誌226，則測定部4〇6可設置在晶 圓載台410的上方，並對通過下方的半導體晶目3〇〇進= 攝像。 …另外，搬運部40對保持晶圓300並移動的處理機的對 半導體晶圓300之相對位置預先進行控制。因此，在半導 體晶圓300被搬運到反應室2〇内之前，半導體晶圓3〇〇 和日曰圓載台410的相對位置是大致進行調整，但測試系統 4〇〇在室内20内，利用測定部406對半導體晶圓3〇〇的位 置進行微調整。 测定部406設置在與對準標誌226的位置相對應的位 置上較佳。對測試系統400可預先賦予半導體晶圓3〇〇的 對準標誌226的位置。如上所述，半導體晶圓3〇〇和晶圓 載α 410的相對位置，可在半導體晶圓3〇〇被搬運到反應 9 1379369 31570pifl 修正曰期101年8月10曰 爲第98118028號中文說明書無劃線修正本 室20内之前大致地進行調整。 因此’如圖3所不，測定部4〇6可使對半導體晶圓3〇〇 的行進方向（以下稱作γ方向）成垂直之方向（以下稱作 X方向）上的攝像範圍，設定得較半導體晶圓·的直徑 還小。例如’測定部406的X方向上的拍攝範圍為對準標 誌、226的2〜3倍左右。測定部4〇6為了可偵測X方向上 的對準標諸226的位置，而具有沿著X方向按照規定的間 距(pitch)排列的多個攝像元件。 而且，測疋部406的X方向上的位置可變更地設置。 測試系統傷可根據預先所賦予的對準標就22 6的位置數 據，而變更測定部406的X方向上的位置。 而且測疋。卩406在X方向的軸上於不同的位置設置 有多個。在這種情況下，可债測多個對準標誌226的位置， 所以能夠精度更好地偵測半導體晶圓3〇〇的位置。 圖4所示為測定部406進行掃描之圖像的一部分。如 上所述，測定部406沿著x方向具有多個攝像元件4〇7， 所以可以與攝像元件407的間距相稱的解析度，偵測X方 ^的對準標諸226的位置。攝像元件407的間距較對準 標誌226的X方向上的寬度小時較佳。而且，攝像元件407 的間距較解誤差的容許範圍小較佳，其巾， =範圍是依據半導體晶圓_及測試用晶圓⑽的線端 ^度=確定°测試系統_從各個測定部406所拍攝的圖 像，偵測各個對準標誌220的X方向的位置。 而且，測試系統400的位置控制部可根據各個测定部 1379369 31570pifl 爲第98118028號中文說明書無劃線 修正日期10丨年8月丨〇曰 時的時序，來計算各 〜226的Y方向上的位置。例如， 羋心 定部406 _對準標諸226後，個测 上，來制將半導體晶請載圓载台410 對準標誌、226的γ方向位置。在㈣載台4U)上後的 而且’測試系、统400的位置控制部可根 法所偵測的各個對準標结226的乂方向的位置及 = 位置’來計算半導體晶圓3⑻的旋轉量。所說的 / 圓300的旋轉量’是表示在與晶圓载台平行的曰日 +導體晶圓300以中心為軸’從正規的位置進行 量。 例如，測試系統400的位置控制 ==的位置和預先所賦予的對準標 疋轉角。該旋轉角可求取χ方向及Υ方向上的、 對準U6的偵測位置與對準標諸226的正規位 =，及從半導體晶圓300的中心到對準標諸226為止的距 對測試請彻的位置控制部，可預先賦科導體曰 圓300的中心和對準標誌226的距離。 曰曰 測試系、统400的位置控制部可根據利用上述方法所偵 2對準標諸m的X方向上的位置、γ方向上的位置及 =轉量’來控制晶圓載台彻。晶圓載台410具有在載置 半導體晶圓300的狀態下’可對χ方向、γ方向及旋轉量 ^調整之水平載台。而且’測試系統400的位置控制部 可猎由根據測定部406所偵測的對準標誌226的位置以控 11 1379369 31570pifl 爲第98118028號中文說明書無劃線修正本 修正日期101年8月10日 制水平載台，而調整晶圓載台410所載置的半導體晶圓300 的X方向、Y方向上的位置及旋轉量。 圖5所示為反應室20的内部構造的一個例子。依次搬 運測試對象的半導體晶圓300至反應室20,並與反應室20 内所固定的測試用晶圓100進行電氣連接。在反應室20 的内部設置有測試用晶圓1〇〇、性能板4〇4、母板4〇2、晶 圓托架(tray)408、晶圓載台410、引導部420、載台支持部 418、測定部406及位置控制部450。 測試用晶圓1〇〇在反應室2〇内被固定。在本例中，測 試用晶圓100被固定在反應室2〇内的性能板4〇4上。性能 板404可為例如形成有配線的印刷基板。而且，性能板4〇4 可固定在反應室20内的母板402上。母板402經由性能板 404而在控制裝置10和測試用晶圓1〇〇之間傳送信號。如 上所述，在測試用晶圓100的與半導體晶圓3〇〇對向的面 上’設置具有多個凸塊(brnnp)的薄膜。測試用晶圓1〇〇利 用該多個凸塊，而與半導體晶圓3〇〇上所形成的多個半導 體晶圓300的焊墊統一地進行電氣連接。 、明圓载台在反應室20内，載置半導體晶圓3〇〇 ，使其移動。在本例中，半導體晶圓3⑻利用吸附等而固 定在晶圓托架408上，且晶圓載台410載置晶圓托架4〇8。 而且，晶圓载台410經由載台支持部418而與引導部42〇 連接’並沿著引導部420而移動。 例如’引導部420使晶圓載台410，在從搬運部4〇接 收半導體晶圓300的接收位置A、和與測試用晶圓1〇〇對 12 31570pifl 修正日期101年8月10日 爲第98118028號中娜牖無®線修正本 4°20 ^^、位置B之間’按照規定的路徑進行移動。引導部 曰^沿著該規定的路徑而設置的軌道。 ^圓載台41G移動到與測試用晶圓動對向的規定位 加導體晶圓沿著垂直方向進行移動並與測 ^jux)電氣連接。晶圓載台·具有水平載台412 及垂直载台416。 平載口 412載置晶圓托架樣，並對半導體晶圓細 的表面和水平面内的半導體晶圓遍的位置進行調整。水 412對該面内的χ方向及¥方向的半導體晶圓獅 以及該面内的半導體晶圓3〇〇的旋轉量進行調整。 藉此’可對半導體晶圓300的位置進行調整，以使半導體 晶圓300的各焊墊與測試用晶圓1〇〇的各焊墊進行電氣連 接0 ” 垂直載台416載置水平載台412，並對水平載台412 的垂直方向的位置進行控制。例如，垂直载台416可藉由 在與測試用晶圓1〇㈣向的位置上，使載置著半導體晶圓 300之狀態的水平載台412可與測試用晶圓1〇〇接近，從 而將半導體晶圓300及測試用晶圓100進行電氣連接 且，垂繼416可在使半導__對==1〇而〇 接近到規定的距離之後，將半導體晶圓3〇〇和測試用晶圓 100間的空間進行減壓，從而將半導體晶圓3〇〇和測試用 晶圓100電氣連接。而且，可在垂直載台416上固定著載 台支持部418。 位置控制部450如圖4所關聯說明的那樣，根據測定 U/9369 31570pifl 修正日期101年8月丨〇日 爲第981麵8獅文 :?6所拍攝的圖像，對晶圓载台410的位置進行控制。 =控制部450藉由控制水平載台4 體晶圓300的位罟推 > 袖杜 ,^ 夏而對+導 墊配置輕、㈣ 以使半導體晶® 的各烊 塾置在與測相晶圓⑽的各凸塊對應的位置上。 上，晶圓位置偵測部42戰在晶圓載台_ h、M用阳圓100的位置預先進行測定。例如 =^^部422可預先偵測對規定的位置B上所配 的曰曰圓载〇 410的、測試用晶圓1〇〇的 面内的相對位置。水平载台412由於水平 變動，所卿如圓㈣騎422設置;^直位載置台= 上佳 半二3,450為了精度良好地使測試用晶圓⑽及 +導體日日回300的終端進行連接’可還根據測 =測部422所測定的測試用晶圓的位置二 平載台412。 +役f」水 利用這種構成，可調整半導體晶圓 '。。的位置，能夠將半導體二=::= ==多個終端這行電氣連接。而且，本例的= 曰曰回的位置疋固定在反應室2〇 Θ，所以，測試用 ，置偵測部422在更接半導體晶圓3G0時，可不對二 ，圓100的位置進行測定。測試用晶圓位置债測部^在 ::規定期間，對測朗晶圓⑽的位置進行测定即可。 因此，可效率良好地對多個半導體晶圓3〇〇進行測試。 在以上的說明中，測定部406是在為了使半導體晶圓 1379369 31570pifl 修正曰期101年8月1〇日 爲第98118028號中文說明書無劃線修正本 3〇〇載置於晶圓载台410上而進行移動期間，伯 晶圓300的對準標言志226的位置。在另外的例子中，測定 部406也可在將半導體晶圓3〇〇載置在晶圓載台上， 位Γ期間’對半導體 :目，—加舰/ 的置進行偵測。在這種情況下， Z、1疋。P没置在晶圓載台410的移動路徑上，並對 一的=:t所載置之半導體晶圓的表面的至少 226=::r:::期:;偵測對额 斜贴細f 作马個例子，本例的測定部406 的測侧相圖:=::: 攄測定部406所偵測的圖像，來控制水平載:41。2根 標認=二在偵測對準 準標諸226的Y方向上的位置。從：『二 置二= 方向上的位置。 〃 了偵測對準標誌、226的丫 位置控制部450根據像這樣翻到的各個對準標諸 15 31570pifl 爲第98118028號中文說明書無劃線修正本 修正日期101年8月10日 226的X方向及γ方向上的位置， 向及Y方向的位置及旋轉量進行調整。這t 載台410的移動…貞測對準標諸226的=j 方向的位置，並對半導體晶圓3〇〇的位 向及 圖7所示為在晶圓載台410進行移動期严 測 才示諸226之另-例子的說明圖。本例的測 働 -個測定部概。而且，即使在關於圖3所說二 圓載台彻搬運半導體晶圓___ 2 ^ =下，也可同樣地利用一個測定部4〇6而偵；；= 在這種情況下，可在半導體晶圓細上，如圖 於X方向的軸上的大致相同的位置，設置多個卜 226。測定部406以可侧這些對準標總a㈣位 = =配置著。這樣的構成，也可_半導體晶圓3〇〇= X方向及Υ方向上的位置偏離及旋轉量。 另外’圖3至圖7中，所示為作為一個例子的矩形對 準杯達' 226，但對準標誌226的形狀並不限定於該形狀。 對準標誌226可具有十字等規定的形狀。而且，對準標誌 226也可具有沿著規定的形狀而排列的多個焊墊。 圖8所示為測試用晶圓1〇〇的剖面圖的—個例子。本 例的測試用晶圓100如上所述，在控制裝置1〇及半導體晶 圓300之間傳送信號。測試用晶圓100具有晶圓側連接= 墊112、裝置侧連接焊墊114、貫通孔116、中間焊墊 及配線117。 3l570pifl 修正日期101年8月1〇日 爲第98118028號中文說明書無劃線修正本 測試用晶圓100如圖8所示，具有晶圓連接面1〇2及 在晶圓連接面102的背面上所形成的裝置連接面·。晶 圓連接面102可以是指與半導體晶圓3〇〇對向的面。而且， 裝置連接面104可以是指與控制裝置1〇電翁拿 多個晶圓侧連接焊墊112形成在測試用晶圓1〇〇的晶 圓連接面102上。而且，晶圓側連接焊墊112對各個半導 體晶片310，至少在每一個上進行設置。例如，晶圓側連 ，焊墊112可對各個半導體晶片31〇的各個輸出入終端的 母一個進行設置。亦即，在各個半導體晶片31〇具有多個 輸出入終端的情況下，晶圓側連接焊墊112可對各個半導 體晶片310的每個設置多個。 各個晶圓侧連接焊墊112與半導體晶圓3〇〇的各個輸 出入終端以相同的間隔而設置，並與對應的半導體晶片 31〇的輸出入終端進行電氣連接。另外，所說的電氣連接， 可以是指在2個構件間能夠傳送電氣信號的狀態。例如， 晶圓側連接焊墊U2及半導體晶片31〇的輸出入終端可藉 由直接接觸或經由其它導體而間接地接觸，從而進行電^ 連接。本例的晶圓侧連接焊墊112經由後面的圖1〇所述的 ，膜，與半導體晶片31〇的輸出入終端進行電氣連接。在 薄膜的與各焊墊相對應的位置上形成有凸塊。 而且’晶圓侧連接焊墊112及半導體晶片31〇的輸出 入終端，也可像電容量結合（靜電結合）或感應結合7磁 結合）等那樣’以非接觸狀態進行電氣連接。而且，曰The position of the day-yen is adjusted. 5 1379369 31570ρϊΠ is the 9811_ Chinese manual without a slash correction. This revision date is August 1st, 2011. In addition, the summary of the above invention does not enumerate all of the essential features of the invention's subset of their characteristic groups (sub- Combination) can also form an invention. [Embodiment] Hereinafter, the present invention will be described by way of embodiments of the invention, but the following embodiments are not intended to limit the invention in the claims. Further, all of the combinations of the features described in the embodiments are not necessarily required for the solution of the invention. FIG. 1 shows an overview of a test system 400 in accordance with an embodiment. Test system 400 tests a plurality of semiconductor wafers formed on semiconductor wafer 300. Moreover, the test system 4 can test a plurality of semiconductor wafers 300 side by side. The test system 400 has a control unit 1, a plurality of reactions 20, a transport unit 4, and a cassette 6 〇. Control device 10 controls the test system 400. For example, the control unit 1 can control the reaction chamber 20, the transport unit 40, and the wafer cassette 6A. The reaction chamber 20 sequentially receives the semiconductor wafer 300 to be tested and tests the semiconductor wafer 300 inside the reaction chamber 20. Each of the reaction chambers 2 can independently test the semiconductor wafer 300. That is, each of the reaction chambers 2 can test the semiconductor wafer 300 without synchronizing with other reaction chambers. The wafer cassette 60 stores a plurality of semiconductor wafers 300. The transport unit 40 sequentially transports a plurality of semiconductor wafers 3 to be tested to the respective reaction chambers 2 (> for example, the transport unit 40 transports the respective semiconductor wafers 300 stored in the wafer cassette 60 to the idle state. In one of the reaction chambers 2, the transport unit 4 can carry out the semiconductor wafer 300 whose type 5 is finished, and carry it out from the reaction chamber 20 and store it on the wafer 31570pifl. The revised period is August 10, 2010. The Chinese manual has no scribe line correction in the case 60. Fig. 2 is an explanatory diagram of a test outline of the test system 400. The test system 400 tests the respective semiconductor wafers 310 of the semiconductor wafer 3 using the test wafer 100. The test wafer 1 is previously disposed in each of the reaction chambers 20 shown in Fig. 1. The test wafer 100 may be formed of the same semiconductor material as the semiconductor wafer 3测试 of the test object. For example, the semiconductor wafer may be A disk-shaped semiconductor wafer. More specifically, the semiconductor wafer 3 can be another semiconductor wafer such as germanium or a compound semiconductor. Further, the test wafer 100 can be connected to the semiconductor wafer of the test object. Have roughly The same diameter, the semiconductor wafer 3 is aligned in a predetermined position opposite to the test wafer 100 in the reaction chamber 2, and then, by & semiconductor crystal 1], and the UJ (10) 4 Thereby, the plurality of wafer side connection pads J12 of the test wafer 100 and the pads for inspection of the plurality of semiconductor wafers 310 are collectively electrically connected. Δ For example, the semiconductor crystal 300 is in the reaction chamber 2 It is placed on the wafer stage and moved to the position facing the test wafer (10) by the wafer stage. The relative positions of the test wafer 100 and the wafer stage are pre-processed. Therefore, the test system 400 can be used to align the semiconductor wafer 300 with a predetermined position by placing the semiconductor wafer lion on a predetermined position on the surface of the wafer stage. The test wafer 100 is aligned with the predetermined position. On the surface opposite to the semiconductor wafer 3, four (four) solder pads can be formed with the semiconductor wafer 31. In addition, the test wafer 100 and the semiconductor wafer 3 can be directly contacted by 1379369. 31570pifl Revised date August 10, 101 The Chinese manual No. 98118028 is electrically connected without a slash correction #, and may be electrically connected by non-contact bonding such as electrostatic bonding or induction bonding. Further, the test wafer 1 and the semiconductor wafer 300 are also electrically connected. The signal can be transmitted and received via the optical transmission path. The test wafer 1 can be electrically connected between the control device 1 and the semiconductor wafer 3 by electrically connecting to the semiconductor wafer 3测试 of the test object. For example, the semiconductor wafer 300 can supply the test signals generated by the control device 1 to the respective semiconductor wafers 31 of the semiconductor wafer 300. Further, the test crystals can output the respective semiconductor wafers 31. The signal is transmitted to the control device 10. Further, the test wafer 1 may have a plurality of circuit portions corresponding to the plurality of semiconductor wafers 310. For example, the test wafer may have a plurality of circuit portions 11() in a one-to-one correspondence with the plurality of semiconductor wafers 310. Each of the circuit sections 110 can generate a signal supplied to the corresponding semiconductor wafer 31, and can also process the signal of the corresponding semiconductor wafer 31. The respective circuit sections 11 can independently test the corresponding semiconductor wafer 31A. In the case of reverse seeding, the control device 10 can supply power supply voltage, control signals, and the like to the respective circuit sections 11A. Fig. 3 shows an example of a method of aligning the semiconductor wafer 3 (8) with the corresponding position of the wafer stage 41A. 3 is a top view of the wafer stage 410 and the semiconductor wafer 3A. The test system 4 (8) of this example has a measuring unit 406 which predetermines the relative position to the wafer stage 41A. Moreover, an alignment mark 226 is formed at a predetermined position of the semiconductor wafer. The measuring unit 406 corrects the semiconductor wafer 300 by placing the semiconductor wafer 3 on the wafer stage 1379369 31570pifl, the date of correction, August 1st, the first day of the 981th. When the wafer stage 41 is moved, it is swept to at least a portion of the surface of the semiconductor wafer 300 to detect the position of the alignment mark provided on the semiconductor wafer 3GG. For example, the measuring unit 406 can be provided in a form of photographing a predetermined fixed scanning position of a region through which the semiconductor wafer 300 passes, and scanning the semiconductor wafer 3 (9) by passing the semiconductor wafer 300 through the scanning position. At least part of it. For example, in the semiconductor wafer 3, if the alignment mark 226 is formed on the surface opposite to the wafer stage 4, the measuring unit 4〇6 may be disposed on the wafer stage 410 and passed through The upper semiconductor wafer 3 is imaged. Further, in the semiconductor wafer 300, if the alignment mark 226 is formed on the back surface of the surface facing the wafer stage 41, the measurement portion 4〇6 can be disposed above the wafer stage 410 and passed under the wafer stage 410. The semiconductor crystal lens is 3 = = camera. Further, the transport unit 40 controls the relative position of the semiconductor wafer 300 of the processor that holds the wafer 300 and moves in advance. Therefore, before the semiconductor wafer 300 is transported into the reaction chamber 2, the relative positions of the semiconductor wafer 3 and the sunroof stage 410 are substantially adjusted, but the test system 4 is used in the room 20, and the measurement is performed. The portion 406 finely adjusts the position of the semiconductor wafer 3 turns. The measuring unit 406 is preferably provided at a position corresponding to the position of the alignment mark 226. The position of the alignment mark 226 of the semiconductor wafer 3 可 can be given to the test system 400 in advance. As described above, the relative position of the semiconductor wafer 3〇〇 and the wafer-loaded α 410 can be transported to the reaction in the semiconductor wafer 3 9 9 1379369 31570pifl 曰 101 101 101 101 101 101 101 101 101 981 981 981 981 981 981 981 981 981 981 The scribing correction is roughly adjusted before the inside of the room 20. Therefore, as shown in FIG. 3, the measurement unit 4〇6 can set the imaging range in the direction in which the traveling direction of the semiconductor wafer 3 (hereinafter referred to as the γ direction) is perpendicular (hereinafter referred to as the X direction). It is smaller than the diameter of the semiconductor wafer. For example, the imaging range in the X direction of the measuring unit 406 is about 2 to 3 times the alignment mark 226. The measuring unit 4〇6 has a plurality of imaging elements arranged at a predetermined pitch along the X direction in order to detect the position of the alignment target 226 in the X direction. Further, the position of the measuring unit 406 in the X direction is changeably provided. The test system injury can change the position of the measuring unit 406 in the X direction based on the position data of the alignment target 22 6 given in advance. And test. The 卩406 is provided at a plurality of positions on the axis in the X direction. In this case, the positions of the plurality of alignment marks 226 can be measured, so that the position of the semiconductor wafer 3 can be accurately detected. FIG. 4 shows a part of an image scanned by the measuring unit 406. As described above, since the measuring unit 406 has the plurality of imaging elements 4〇7 along the x direction, the position of the alignment mark 226 of the X square can be detected with the resolution proportional to the pitch of the imaging element 407. The pitch of the image pickup element 407 is preferably smaller than the width of the alignment mark 226 in the X direction. Moreover, the pitch of the imaging element 407 is preferably smaller than the allowable range of the solution error, and the range of the towel is = according to the line length of the semiconductor wafer_ and the test wafer (10) = determination ° test system - from each measurement section The image taken by 406 detects the position of each alignment mark 220 in the X direction. Further, the position control unit of the test system 400 can calculate the position in the Y direction of each of the 226 according to the timing of the time when the measurement unit 1379369 31570pifl is the Chinese manual No. 98118829 and the scribe line correction date is 10:00 August. . For example, after the alignment of the target 406 _ _ _ 226, the semiconductor wafer carrier stage 410 is aligned with the gamma-direction position of the mark 226. The rotation of the semiconductor wafer 3 (8) is calculated after the (four) stage 4U) and the position control unit of the test system 400 can detect the position of the alignment marks 226 and the position of the respective alignment marks 226. the amount. The amount of rotation of the /circle 300 is shown to be from a regular position on the next day in parallel with the wafer stage + the conductor wafer 300 is centered on the axis '. For example, the position of the test system 400 is controlled == the position and the pre-assigned alignment angle. The rotation angle can be determined in the χ direction and the Υ direction, the detection position of the alignment U6 and the normal position of the alignment mark 226, and the distance from the center of the semiconductor wafer 300 to the alignment target 226. The position control unit of the test can be pre-assigned to the distance between the center of the conductor circle 300 and the alignment mark 226. The position control unit of the test system 400 can control the wafer stage according to the position in the X direction, the position in the γ direction, and the amount of rotation ′ of the mark m in accordance with the above method. The wafer stage 410 has a horizontal stage that can be adjusted in the χ direction, the γ direction, and the rotation amount in a state in which the semiconductor wafer 300 is placed. Moreover, the position control unit of the test system 400 can be hunted by the position of the alignment mark 226 detected by the measuring unit 406 to control 11 1379369 31570pifl as the Chinese manual No. 98118018 without a slash correction. The correction date is August 10, 101. The horizontal stage is adjusted to adjust the position and the amount of rotation of the semiconductor wafer 300 mounted on the wafer stage 410 in the X direction and the Y direction. FIG. 5 shows an example of the internal structure of the reaction chamber 20. The semiconductor wafer 300 to be tested is sequentially transferred to the reaction chamber 20, and electrically connected to the test wafer 100 fixed in the reaction chamber 20. Inside the reaction chamber 20, a test wafer 1A, a performance board 4〇4, a mother board 4〇2, a wafer tray 408, a wafer stage 410, a guide unit 420, and a stage support unit are provided. 418. Measurement unit 406 and position control unit 450. The test wafer 1 is fixed in the reaction chamber 2〇. In this example, test wafer 100 is attached to performance plate 4〇4 in reaction chamber 2〇. The performance board 404 can be, for example, a printed substrate on which wiring is formed. Moreover, the performance board 4〇4 can be fixed to the motherboard 402 in the reaction chamber 20. The motherboard 402 transmits signals between the control device 10 and the test wafer 1 via the performance board 404. As described above, a film having a plurality of bumps (brnnp) is provided on the surface of the test wafer 100 opposite to the semiconductor wafer 3'. The test wafer 1 utilizes the plurality of bumps to electrically connect the pads of the plurality of semiconductor wafers 300 formed on the semiconductor wafer 3 to each other. The wafer stage is placed in the reaction chamber 20, and the semiconductor wafer 3 is placed and moved. In this example, the semiconductor wafer 3 (8) is fixed to the wafer carrier 408 by suction or the like, and the wafer stage 410 is placed on the wafer carrier 4'8. Further, the wafer stage 410 is connected to the guide portion 42 via the stage support portion 418 and moves along the guide portion 420. For example, the guiding unit 420 causes the wafer stage 410 to receive the receiving position A of the semiconductor wafer 300 from the conveying unit 4, and the test wafer 1 to 12, 31,570 pifl, and the date of correction, August 10, 2011, as the 9811808 No. Naka no ® line correction 4°20 ^^, position B 'moves according to the specified path. Guide section 曰^ A track set along the specified path. The circular stage 41G is moved to a predetermined position opposite to the test wafer. The conductor wafer is moved in the vertical direction and electrically connected to the test. The wafer stage has a horizontal stage 412 and a vertical stage 416. The flat carrier port 412 mounts the wafer carrier and adjusts the position of the semiconductor wafer on the fine surface of the semiconductor wafer and the horizontal plane. The water 412 adjusts the amount of rotation of the semiconductor wafer lion in the x direction and the direction of the wafer in the plane and the semiconductor wafer 3 in the plane. Thereby, the position of the semiconductor wafer 300 can be adjusted so that the pads of the semiconductor wafer 300 are electrically connected to the pads of the test wafer 1". The vertical stage 416 is placed on the horizontal stage. 412, and controlling the position of the horizontal stage 412 in the vertical direction. For example, the vertical stage 416 can be placed on the semiconductor wafer 300 at a position facing the test wafer 1 (4). The horizontal stage 412 can be close to the test wafer 1 to electrically connect the semiconductor wafer 300 and the test wafer 100, and the successor 416 can be close to the semiconductor __ pair = 1 〇 After a predetermined distance, the space between the semiconductor wafer 3 and the test wafer 100 is depressurized to electrically connect the semiconductor wafer 3 and the test wafer 100. Moreover, the vertical stage can be mounted. The stage support portion 418 is fixed to the 416. As described in connection with Fig. 4, the position control unit 450 is based on the measurement U/9369 31570pifl correction date, the date of August, 101, the 981th face, 8 lion text: ? The image controls the position of the wafer stage 410. = Control unit 45 0, by controlling the position of the horizontal stage 4 wafer 300, pushing the sleeve, and setting the light to the + pad, (4) so that the semiconductor wafers are placed on the phase-measuring wafer (10). At the position corresponding to each bump, the wafer position detecting unit 42 performs the measurement in advance at the positions of the wafer stage _ h and M at the sun circle 100. For example, the =^^ portion 422 can detect the predetermined position in advance. The relative position in the plane of the test wafer 1〇〇 of the round wafer 410 on the B. The horizontal stage 412 is horizontally changed, and the Qing is set by the circle (4) riding 422; ^ Straight position mounting table = The upper half 3,450 is connected to the terminal of the test wafer (10) and the + conductor back to 300 in order to accurately perform the second test stage 412 according to the position of the test wafer measured by the measurement unit 422. + Service f" Water uses this configuration to adjust the semiconductor wafer'. . The position of the semiconductor two =::= == multiple terminals this line of electrical connection. Further, since the position of the bypass of the present example is fixed in the reaction chamber 2, the test detecting unit 422 can measure the position of the circle 100 when the semiconductor wafer 3G0 is further connected. The test wafer position debt measuring unit can measure the position of the measuring wafer (10) during the predetermined period of ::. Therefore, it is possible to efficiently test a plurality of semiconductor wafers. In the above description, the measuring unit 406 is placed on the wafer stage 410 in order to correct the semiconductor wafer 1379369 31570pifl. During the movement up, the alignment of the primary wafer 300 is marked with the position of the 226. In another example, the measuring unit 406 may mount the semiconductor wafer 3 on the wafer stage, and detect the position of the semiconductor, the target, and the ship. In this case, Z, 1疋. P is not placed on the moving path of the wafer stage 410, and at least 226 =::r::: period of the surface of the semiconductor wafer placed on a =: t:; As an example, the side phase diagram of the measuring unit 406 of this example: =::: The image detected by the measuring unit 406 to control the horizontal load: 41. 2 marks = 2 in the detection alignment The position of the 226 in the Y direction is quasi-standard. From: "Two set two = position in the direction.丫 侦测 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 丫 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 The position and the position in the γ direction are adjusted in the position in the Y direction and the amount of rotation. The movement of the t stage 410 is measured in the =j direction of the target 226, and the position of the semiconductor wafer 3〇〇 and the movement stage of the wafer stage 410 are shown in FIG. Show an illustration of another example of 226. The measurement of this example - a measurement section. Further, even if the semiconductor wafer ___ 2 ^ = is completely conveyed with respect to the two-circle stage shown in Fig. 3, it can be similarly detected by one measuring portion 4〇6;; = in this case, in the semiconductor crystal On the round shape, a plurality of 226 are provided as shown in the substantially same position on the axis in the X direction. The measuring unit 406 is disposed such that the alignment target a (four) bits ==. In such a configuration, the semiconductor wafer 3 〇〇 = positional deviation and the amount of rotation in the X direction and the Υ direction. Further, in Figs. 3 to 7, a rectangular alignment cup as an example is shown as '226, but the shape of the alignment mark 226 is not limited to this shape. The alignment mark 226 may have a prescribed shape such as a cross. Moreover, the alignment mark 226 may have a plurality of pads arranged in a predetermined shape. Fig. 8 shows an example of a cross-sectional view of the test wafer. The test wafer 100 of this example transmits a signal between the control device 1A and the semiconductor wafer 300 as described above. The test wafer 100 has a wafer side connection = pad 112, a device side connection pad 114, a through hole 116, an intermediate pad, and a wiring 117. 3l570pifl Revision Date August 1st, 2011 is No. 98118028 Chinese Manual No scribe correction The test wafer 100 has a wafer connection surface 1〇2 and a back surface of the wafer connection surface 102 as shown in FIG. The device connection surface formed. The wafer connection surface 102 may refer to a surface that faces the semiconductor wafer 3A. Further, the device connection surface 104 may be formed on the crystal connection surface 102 of the test wafer 1A by the control device 1 and the plurality of wafer side connection pads 112. Further, the wafer side connection pads 112 are provided for at least each of the semiconductor wafers 310. For example, the wafer side connection, the pad 112 can be set for each of the input and output terminals of each of the semiconductor wafers 31A. That is, in the case where each of the semiconductor wafers 31 has a plurality of input and output terminals, the wafer side connection pads 112 may be provided for each of the respective semiconductor wafers 310. Each of the wafer side connection pads 112 is provided at the same interval from each of the input and output terminals of the semiconductor wafer 3, and is electrically connected to the input/output terminal of the corresponding semiconductor wafer 31A. Further, the electrical connection may be a state in which an electrical signal can be transmitted between two members. For example, the wafer side connection pad U2 and the input and output terminals of the semiconductor wafer 31 can be electrically connected by direct contact or indirect contact via other conductors. The wafer-side connection pad 112 of this example is electrically connected to the input/output terminal of the semiconductor wafer 31A via a film as described later in FIG. Bumps are formed at positions of the film corresponding to the respective pads. Further, the output terminals of the wafer-side connection pads 112 and the semiconductor wafers 31 can be electrically connected in a non-contact state as in the case of capacitance coupling (electrostatic bonding) or induction bonding (7-magnetic bonding). And, 曰
日日 HJ 侧連接焊墊112及半導體晶片31〇的輸出入終端之間的傳 1379369 3l570pifl 修正日期101年8月1〇曰 爲第98118028號中文說明書無劃線修正本 送線路的一部分，也可為光學傳送線路。 多個裝置侧連接焊墊114形成在測試用晶圓1〇〇的裝 置連接面1〇4上且與性能板4〇4進行電氣連接。而且，裝 置侧連接焊墊114是與多個晶圓側連接焊墊112 一對一地 對應設置。在這裏，裝置侧連接焊墊114與性能板4〇4的 終端是以相同的間隔而設置。因此，如圖8所示，裝置側 連接焊墊114可以與晶圓侧連接焊墊112不同的間隔而設 置。 貝通孔116、中間焊墊150及配線17〇形成在測試用 曰曰圓100上，將對應的晶圓側連接焊塾及裝置側連接 焊墊114進行電氣連接。例如，中間焊墊150設置在裝置 連接面104的與晶圓侧連接焊墊112對向的位置上。貫通 孔116以一端與晶圓侧連接焊墊112連接，另一端與中間 焊墊150連接的形態，貫通測試用晶圓1〇〇而形成。'而且， 配線117在裝置連接面1〇4上，將中間焊墊15〇及裝置侧 連接焊墊114進行電氣連接。利用這種構成，可將排列間 隔不同的裝置侧連接焊墊114及晶圓侧連接焊墊112進行φ 電氣連接。 例如，晶圓側連接焊墊112為了與半導體晶片31〇的 各輸入終端進行電氣連接，而與各輸入終端以相同的間隔 ，配置。因此，晶圓侧連接焊墊112例如像圖2所示，在 每一半導體晶片310上’於預先確定的區域以微小的間隔 而設置。 對此，各個裝置侧連接焊墊114可以較1個半導體晶 1379369 31570pifl 修正日期101年8月10日 爲第98118028號中文說明書無劃線修正本 片310所對應的多個晶圓側連接焊墊112的間隔大之間隔 而設置。例如，裝置侧連接焊墊114在裝置連接面1〇4的 面内，以等間隔進行配置以使裝置側連接焊墊114的分佈 大致均等。 本例的測試用晶圓100與半導體晶圓3〇〇是以相同的 半導體材獅成，所以即使在周目溫度變耗情況下，也 可良好地維持測試用晶圓100和半導體晶圓300之間的電 氣連接。因此’即使在加熱半導體晶圓300並進行測試的 情況下，也可精度良好地對半導體晶圓則進行測試。 而且，由於測試用晶圓刚由半導體材料等形成，所 以可在測試用晶圓Η) 〇上容易地形成多個晶圓側連接焊塾 112等。例如，藉由曝光等的半導體製程可容易地 形成晶圓侧連接料112、裝置側連接焊墊丨14、貫通孔 116及配線117。因此’可在剩試用晶圓100上，容易地形 成與f個半導體晶片310相對應的多個晶圓側連接焊塾 荨。而且，職用晶圓丨⑻的終端可藉由在測試用晶 圓100上電鍍、蒸鍍導電材料等而形成。 =所示為電路部110的構成例。電 =部⑵、波形成形部13〇、驅動器132、比較器二圖 時序產生部136、邏輯崎部138、特 供給部142。另外，電路部⑽可在所連接的半導2片原 案產生部122具有圖_^^^案。本例的圖 題124、期待值記憶體126及 1379369 31570pifl 修正曰期101年8月10日 爲第98118028號中文說明書無劃線 ，效記憶體128。圖案產生部122可對圖案記憶體124輪 ，預先存儲的邏輯圖案。圖案記憶體]24可在測試開始前 存儲從控職置K)所舒的邏輯_。而且，圖案產 =也可根據縣賦料演算法(al細㈣*生成該 圖案。 波形成形部130根據從圖案產生部122所賦予的邏輯 圖案三形成測雜號⑽形。例如，波形成形部13〇可摔 叙的位兀期間輸出與邏輯圖案的各邏輯值相稱 的電壓，而形成測試信號的波形。 稱之器Γ輸出與從波形成形部l3G所賦予的波形相 ^之測试驅動器132可依據從時序產生部136所 予的時序錢，以輪_試信號。例如 出與時序信號相同週期的測試信號。媒動器?：= :信號經由切換部等而被供給到對應的半導體晶片 比較器134測疋半導體晶片31〇所輸出的響古。 二，Λ較二34可藉由依據從時序產生部136所。的 案依次偵測響應信號的邏輯值，而測定響 。。邏輯比，部138作為判定部而發揮機能，以根據比較 益134所測定的響應錢的賴 體晶片310的好壞。例如，、緖❹如”。Κ對應的+導 產生邛122所賊〜Γ 較部％可根據從圖案 :ΓΓ待值圖案和比較器134所债測的邏 _圖案疋否-致’而判定半導體晶片31〇的 20 1379369 31570pifl mm 98U 8028 修正日期10丨年8月l〇日 ί部二體126中所預先存儲的期待值圖 ^ 1讀比較部138。期待值記賴 裝置10所賦予的邏輯圖案。而且:圖 待值圖案。可根據預先所賦予的演算法，以生成該期 如，比較部138的比較結果。例 下，失憶體區域進行職的情況 儲邏輯ίίί 在半導體晶片31G的每—地址，存 t扣比較部138的好壞判定結果。控繼置料予 效5己憶體128所存儲的好壞判定社 貝 垾墊114可將失七？‘产萨」：：果。例如’裝置側連接 出到、㈣I 所存儲的好壞判定結果，輪 J測忒用日日圓100的外部的控制裝置1〇。 或電=、古Γ測定部140測定驅動器132所輸出的電壓 機” 140作為判定部而發The daily HJ side connection pad 112 and the semiconductor chip 31〇 between the input and output terminals 1379369 3l570pifl Correction date 101 August 1st is No. 98118082 Chinese manual without a slash correction part of the transmission line, also For optical transmission lines. A plurality of device side connection pads 114 are formed on the device connection surface 1〇4 of the test wafer 1A and electrically connected to the performance board 4〇4. Further, the device side connection pad 114 is provided in one-to-one correspondence with the plurality of wafer side connection pads 112. Here, the terminal of the device side connection pad 114 and the performance board 4〇4 are disposed at the same interval. Therefore, as shown in Fig. 8, the device side connection pads 114 can be disposed at different intervals from the wafer side connection pads 112. The beacon hole 116, the intermediate pad 150, and the wiring 17 are formed on the test dome 100, and the corresponding wafer side connection pad and the device side connection pad 114 are electrically connected. For example, the intermediate pad 150 is disposed at a position of the device connection face 104 opposite to the wafer side connection pad 112. The through hole 116 is formed by connecting one end to the wafer side connection pad 112 and the other end to the intermediate pad 150 so as to penetrate the test wafer 1B. Further, the wiring 117 is electrically connected to the device side connecting pad 1 and the intermediate pad 15 and the device side connecting pad 114. With this configuration, the device side connection pad 114 and the wafer side connection pad 112 having different arrangement intervals can be electrically connected by φ. For example, the wafer side connection pads 112 are disposed at the same intervals as the respective input terminals in order to electrically connect to the respective input terminals of the semiconductor wafer 31A. Therefore, the wafer side connection pads 112 are disposed, for example, as shown in Fig. 2, at a predetermined interval on each semiconductor wafer 310 at a predetermined interval. In this regard, the device-side connection pads 114 can be compared to a plurality of wafer-side connection pads corresponding to one semiconductor crystal 1379369 31570pifl, dated August 10, 2011, and the number of wafer-side connection pads corresponding to the slice 310. The interval of 112 is set at intervals. For example, the device side connection pads 114 are disposed at equal intervals in the plane of the device connection faces 1 to 4 so that the distribution of the device side connection pads 114 is substantially equal. Since the test wafer 100 and the semiconductor wafer 3 in this example are made of the same semiconductor material, the test wafer 100 and the semiconductor wafer 300 can be favorably maintained even in the case where the temperature of the peripheral temperature is consumed. Electrical connection between. Therefore, even when the semiconductor wafer 300 is heated and tested, the semiconductor wafer can be accurately tested. Further, since the test wafer is formed of a semiconductor material or the like, a plurality of wafer side connection pads 112 and the like can be easily formed on the test wafer. For example, the wafer side material 112, the device side connection pad 14, the through hole 116, and the wiring 117 can be easily formed by a semiconductor process such as exposure. Therefore, a plurality of wafer side connection pads corresponding to the f semiconductor wafers 310 can be easily formed on the remaining test wafer 100. Further, the terminal of the job wafer crucible (8) can be formed by plating, vapor-depositing a conductive material or the like on the test wafer 100. = is shown as a configuration example of the circuit unit 110. The electric portion (2), the waveform forming portion 13A, the driver 132, the comparator 2 map timing generating portion 136, the logical slug portion 138, and the special supply portion 142. Further, the circuit portion (10) can have a picture in the connected semi-guided pattern generating portion 122. Figure 124 of this example, expected value memory 126 and 1379369 31570pifl Correction period August 10, 101 is No. 98118018 Chinese manual without scribe line, effect memory 128. The pattern generating unit 122 can perform a logical pattern stored in advance on the pattern memory 124. The pattern memory 24 can store the logic _ from the control position K) before the test starts. Further, the pattern production = the pattern can be generated according to the county distribution algorithm (al fine (4) *. The waveform shaping unit 130 forms a measurement number (10) shape based on the logical pattern three given from the pattern generation portion 122. For example, the waveform forming portion A voltage commensurate with each logical value of the logic pattern is output during the position of 13 〇 叙 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The test signal of the same cycle as the timing signal can be generated based on the timing of the timing from the timing generation unit 136. For example, the test signal of the same cycle as the timing signal is supplied to the corresponding semiconductor chip via the switching unit or the like. The comparator 134 measures the loudness of the output of the semiconductor wafer 31. Second, the second ratio 34 can be determined by sequentially detecting the logical value of the response signal according to the case from the timing generating portion 136. The part 138 functions as a determination unit, and the quality of the reliance wafer 310 of the response money measured according to the comparison benefit 134. For example, the + ❹ ” Κ Κ Κ Κ Κ Κ Κ Κ Κ Κ Κ 邛 邛 所 贼 贼 贼%% According to the pattern: the pattern of the value of the pattern and the logic pattern of the debt 134 of the comparator 134, the semiconductor wafer 31 is determined to be 20 1379369 31570pifl mm 98U 8028, and the date of correction is 10:00, August 1st, ί The expected value map 1 stored in the body 126 reads the comparison unit 138. The expected value is recorded in the logical pattern given by the device 10. Moreover, the pattern of the pending value can be generated according to an algorithm given in advance to generate the period. The comparison result of the comparison unit 138. For example, in the case where the memory of the memory is lost, the memory ί 逻辑 在 在 在 在 在 在 在 在 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The memory of the goodness and badness of the body 128 can be lost. The result is: for example, the device side is connected to the (4) I stored in the good or bad judgment result, and the wheel J is measured and used. The external control device 1 of the Japanese yen 100. The electric power measurement unit 140 measures the voltage machine output by the driver 132" 140 as a determination unit.
波形是否滿足規定的樣式，而判定半導體二I 31〇 祕轉半導體晶片 所睡將與職中從控制裝置10 3予=力相稱的電源電力，供給到半導體晶片勝 供給部142也可對電她 料11G具有這種構成，所以可實現 控制裝置!。的規模之測試系統姻。例如，作為控制農丄 1379369 31570pifl 修正日期101年8月1〇日 爲第98118028號中文說明書無劃線修正# 1〇 ’可利用通用的個人計算機等。 圖10所不為將測試用晶圓100及半導體晶圓300進行 電氣連接的構成例。本例的測試系統藉由將測試用曰 圓100及半導體晶圓300配置在密閉空間内，並對該: 空間内進行，而使測試用晶圓100及半導體晶圓300 接近並進行電氣連接。 、更具體地說，在固定有測試用晶圓100的性能板404 及載置半導體晶圓3GG的晶_架之間形成密閉空 間。而且’在性能板404、測試用晶圓1〇〇及半導體晶= 3〇〇之間分別設置異向性導電片。•然後，藉由對密閉 内進行減壓，而利制試用晶圓等來題異向性 片，使測試用晶15 1〇〇等進行電氣連接。因此，測 圓100以在垂直方向上可移動的形態，而固定在性能板Z 上。 而二且，測試用晶圓100在水平方向上可移動的範圍中 ，於，试用晶圓100及半導體晶圓3()()之間的對準誤差的 容許範圍内較佳。例如，測試用晶圓100在水平方向可移 動的範圍’與測試用晶圓觸及半導體晶圓3⑻ 度相比足夠小時較佳。 T見 測試用晶圓100利用支持部綱而固定在性能板4〇4 上。支持部204將裝置側異向性導電片212、裝置側密封 214 ' /則试用晶圓10〇、晶圓側異向性導電片218、 _ 222及固定環220固定在性能板404上。 ‘、 裝置側異向性導電片212由於設置在測試用晶圓1〇〇 22 1379369 3l570pifl 修正日期101年8月10曰 爲第98118028號中文說明書無劃線修正本 及性能板姻之間並受到按壓，所以將測試用晶圓削的 電極和性能板彻的電極進行電氣連接。測試用晶圓1〇〇 f壓裝置側異向性導電片212，並以可與性能板電氣 f接的程度，以對性能板偏的下面之垂直方向的位置可 在規定的範圍進行位移的形態而得到支持。 j置側密封部214沿著薄膜222的性能板彻側的面 =邊部而設置’並對薄膜222的性能板4〇4侧的面的周 能板404之間進行密封。裝置側密封部214可以 相._㈣健《向性導電片加*與性能板 4〇4導通的程度以利用具有彈性的彈性材料來形成。 異向性導電片218設置在測試用晶圓_及薄 膜22之間。晶圓側異向性電導電片218藉由按屋，而將 :則f用晶圓100的半導體晶圓3〇 側連接終端和薄膜222㈣塊終端進行電氣=置之b曰固 的玖端㈣^ 可具有凸塊終端，將半導體晶圓300 t固定^ 2== _的晶圓侧連接終端進行電氣連 ^ 寻膜222對裝置側密封部214進行固定。 幻如，固定環22〇可沿著薄膜您的半導體 周邊部呈環狀而設置。固定環22〇的内‘較晶 薄導電片218及半導體晶圓300的直徑還大。日日 且端具有大致相同直徑的圓形狀， ^ 壞0上。裝置側異向性導電片212、 =日日圓1〇〇及晶圓側異向性導電片218，配置在薄膜 23 丄:wy划 31570pifl 爲第98118028號中文說鴨無劃線修正本 修正日期101年8月1〇日 二t性旎板404之間’並利用薄膜222而對性能板404 ^、、規疋的位置上<•如圖1〇所示，在裝置側異向性導電 片212、測試用晶圓卿及晶圓側異向性導電片218和裝 置=封部214之間’可設置有間隙。利用這種構成，而 以+導體晶圓來按壓薄膜222，從而可將半導體晶圓 3〇〇和測試用晶圓100進行電氣連接。 、一支持部2〇4可藉由支持該固定環MO而對薄膜Μ2等 ，打支持。支持部204可以薄膜222對性能板4〇4的下面 月匕夠在規定的涵内接近之形態，而對測試用晶圓削進 行支持。例如’支持部204可以固定環22〇的下端從性能 板404的下面不離開規歧離以上的形態，而在從性能板 404的下面只離開規定距離的位置上，來對固定環的 下端進行支持。 晶圓託盤408在配置於規定位置的情況下，以與性能 板404形成密閉空間的形態而設置。本例的晶圓托架娜 2性能板404、裝置侧孔部214及晶圓側密封部224形成 密閉空間。而且’晶圓托架在該密閉空間側的面上載φ 置半導體晶圓300。 晶圓侧密封部224在晶圓托架408的表面上，沿著與 薄膜222的周邊部相對應的區域而設置，並對薄膜222的 晶圓托架側的面的周邊部及晶圓托架4〇8之間進行密封。 晶圓側密封部224在晶圓托架408的表面上可形成環狀。 而且，晶圓側密封部224形成唇(lip)狀，其隨著與晶 圓托架408表面的距離增大，環狀的直徑亦增大。晶圓側 24 3l570pifi •修正曰期101年8月1〇日 胃胃98118028號中文說明書無劃線修正本 密封部224在被按壓在_ 222 ±的情況下，依據該按壓 力而頂端撓曲，從而使薄膜222和半導體晶圓300的距離 接近。而且，晶圓側密封部224在未被按壓在薄膜222上 的狀態下，自晶圓托架408的表面的高度成為較半導體晶 圓300的高度還高。 圖5所關聯說明的垂直載台416使晶圓托架4〇8進行 移動，直至晶圓側密封部224的上端部與薄膜222緊宗 合的位置。藉由這種構成’可性能板:J = 、裝置側密封部214及晶圓側密封部224，而形成存儲 測η式用晶圓1 〇〇及半導體晶圓3〇〇的密閉空間。另外，水 平載台412在垂直載台416使晶圓托架408沿著垂直方向 進行移動之前，對半導體晶圓300的水平面内的位置及傾 斜進行調整較佳。 減壓部234對性能板404及晶圓托架4〇8之間的密閉 空間進行減壓，該密閉空間由性能板4〇4、晶圓托架4〇8、 裝置側密封部214及晶圓側密封部224形成。減壓部234 在晶圓載台410使晶圓托架408移動而形成上述的密閉空 間後，對該密閉空間進行減壓。 $ 藉此，減壓部234使晶圓托架408對性能板4〇4接近 到規定的位t。晶圓托架概藉由配置在該蚊的位置 上，而對裝置側異向性導電片212及晶圓側異向性導電片 218施加按壓力，使性能板404及測試用晶圓1〇〇進行電 氣連接，且使測試用晶圓1〇〇及半導體晶圓3〇〇進行電氣 1379369 3l570pifl 爲第98118028號中文說明書無劃線修正# 修正曰期101年8月丨0日 日日關㈣邵224可在固定環22〇的 斑 溥膜222相接觸。在這種情況下， ” 八*…… 况下袷閉空間由薄膜222而 刀割，能板4〇4_空間和晶圓托架4〇8側的空間。因 ^在薄膜222上設置將這些空間進行連接的貫通孔242 季父佳。 而且，在測試用晶圓100、裝置側異向性導電片212 及晶圓側異向性導電片218上，也設置貫通孔24〇、貫通 孔213及貫通孔219較佳。薄膜222、測試用晶圓1〇〇、裝 置侧^向性導電片212及晶圓側異向性導電片218上所設 置的貝通孔，在各個面内大致均等地分散配置較佳。藉由 XI種構成，在對密閉空間進行減壓的過程中所吸入的空 氣，利用多個貫通孔而分散流動。另外，貫通孔242、貫 通孔240、貫通孔213及貫通孔219可設置在對應的位置 上’而且，也可設置在彼此不同的位置上。 因此，在對密閉空間進行減壓的過程中，在裝置側異 向性導電片212及晶圓侧異向性導電片218上所施加的按 壓力，可在各個面内大致均等地分散著，大幅減小減壓過 程中的應力歪斜。因此，可防止測試用晶圓1〇〇的割裂、 異向性導電片的歪斜等。藉由這種構成，可利用一個減壓 部234，而對性能板404及薄膜222之間的空間和薄膜222 及半導體晶圓300之間的空間進行減壓。 而且，減壓部234可使半導體晶圓300吸附在晶圓托 架408上。本例的減壓部234具有密閉空間用的減壓器236 和半導體晶圓用的減壓器238。而且，在晶圓托架408上， 1379369 3l570pifl 修正曰期101年8月10日 爲第98118028號中文說明書無劃線修正本 形成有密閉空間用的吸氣路徑232和半導體晶圓用的吸氣 路徑230。 利用這種構成’可將性能板彻上所固定的測試用晶 圓100和半導體晶圓300進行電氣連接。如上所述，由於 職用晶圓100固定在性能板4〇4上，所以可容易地進行 測試用晶圓100及半導體晶圓300間的對準。 雖然本發明已以實施例揭露如上，然其並非用以限定 ί發明，任㈣屬技術領域中具有通f知識者，在不脫離 =明之射和範_，當可作些許之更動與潤飾 ^明之賴顏當狀冑請專· 【圖式簡單制】 ，1所禾為關於-實施形態的測試系統侧的概 圖2為測試系統4〇〇的測試的概要說明圖。 圖3為將半導體晶圓3〇〇與晶 進行對準之方法的-個例子。 秋口 的規疋位置 ::示=部.進行了掃据之圖 圖5所不為反應室20的内部構造的—個例子 載台彻進行移動㈣侧對準標諸 挪二進行移動期間偵測對準標諸 ::2測試用晶圓1 〇 〇的剖面圖的一個例子。 圖9所示為電路11〇的構成例。 圖1〇所示為將測試用晶圓⑽及半導體晶圓300進 27 1379369 修正日期ιοί年8月10曰 31570pifl 爲第98118028號中文說明書無劃線修正本 行電氣連接的構成例。 【主要元件符號說明】 10 :控制裝置 20 :反應室 40 :搬運部 60 :晶圓盒 100 ·測試用晶圓 102 .晶圓連接面 104 :裝置連接面 110 :電路部 112 :晶圓侧連接焊墊 114 :裝置侧連接焊墊 116 :貫通孔 117 :配線 122 :圖案產生部 124 :圖案記憶體 126 :期待值記憶體 _ 128 :失效記憶體 130 :波形成形部 132 :驅動器 134 :比較器 136 :時序產生部 138 :邏輯比較部 140 :特性測定部 28 1379369 31570pifl 爲第98118028號中文說明書無劃線修正本 修正日期101年8月10日Whether or not the waveform satisfies the predetermined pattern, and it is determined that the semiconductor power source of the semiconductor chip is to be supplied with power to the semiconductor wafer win supply unit 142. The material 11G has such a configuration, so that the control device can be realized! The scale of the test system marriage. For example, as a control farmer 1379369 31570pifl Correction date August 1st, 2011 No. 98118028 Chinese manual no scribe correction # 1〇 'You can use a general-purpose personal computer. Fig. 10 is not a configuration example in which the test wafer 100 and the semiconductor wafer 300 are electrically connected. In the test system of this example, the test wafer 100 and the semiconductor wafer 300 are placed in a sealed space, and the test wafer 100 and the semiconductor wafer 300 are brought into close proximity and electrically connected to the space. More specifically, a sealed space is formed between the performance plate 404 to which the test wafer 100 is fixed and the crystal frame on which the semiconductor wafer 3GG is placed. Further, an anisotropic conductive sheet is provided between the performance plate 404, the test wafer 1A, and the semiconductor crystal = 3〇〇. • Then, by decompressing the sealed interior, a test wafer or the like is used to electrically connect the test wafers, and the test crystals are electrically connected. Therefore, the measuring circle 100 is fixed to the performance board Z in a form movable in the vertical direction. Further, in the range in which the test wafer 100 is movable in the horizontal direction, it is preferable within the allowable range of the alignment error between the trial wafer 100 and the semiconductor wafer 3 (). For example, it is preferable that the range in which the test wafer 100 is movable in the horizontal direction is sufficiently smaller than when the test wafer touches the semiconductor wafer 3 (8). T See test wafer 100 is fixed on performance board 4〇4 using the support section. The support unit 204 fixes the device side anisotropic conductive sheet 212, the device side seal 214' / the test wafer 10A, the wafer side anisotropic conductive sheets 218, _ 222, and the fixing ring 220 to the performance board 404. ', the device side anisotropic conductive sheet 212 is set in the test wafer 1 〇〇 22 1379369 3l570pifl correction date August 10, 2010 is the number 98118018 Chinese manual no line correction and performance between the board and received Pressing, the electrode for the test wafer is electrically connected to the electrode of the performance plate. The test wafer 1〇〇f presses the device side anisotropic conductive sheet 212, and the position in the vertical direction of the lower surface of the performance plate can be displaced within a predetermined range to the extent that it can be electrically connected to the performance board. Supported by form. The j-side seal portion 214 is provided along the surface of the film 222 on the side of the performance plate = the side portion, and seals between the surface plates 404 on the surface of the film 222 on the performance plate 4〇4 side. The device side seal portion 214 can be formed by using a flexible elastic material to the extent that the directional conductive sheet plus * and the performance sheet 4 〇 are conducted. The anisotropic conductive sheet 218 is disposed between the test wafer _ and the film 22. The wafer-side anisotropic conductive sheet 218 is made by the house, and then the semiconductor wafer 3 is connected to the terminal of the wafer 100 and the terminal of the film 222 (four) is electrically connected to the end of the film (4). ^ There may be a bump terminal, and the wafer side connection terminal of the semiconductor wafer 300 t fixed ^ 2 == _ is electrically connected to the device side sealing portion 214 to fix the device side sealing portion 214. The phantom, the retaining ring 22〇 can be placed in a ring shape along the periphery of the film. The inner diameter of the thinner conductive sheet 218 and the semiconductor wafer 300 in the fixing ring 22'' is larger. The day and end have a circular shape of approximately the same diameter, ^ bad 0. Device side anisotropic conductive sheet 212, = Japanese yen 1 〇〇 and wafer side anisotropic conductive sheet 218, arranged in the film 23 丄: wy stroke 31570pifl is the number 98118082 Chinese duck no line correction this correction date 101 Between the two 旎 旎 404 on the 1st of August of the year, and using the film 222 and the performance board 404 ^, the position of the rule < • as shown in Figure 1 ,, on the device side anisotropic conductive sheet 212. A gap may be provided between the test wafer and the wafer side anisotropic conductive sheet 218 and the device=seal 214. With such a configuration, the film 222 is pressed by the + conductor wafer, whereby the semiconductor wafer 3 and the test wafer 100 can be electrically connected. A support portion 2〇4 can support the film Μ2 and the like by supporting the fixed ring MO. The support portion 204 can support the test wafer for the film 222 to approach the lower portion of the performance board 4〇4 within a predetermined culvert. For example, the support portion 204 can fix the lower end of the ring 22 from the lower end of the performance plate 404 without departing from the lower surface of the performance plate 404, and at a position away from the lower surface of the performance plate 404 by a predetermined distance. stand by. When the wafer tray 408 is placed at a predetermined position, the wafer tray 408 is provided in a closed space with the performance plate 404. The wafer carrier Na 2 performance plate 404, the device side hole portion 214, and the wafer side sealing portion 224 of this example form a sealed space. Further, the wafer carrier mounts the semiconductor wafer 300 on the surface of the sealed space. The wafer side sealing portion 224 is provided on the surface of the wafer holder 408 along a region corresponding to the peripheral portion of the film 222, and the peripheral portion of the surface of the film 222 on the wafer carrier side and the wafer holder Seal between the shelves 4〇8. The wafer side sealing portion 224 may form a ring shape on the surface of the wafer carrier 408. Further, the wafer side sealing portion 224 is formed in a lip shape, and as the distance from the surface of the crystal circular holder 408 increases, the diameter of the annular shape also increases. Wafer side 24 3l570pifi • Corrected the period of the first quarter of August, 101 days, the stomach of the stomach, 98118028, the Chinese manual, no line correction, the sealing part 224 is pressed at _ 222 ±, the top end is deflected according to the pressing force, Thereby, the distance between the film 222 and the semiconductor wafer 300 is close. Further, in a state where the wafer side sealing portion 224 is not pressed against the film 222, the height from the surface of the wafer holder 408 is higher than the height of the semiconductor wafer 300. The vertical stage 416 associated with Fig. 5 moves the wafer carrier 4A8 until the upper end portion of the wafer side sealing portion 224 is in close contact with the film 222. By the configuration of the "performance board: J = , the device side sealing portion 214 and the wafer side sealing portion 224", a sealed space for storing the wafer 1 and the semiconductor wafer 3 is formed. Further, the horizontal stage 412 preferably adjusts the position and inclination in the horizontal plane of the semiconductor wafer 300 before the vertical stage 416 moves the wafer carrier 408 in the vertical direction. The pressure reducing unit 234 decompresses the sealed space between the performance board 404 and the wafer holder 4〇8, which is composed of the performance board 4〇4, the wafer holder 4〇8, the device side sealing unit 214, and the crystal. The round side seal portion 224 is formed. The decompression unit 234 moves the wafer holder 408 on the wafer stage 410 to form the above-described sealed space, and then decompresses the sealed space. Thereby, the decompression unit 234 brings the wafer carrier 408 close to the predetermined level t to the performance board 4〇4. The wafer carrier is placed at the position of the mosquito, and a pressing force is applied to the device-side anisotropic conductive sheet 212 and the wafer-side anisotropic conductive sheet 218 to make the performance board 404 and the test wafer 1 〇Electrical connection, and the test wafer 1〇〇 and the semiconductor wafer 3〇〇 electrical 1379369 3l570pifl is the 9811802 Chinese manual without scribe correction # 曰 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 The 224 can be contacted by the cornea membrane 222 of the retaining ring 22〇. In this case, "eight*... The closed space is cut by the film 222, and the space of the board 4〇4_ space and the wafer carrier 4〇8 side. The through holes 242 that are connected to these spaces are preferably used. Further, the test wafer 100, the device-side anisotropic conductive sheets 212, and the wafer-side anisotropic conductive sheets 218 are also provided with through holes 24 and through holes. Preferably, the through hole 219 is 213 and the through hole 219 provided in the film 222, the test wafer 1 〇〇, the device side conductive conductive sheet 212, and the wafer side anisotropic conductive sheet 218 is substantially in each plane. It is preferable to disperse and distribute uniformly. The air sucked in the process of depressurizing the sealed space is dispersed by a plurality of through holes, and the through holes 242, the through holes 240, and the through holes 213 are formed by the XI configuration. And the through holes 219 may be disposed at corresponding positions 'and may be disposed at positions different from each other. Therefore, in the process of decompressing the sealed space, the device side anisotropic conductive sheet 212 and the wafer side The pressing force applied on the anisotropic conductive sheet 218 can be applied to each surface The inside is substantially uniformly dispersed, and the stress skew during the decompression process is greatly reduced. Therefore, it is possible to prevent the crack of the test wafer 1 歪, the skew of the anisotropic conductive sheet, etc. With this configuration, one can be utilized. The decompression portion 234 decompresses the space between the performance plate 404 and the film 222 and the space between the film 222 and the semiconductor wafer 300. Further, the decompression portion 234 can adsorb the semiconductor wafer 300 to the wafer holder. The pressure reducing portion 234 of the present example has a pressure reducer 236 for a sealed space and a pressure reducer 238 for a semiconductor wafer. Moreover, on the wafer carrier 408, 1379369 3l570pifl is amended in the last ten months of August. On the 10th, the Chinese manual No. 98118028 has no scribing correction. The intake path 232 for the sealed space and the intake path 230 for the semiconductor wafer are formed. With this configuration, the performance board can be completely fixed for testing. The wafer 100 and the semiconductor wafer 300 are electrically connected. As described above, since the job wafer 100 is fixed on the performance board 4〇4, alignment between the test wafer 100 and the semiconductor wafer 300 can be easily performed. Although the invention has been implemented The example is disclosed above, but it is not intended to limit the invention. Anyone who has knowledge of the technology in the field of technology does not leave the field of the Ming and the _, and can make some changes and refinement. Fig. 3 is a schematic diagram of the test of the test system 4〇〇. Fig. 3 shows the semiconductor wafer 3〇〇 and the crystal. An example of the method of aligning. The position of the autumn mouth:: indication = part. The diagram of the sweeping data is shown in Fig. 5. The example of the internal structure of the reaction chamber 20 is not carried out. An example of a cross-sectional view of the 1: test wafer 1 〇〇 is used for the calibration of the target during the movement. Fig. 9 shows an example of the configuration of the circuit 11A. Fig. 1A shows a configuration example in which the test wafer (10) and the semiconductor wafer 300 are incorporated into the current specification of the Chinese language specification No. 9811828. [Description of Main Components] 10: Control device 20: Reaction chamber 40: Transport unit 60: wafer cassette 100 • Test wafer 102. Wafer connection surface 104: Device connection surface 110: Circuit portion 112: Wafer side connection Pad 114: Device side connection pad 116: Through hole 117: Wiring 122: Pattern generating portion 124: Pattern memory 126: Expected value memory _128: Failed memory 130: Waveform forming portion 132: Driver 134: Comparator 136: Timing generation unit 138: Logic comparison unit 140: Characteristic measurement unit 28 1379369 31570pifl No. 98118829 Chinese manual No slash correction This correction date is August 10, 101
142 電源供給部 150 中間焊墊 204 支持部 212 裝置側異向性導電片 213 貫通孔 214 裝置側密封部 218 晶圓側異向性導電片 219 貫通孔 220 固定環 222 薄膜 224 晶圓側密封部 226 對準標誌 230 吸氣路徑 232 吸氣路徑 234 減壓部 236 減壓器 238 減壓器 240 貫通孔 242 貫通孔 300 半導體晶圓 310 半導體晶片 400 測試糸統 402 母板 404 性能板 29 1379369 31570pifl 修正日期ιοί年8月10日 爲第98118028號中文說明書無劃線修正本 406 :測定部 407 :攝像元件 408 .晶圓托架 410 :晶圓載台 412 :水平載台 416 :垂直載台 418 :載台支持部 420 :引導部 422 ·測試用晶圓位置Ί貞測部 450 :位置控制部142 power supply unit 150 intermediate pad 204 support portion 212 device side anisotropic conductive sheet 213 through hole 214 device side sealing portion 218 wafer side anisotropic conductive sheet 219 through hole 220 fixing ring 222 film 224 wafer side sealing portion 226 Alignment mark 230 Suction path 232 Suction path 234 Pressure reducing part 236 Pressure reducer 238 Pressure reducer 240 Through hole 242 Through hole 300 Semiconductor wafer 310 Semiconductor wafer 400 Test system 402 Mother board 404 Performance board 29 1379369 31570pifl Amendment date ιοί年8月10日#98118028 Chinese manual no scribe correction 406: Measurement unit 407: imaging element 408. Wafer holder 410: Wafer stage 412: Horizontal stage 416: Vertical stage 418: Stage support unit 420 : Guide unit 422 · Test wafer position detecting unit 450 : Position control unit
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