200945970 九、發明說明： *【發明所屬之技術領域】 本發明涉及電路板製作技術領域，尤其涉及一種具有 斷差結構之電路板之製作方法。 【先前技術】 ’ 隨著電子產品日趨小型化及高速性能化，電路板表面 焊接之元件越來越多，要求電路板之導電線路密度及訊號 ❹傳輸量亦越來越大。為適應此需求，電路板已從單面板發 展為雙面板及多層板。其中，雙面電路板及多層電路板具 有較多佈線面積、較高裝配密度而得到廣泛應用，參見文 獻：Takahashi，A·; High density multilayer printed circuit board for HITAC M-880; IEEE Trans, on Components, Packaging，and Manufacturing Technology; 1992 o 作為近年來出現之一種新型多層電路板，具有斷差結 構之電路板由於其於不同區域具有不同層數，層數少之區 Ο 域厚度小、剛性小，層數多之區域具有高線路密度、較大 厚度及較大剛度，而具有優異之整體性能，其既可達成大 量訊號之傳輸，又具有適當之剛撓性。 參見圖la，為一種具有斷差結構之多層電路板1〇〇之 結構示意圖。該多層電路板1〇〇由一雙面基板no與一單 面基板120製成，其中’該雙面基板110之第一導電線路 111表面設有用於封裝電子元件之貼裝區112。 目前，通常採用增層法即層層疊加法製作具有斷差結 7 200945970 構之電路板。以多層電路板100為例，其習知之製作方法 « 包括：首先，提供雙面基板110、單面基板120及黏合層 130 ’請一併參閱圖ia及圖lb，該雙面基板110之第一表 面為導電線路層111，該黏合層130設有與貼裝區112尺寸 對應之切口 131;其次，請參見圖lc，利用黏合劑層130 ‘， 將單面基板120之基材層121壓合到雙面基板110之第一 導電線路層111表面，由此得到電路板基板140 ;再次，參 見圖Id及圖le，於電路板基板140之外層導電層表面142 ®鋪設幹膜150，採用曝光、顯影、蝕刻法製作第二導電線路 143等步驟。 然而，當雙面基板110為柔性電路基板時，由於具有 較好之撓曲性及延展性，其與單面基板120壓合時，切口 131對應處之雙面基板將朝單面基板120凹陷，引起貼附於 該處之幹膜結構發生彎曲，當曝光、顯影及蝕刻線路時， 由於切口 131對應處之幹膜150向單面基板120凹陷，將 ❽引起後續藉由曝光、顯影、蝕刻導電層工藝製得之第二導 電線路143粗細不一，甚至斷線，極大地影響電路板之線 路精度及產品合格率。 有鐘於此，提供一種具有斷差結構之電路板之製作方 法’以提高電路板之製作精度及合格率實為必要。 【發明内容】 一種具有斷差結構之電路板之製作方法，其包括下述 步驟：提供第一基板、黏合層及第二基板，該第一基板包 8 200945970 • 一基材層相對兩表面之第-導電 第二基材層表面之第三導電層;於第一導==於: =路，並於該第-導電線路表面定義出 合層設置貫通其相對兩表面之切口，由此於該黏 L切割面及與第一切割面相對之第二切割面; 寸對應之加強片；將第—基板、黏合層及第二基板 依。人疊層並壓合，且使該第一導電線路及第二基 緊貼於黏合層之相對兩表面，該貼裝區位於第一切割:與 第二切割面之間，該加強片收容於切口；於第二導電層形 成第二導電線路，得電路基板；沿第一切割面裁斷該;路 基板’由此製得具有斷差結構之電路板。 本技術方案提供之具有斷差結構之電路板之製作方法 藉由於黏合層没置與貼裝區尺寸匹配之切口，利用該具有 切口之黏合層黏合第一基板及第二基板’再採用加強片填 ❹充切口 ’使得外層待佈線之導電層表面平整，避免了壓人 第一基板與第二基板時由於切口引起之外層導電層向切口 凹陷產生落差，從而克服了先前技術之製作方法容易導致 導電線路粗細不一，甚至斷線之缺陷。因此，使用本技術 方案之製作方法可顯著地提高電路板之線路製作精度及產 品合格率。 【實施方式】 以下將結合實施例及附圖對本技術方案提供之具有斷 9 200945970 差結構之電路板之製作方法進行詳細說明。 本實施例提供之具有斷差結構之電路板之製作方法包 括以下步驟： 第一步’提供第一基板2〇〇、第二基板300及黏合層 400 °200945970 IX. INSTRUCTIONS: * [Technical Field of the Invention] The present invention relates to the field of circuit board manufacturing technology, and in particular to a method for fabricating a circuit board having a stepped structure. [Prior Art] With the increasing miniaturization and high-speed performance of electronic products, more and more components are soldered on the surface of the board, and the density of the conductive lines of the board and the transmission amount of the signal are also increasing. To meet this need, boards have evolved from single-panel to dual-panel and multi-layer boards. Among them, the double-sided circuit board and the multi-layer circuit board have a large wiring area and a high assembly density and are widely used, see the literature: Takahashi, A·; High density multilayer printed circuit board for HITAC M-880; IEEE Trans, on Components , Packaging, and Manufacturing Technology; 1992 o As a new type of multilayer circuit board that has emerged in recent years, circuit boards with a faulty structure have different layers in different regions, and the area with a small number of layers has a small thickness and a small rigidity. The area with a large number of layers has high line density, large thickness and large rigidity, and has excellent overall performance, which can achieve a large number of signal transmission and appropriate rigidity. Referring to Fig. la, it is a schematic structural view of a multilayer circuit board having a stepped structure. The multilayer circuit board 1 is made of a double-sided substrate no and a single-sided substrate 120, wherein the surface of the first conductive line 111 of the double-sided substrate 110 is provided with a mounting region 112 for packaging electronic components. At present, a circuit board having a fault junction 7 200945970 is usually produced by a layer-up method, that is, a layer stacking method. Taking the multilayer circuit board 100 as an example, the conventional manufacturing method includes: first, providing the double-sided substrate 110, the single-sided substrate 120, and the adhesive layer 130. Referring to FIG. 1A and FIG. 1b, the double-sided substrate 110 One surface is a conductive circuit layer 111, and the adhesive layer 130 is provided with a slit 131 corresponding to the size of the mounting region 112. Secondly, referring to FIG. 1c, the substrate layer 121 of the single-sided substrate 120 is pressed by the adhesive layer 130'. The circuit board substrate 140 is obtained on the surface of the first conductive circuit layer 111 of the double-sided substrate 110. Again, referring to FIG. 1D and FIG. The second conductive line 143 is formed by exposure, development, and etching. However, when the double-sided substrate 110 is a flexible circuit substrate, since it has better flexibility and ductility, when it is pressed against the single-sided substrate 120, the double-sided substrate corresponding to the slit 131 will be recessed toward the single-sided substrate 120. The dry film structure attached to the portion is bent. When the line is exposed, developed, and etched, the dry film 150 corresponding to the slit 131 is recessed toward the single-sided substrate 120, causing the subsequent exposure, development, and etching. The second conductive line 143 obtained by the conductive layer process has different thicknesses and even broken wires, which greatly affects the circuit precision and product qualification rate of the circuit board. In view of this, it is necessary to provide a method for fabricating a circuit board having a stepped structure to improve the precision and yield of the circuit board. SUMMARY OF THE INVENTION A method for fabricating a circuit board having a fault structure includes the steps of: providing a first substrate, an adhesive layer, and a second substrate, the first substrate package 8 200945970 • a substrate layer opposite to both surfaces a third conductive layer on the surface of the first conductive second substrate layer; on the first conductive path ===:= way, and defining a slit formed on the surface of the first conductive conductive path through the opposite surfaces thereof, thereby The adhesive L-cut surface and the second cut surface opposite to the first cut surface; the corresponding reinforcing sheet; the first substrate, the adhesive layer and the second substrate. The person is laminated and pressed, and the first conductive line and the second base are closely attached to opposite surfaces of the adhesive layer, and the mounting area is located between the first cutting surface and the second cutting surface, and the reinforcing sheet is received in the a second conductive line is formed on the second conductive layer to obtain a circuit substrate; the circuit is cut along the first cutting surface; and the circuit substrate 'is thus obtained a circuit board having a stepped structure. The method for manufacturing a circuit board having a fault structure provided by the technical solution is characterized in that the adhesive layer does not have a slit matching the size of the mounting area, and the first substrate and the second substrate are bonded by the adhesive layer having the slit. Filling the entangled incision 'so that the surface of the conductive layer to be laid on the outer layer is flat, avoiding the gap between the outer conductive layer and the recessed recess caused by the slit when pressing the first substrate and the second substrate, thereby overcoming the prior art manufacturing method is easy to cause The thickness of the conductive lines is different, and even the defects of the broken lines. Therefore, the fabrication method of the present technical solution can significantly improve the circuit fabrication precision and product yield of the circuit board. [Embodiment] Hereinafter, a method for fabricating a circuit board having a differential structure of the present invention provided by the present invention will be described in detail with reference to the embodiments and the accompanying drawings. The method for manufacturing a circuit board having a fault structure provided by this embodiment includes the following steps: First step 'providing a first substrate 2, a second substrate 300, and an adhesive layer 400 °
請參閱圖2,第一基板2〇〇為包括至少兩層導電層之柔 性基板’其具體結構依待製作之具有斷差結構之電路板之 具體結構而定。本實施例中，第一基板200為一柔性雙面 銅層墨板’其包括第一基材層21〇及分別位於第一基材 210相對兩表面之第一導電層22〇及第二導電層230。 第一基材層210可為單層絕緣基材，亦可為單層導電 覆Referring to FIG. 2, the first substrate 2A is a flexible substrate having at least two conductive layers, the specific structure of which depends on the specific structure of the circuit board having the stepped structure to be fabricated. In this embodiment, the first substrate 200 is a flexible double-sided copper ink sheet comprising a first substrate layer 21 and a first conductive layer 22 and a second conductive layer respectively located on opposite surfaces of the first substrate 210. Layer 230. The first substrate layer 210 may be a single-layer insulating substrate or a single-layer conductive coating.
層與分別设於該單層導電層相對兩表面之絕緣基材構成之 複合基材。本實施例中，第一基材層21〇為單層絕緣基材 層，其材質為柔動性較好之材料，如選自㈣亞胺、聚四 氟乙稀f硫胺、聚甲基丙烯酸甲酯、聚碳酸酯、聚乙烯 對苯二酸醋、聚醯亞胺-聚乙稀_對苯二甲@旨共聚物中之一種 弟一導電層220及第-莫雷思 人乐一导電層230之材質可為銅、銀、 金或其它常見金屬。本實施仓丨φ 贫 4貝她例甲，第一導電層220及第二 導電層230為麼延銅箱。 错椒2基板綱可為剛性基板，亦可為柔性基板，其結 構根據實㈣㈣作之具有斷差結狀電路板而定。本實 施例中’第二基板300為包括筮—A a ^ „ α1Λ ^ 匕括第一基材層310及形成於第 一基材層310 —表面之第二導雷 示一导電層320之剛性基板，其具 200945970 •有第一表面301及與第一表面301相對之第二表面3〇2。其 中，第-表面3〇1對應於第二基材層31G之表面，第二表 面302對應於第三導電層32〇之表面。 第二基材層310可為單層絕緣基材，亦可 廣與分別設於該單層導電層相對兩表面之絕緣基材^成之 複合基材。本實施例中，第二基材層31G為單層絕緣基材， 其材質為剛性較好之材料，如選自㈣亞胺、聚四氟乙稀、 聚硫胺、聚甲基丙稀酸曱酯、聚碳酸酯、聚酿亞胺-聚乙稀_ 〇對苯二甲酯中之一種或幾種。 第三導電層320材質可為銅、銀、金或其它常見金屬， 本實施例中，其為壓延銅箔。 黏合層400用於壓合工藝中黏接第一基板2〇〇及第二 基板300,其為本領域常用之膠黏劑，如環氧樹g旨膠黏劑。 第二步，於第一導電層22〇形成第一導電線路221，並 於該第一導電線路221表面定義出貼裝區222。 ❹ 本實施例採用本領域常見工藝形成該第一導電線路 221，如於第一導電層22〇之表面貼附幹膜，然後經曝光、 顯影、钱刻工序而成。 參見圖3，其為貼裝區222相對於第一導電線路221 之位置示意圖。貼裝區222用於後續採用表面貼裝工藝將 電子元件貼裝至電路板表面，其形狀及尺寸根據實際需要 而定。本實施例中，貼裝區222呈矩形，其位於第一導電 線路221之中部。 第二步，於黏合層400開設與貼裝區222相對應之切 11 200945970 口 410。 切口 410可私用衝裁設備衝出，其可為不同形狀之通 孔’如11形、矩形或其它多邊形等。亦可將黏合層棚切 斷成尺寸較小之兩部分，使得每部分具有切割面，然後將 該兩部分之切割面相對設置但不相互接觸，由此相當於於 該兩部分之間形成切口 410。參見圖4, 士刀π 410之尺寸岸 滿足當第-導電線路221及第二基材層31〇分別緊貼黏合 層棚之相對兩表面時，貼裝@ 222相對於第二基材層31〇 之投影位於切口 410相對於第二基材層31〇之投影内。優 選地，切口 410之橫截面形狀及尺寸與貼裝區222之形狀 及尺寸匹配。本實施例中，黏合層_被切斷成相互分離 之第一黏合部420及第二黏合部43〇，且第一黏合部42〇 具有第一切割面421，第二黏合部43〇具有與第一切割面 421相對之第二切割面431。第一切割面421與第二切割面 431配合形成切口 410。 ° ❹ 第四步，提供一與貼裝區222尺寸對應之加強片5〇〇。 加強片500可直接置於切口 41〇内，亦可黏附於第二 基材310之第一表面。具體地，可先於第三導電層32〇表 面定義出標識區321，並於第二基材31〇之第一表面3〇2 與標識區321相對應處貼裝加強片5〇〇。本實施例中，加強 片500貼於第一表面302與標識區321相對應之表面處。 請一併參閱圖5至圖6’標識區321之示出需根據切口 41〇 之尺寸及形狀而定。優選地，標識區321之形狀及尺寸與 切口 410匹配。具體地，標識區421之示出可採用蝕刻第 12 200945970 三導電層320並於第三導電層320之第一表面3〇1形成標 識圖案之方式’亦可於第一表面301貼裝標識片，或以其 它常見方式示出，只要能起直觀識別作用即可。藉由設置 標識區321可直觀得出所需貼裝之加強片50〇之尺寸及定 義加強片500相對於第一表面301之位置，以便於後續於 第一表面301與該標識區221相對應處貼裝加強片5〇〇以 及後續根據標識區321除去標識區321對應之第二某材層。 加強片500用於填充切口 410，優選地，其形狀及尺寸 ©與貼裝區222及切口 410之形狀及尺寸匹配，以確保後續 第一基板200與第二基板300以第一導電線路221、第二基 材層310緊貼黏合層400相對兩表面之方式壓合後，加強 片500完全填充切口 410 ’且貼裝區222位於第一切割面 421及第二切割面431之間。 第五步，將第一基板200、黏合層400及第二基板3〇〇 依次疊層並壓合。 q 請一併參閱圖4及圖7，第一基板200、黏合層400及 第二基板300之疊層及壓合應使得第二基材層310及第一 導電線路221分別緊貼於黏合層400相對之兩表面，且貼 裝區222位於第一切割面421與第二切割面431之間，加 強片500收容於切口 410内，並與切口 410處對應之貼裝 區222相接觸。由此，切口 410被加強片500完全填充， 第二導電層230與切口 410對應之部分不再朝第二基材層 310凹陷，即，藉由設置加強片500填充切口之方式使得第 二導電層230表面平整度提高，不再存有較大落差。 13 200945970 第六步，於第二導電層230形成第二導電線路231，得 電路基板700。 參閱圖8及圖9,第二導電線路231之形成可採用蝕刻 工藝，其具體包括於第二導電層230表面貼幹膜600、曝 光、顯影、蝕刻等步驟。另外，參見圖10，於第二導電線 路231之圖案形成之前或之後，還可包括一鑽貫通第二導 電層230及第三導電層320之通孔、將通孔孔壁電鍍之步 驟，以導通第二導電層230與第三導電層320,使得第二導 ❹電層230與第三導電層320之間可達成訊號傳輸。如果通 孔孔壁電鍍工藝係於第二導電線路231之圖案形成之後進 行，則進行孔壁電鍍之前應於第二導電層230之表面貼覆 幹膜以保護線路圖案。 第七步，沿第一切割面421裁切電路板基板700。 於裁切電路板基板700前可取出加強片500,然後再沿 第一切割面421裁切電路板基板700，亦可不取出加強片 ^ 500，而直接採用切割設備裁切電路板基板700。請一併參 ❹ 閱圖11至圖13，本實施例中，裁切電路板基板700前藉由 除去標識區321對應之第三導電層，暴露出部分第二基材 層310，除去該部分第二基材層310，而取出加強片500。 參見圖11，導電層可採用蝕刻方式，亦可採用摻鈥釔 鋁石榴石Nd:YAG鐳射切割。請一併參閱圖11及圖12，該 部分第二基材層310可藉由鐳射切割去除。鐳射種類根據 第二基材層310之材質進行相應選擇。一般來說，摻鈥釔 鋁石榴石Nd:YAG鐳射器發射之鐳射波長較短，屬紫外波 14 200945970 =衝頻率較高，可用於切割導電層及絕緣層 器發射之鐳㈣紐長，射紅外波段 · 割絕緣層。當缺，亦可·、“你“ 吊僅應用於切 錯射切割導電層，即’以Nd:YAG mu 切割絕緣層。本實施例中， 一 土材層31〇為絕緣層，故以c〇2錯射進行切割即可。 當然，還可根據需要，於第三導電層32〇製作第三 ❹ =路。第三導電線路之製作可與第二導電線路231同時 製作’亦可於取出加強片5〇〇後製作。 參見圖12及圖13,沿第一切割面421 一併裁斷第一 電線路221、第-基材層21〇及第二導電線路231即可得到 具有斷差結構之電路板。 本實施例之具有斷差結構之電路板之製作方法藉由設 置加強片500填充切口 410,使得待佈線之第二導電層23〇 表面平整，避免了壓合第一基板2〇〇與第二基板3〇〇時由 於切口 410引起之第二導電層23〇沿切口 41〇凹陷產生落 ❾差，從而克服了先前技術之製作方法容易導致導電線路粗 細不一，甚至斷線之缺陷。因此，使用本技術方案之製作 方法可顯著地提尚電路板之線路製作精度及產品合格率。 綜上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限製本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化，皆 應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 15 200945970 圖la至圖le係習知斷差結構之電路板製作方法中壓 合及形成電路之示意圖。 ‘ 圖2至圖13係本技術方案之實施例提供之具有斷差結 構之電路板製作方法之示意圖。 【主要元件符號說明】 多層電路板 100 雙面基板 110 ❹單面基板 120 第一導電線路 111 、 221 貼裝區 112、222 黏合層 130、 400 切口 131 、 410 基材層 121 電路板基板 140 、 700 π導電層表面 142 ❹ 幹膜 150、600 第二導電線路 143 、 231 第一基板 200 第二基板 300 第一基材層 210 第一導電層 220 第二導電層 230 第二基材層 310 16 200945970 第三導電層 320 第一表面 301 第二表面 302 第一黏合部 420 第二黏合部 430 第一切割面 421 第二切割面 431 加強片 500 標識區 321 〇 17A composite substrate comprising a layer and an insulating substrate respectively disposed on opposite surfaces of the single-layer conductive layer. In this embodiment, the first substrate layer 21 is a single-layer insulating substrate layer, and the material thereof is a material with good flexibility, such as (IV) imine, polytetrafluoroethylene f thiamine, polymethyl One of a kind of conductive layer 220 and the first-Morexian music layer of methyl acrylate, polycarbonate, polyethylene terephthalic acid vinegar, polyimide-polyethylene _ p-benzoene @ copolymer The material of the conductive layer 230 may be copper, silver, gold or other common metals. In this embodiment, the first conductive layer 220 and the second conductive layer 230 are copper-clad boxes. The 2nd board can be a rigid substrate or a flexible substrate, and the structure is determined according to the circuit board having a faulty junction according to the actual (4) and (4). In the present embodiment, the second substrate 300 includes a first substrate layer 310 including a first substrate layer 310 and a second conductive layer 320 formed on the surface of the first substrate layer 310. a rigid substrate having a first surface 301 and a second surface 3〇2 opposite to the first surface 301. The first surface 3〇1 corresponds to the surface of the second substrate layer 31G, and the second surface 302 Corresponding to the surface of the third conductive layer 32. The second substrate layer 310 can be a single-layer insulating substrate, and can also be widely combined with the insulating substrate disposed on opposite surfaces of the single-layer conductive layer. In this embodiment, the second substrate layer 31G is a single-layer insulating substrate, and the material thereof is a material with good rigidity, such as selected from (IV) imine, polytetrafluoroethylene, polythioamide, polymethyl propylene One or more of yttrium ester, polycarbonate, poly-imine-polyethylene phthalate. The third conductive layer 320 may be made of copper, silver, gold or other common metals. In the example, it is a rolled copper foil. The adhesive layer 400 is used for bonding the first substrate 2 and the second substrate 300 in a pressing process, which is common in the art. The adhesive agent, such as an epoxy resin, is used to form a first conductive line 221 on the first conductive layer 22, and a mounting area 222 is defined on the surface of the first conductive line 221. In this embodiment, the first conductive line 221 is formed by a common process in the art, such as attaching a dry film to the surface of the first conductive layer 22, and then forming by exposure, development, and engraving. See FIG. 3, which is a sticker. The position of the loading area 222 relative to the first conductive line 221. The mounting area 222 is used for subsequently mounting the electronic component to the surface of the circuit board by using a surface mount process, and the shape and size thereof are determined according to actual needs. The mounting area 222 is rectangular and located in the middle of the first conductive line 221. In the second step, the adhesive layer 400 is provided with a cut 11 200945970 port 410 corresponding to the mounting area 222. The slit 410 can be punched by a private punching device. It can be a through hole of different shapes such as elliptical shape, rectangular shape or other polygonal shape, etc. The adhesive layer shed can also be cut into two smaller parts so that each part has a cutting surface, and then the two parts are The cutting faces are opposite but Contacting each other, thereby forming a slit 410 between the two portions. Referring to FIG. 4, the size of the shovel π 410 satisfies the first conductive line 221 and the second base layer 31 紧 closely adjacent to the adhesive layer shed. The projection of the mounting @ 222 relative to the second substrate layer 31 is located within the projection of the slit 410 relative to the second substrate layer 31 相对 on opposite surfaces. Preferably, the cross-sectional shape and size of the slit 410 and the placement The shape and size of the region 222 are matched. In this embodiment, the adhesive layer _ is cut into the first adhesive portion 420 and the second adhesive portion 43 相互 separated from each other, and the first adhesive portion 42 〇 has a first cutting surface 421 . The second bonding portion 43 has a second cutting surface 431 opposite to the first cutting surface 421. The first cutting face 421 cooperates with the second cutting face 431 to form a slit 410. ° ❹ In the fourth step, a reinforcing sheet 5〇〇 corresponding to the size of the mounting area 222 is provided. The reinforcing sheet 500 may be directly placed in the slit 41〇 or adhered to the first surface of the second substrate 310. Specifically, the identification area 321 may be defined before the third conductive layer 32 , surface, and the reinforcing sheet 5 贴 may be placed on the first surface 3 〇 2 of the second substrate 31 与 corresponding to the identification area 321 . In this embodiment, the reinforcing sheet 500 is attached to the surface of the first surface 302 corresponding to the marking area 321 . Please refer to Fig. 5 to Fig. 6' for the indication area 321 to be determined according to the size and shape of the slit 41. Preferably, the shape and size of the identification zone 321 matches the slit 410. Specifically, the marking area 421 can be formed by etching the 12th 200945970 three conductive layer 320 and forming a marking pattern on the first surface 3〇1 of the third conductive layer 320. The marking surface can also be mounted on the first surface 301. Or, in other common ways, as long as it can be visually recognized. By setting the marking area 321 , the size of the reinforcing sheet 50 所需 to be mounted can be visually obtained and the position of the reinforcing sheet 500 relative to the first surface 301 can be defined so as to be corresponding to the marking area 221 subsequent to the first surface 301 . The reinforcing sheet 5 is placed and the second certain layer corresponding to the marking area 321 is removed according to the marking area 321 . The reinforcing sheet 500 is used to fill the slit 410. Preferably, the shape and size thereof are matched with the shape and size of the mounting area 222 and the slit 410 to ensure that the first first substrate 200 and the second substrate 300 are in the first conductive line 221, After the second substrate layer 310 is pressed against the two surfaces of the adhesive layer 400, the reinforcing sheet 500 completely fills the slit 410' and the mounting region 222 is located between the first cutting surface 421 and the second cutting surface 431. In the fifth step, the first substrate 200, the adhesive layer 400, and the second substrate 3 are laminated in this order and pressed. Please refer to FIG. 4 and FIG. 7 together, the lamination and pressing of the first substrate 200, the adhesive layer 400 and the second substrate 300 are such that the second substrate layer 310 and the first conductive line 221 are respectively adhered to the adhesive layer. The two opposite surfaces of the 400 are disposed, and the mounting area 222 is located between the first cutting surface 421 and the second cutting surface 431. The reinforcing sheet 500 is received in the slit 410 and is in contact with the corresponding mounting area 222 at the slit 410. Thereby, the slit 410 is completely filled by the reinforcing sheet 500, and the portion of the second conductive layer 230 corresponding to the slit 410 is no longer recessed toward the second base material layer 310, that is, the second conductive layer is made by providing the reinforcing sheet 500 to fill the slit. The surface flatness of the layer 230 is increased, and there is no longer a large drop. 13 200945970 In the sixth step, the second conductive line 231 is formed on the second conductive layer 230 to obtain the circuit substrate 700. Referring to FIG. 8 and FIG. 9, the second conductive line 231 may be formed by an etching process, which specifically includes the steps of adhering the film 600, exposing, developing, etching, etc. to the surface of the second conductive layer 230. In addition, referring to FIG. 10, before or after the pattern formation of the second conductive line 231, a step of drilling through the via holes of the second conductive layer 230 and the third conductive layer 320 and plating the via hole walls may be further included. The second conductive layer 230 and the third conductive layer 320 are turned on, so that signal transmission can be achieved between the second conductive layer 230 and the third conductive layer 320. If the via hole wall plating process is performed after the patterning of the second conductive line 231, the dry film should be applied to the surface of the second conductive layer 230 to protect the line pattern before the hole wall plating. In the seventh step, the circuit board substrate 700 is cut along the first cutting surface 421. The reinforcing sheet 500 can be taken out before cutting the circuit board substrate 700, and then the circuit board substrate 700 can be cut along the first cutting surface 421, or the circuit board substrate 700 can be directly cut by a cutting device without taking out the reinforcing sheet ^500. Referring to FIG. 11 to FIG. 13 , in this embodiment, a portion of the second substrate layer 310 is exposed by removing the third conductive layer corresponding to the identification region 321 before cutting the circuit board substrate 700, and the portion is removed. The second substrate layer 310 is taken out and the reinforcing sheet 500 is taken out. Referring to Fig. 11, the conductive layer may be etched or ytterbium-doped aluminum garnet Nd:YAG laser cut. Referring to Figures 11 and 12 together, the portion of the second substrate layer 310 can be removed by laser cutting. The laser type is selected according to the material of the second substrate layer 310. In general, the yttrium-aluminum garnet Nd:YAG laser emits a shorter laser wavelength, which belongs to the ultraviolet wave 14 200945970 = higher punch frequency, which can be used to cut the conductive layer and the radium (four) of the insulating layer. Infrared band · Cut insulation. When it is missing, it can also be used to "cut" the conductive layer only by cutting the faulty layer, that is, cutting the insulating layer with Nd:YAG mu. In the present embodiment, a soil material layer 31 is an insulating layer, so that cutting can be performed by c〇2 misalignment. Of course, a third ❹ = way can be made on the third conductive layer 32 根据 as needed. The third conductive line can be fabricated simultaneously with the second conductive line 231. It can also be fabricated after the reinforcing sheet 5 is removed. Referring to Fig. 12 and Fig. 13, the first electric circuit 221, the first substrate layer 21, and the second conductive line 231 are collectively cut along the first cutting surface 421 to obtain a circuit board having a stepped structure. The manufacturing method of the circuit board with the fault structure of the present embodiment fills the slit 410 by providing the reinforcing sheet 500, so that the surface of the second conductive layer 23 to be wired is flat, and the first substrate 2 and the second substrate are prevented from being pressed. When the substrate 3 is turned, the second conductive layer 23 is recessed along the slit 41〇 due to the slit 410, thereby overcoming the defect that the manufacturing method of the prior art is liable to cause the thickness of the conductive line to be different or even broken. Therefore, the manufacturing method of the technical solution can significantly improve the circuit fabrication precision and product qualification rate of the circuit board. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the present invention are intended to be included within the scope of the following claims. [Simple description of the drawing] 15 200945970 Fig. la to Fig. la is a schematic diagram of the pressing and forming circuit in the circuit board manufacturing method of the conventional stepped structure. ‘FIG. 2 to FIG. 13 are schematic diagrams showing a method of fabricating a circuit board having a fault structure provided by an embodiment of the present technical solution. [Main component symbol description] Multi-layer circuit board 100 Double-sided substrate 110 ❹ Single-sided substrate 120 First conductive line 111, 221 Mounting area 112, 222 Adhesive layer 130, 400 Notch 131, 410 Substrate layer 121 Circuit board substrate 140, 700 π conductive layer surface 142 ❹ dry film 150, 600 second conductive line 143, 231 first substrate 200 second substrate 300 first substrate layer 210 first conductive layer 220 second conductive layer 230 second substrate layer 310 16 200945970 Third conductive layer 320 First surface 301 Second surface 302 First adhesive portion 420 Second adhesive portion 430 First cutting surface 421 Second cutting surface 431 Strengthening sheet 500 Identification area 321 〇 17