200945968 九、發明說明： '【發明所屬之技術領域】 ' 本發明涉及電路板製作技術領域，尤其涉及一種具有 斷差結構之電路板之製作方法。 【先前技術】 隨著電子產品日趨小型化及高速性能化，電路板表面 焊接之元件越來越多，要求電路板之導電線路密度及訊號 ©傳輸量亦越來越大。為適應此需求，電路板已從單面板發 展為雙面板及多層板。其中，雙面電路板及多層電路板具 有較多佈線面積、較高裝配密度而得到廣泛應用，參見文 獻：Takahashi, A.; High density multilayer printed circuit board for HITAC M-880; IEEE Trans, on Components, Packaging, and Manufacturing Technology; 1992 〇 作為近年來出現之一種新型多層電路板，具有斷差結 I構之電路板由於其於不同區域具有不同層數，層數少之區 ❹ 域厚度小、剛性小，層數多之區域具有高線路密度、較大 厚度及較大剛度，而具有優異之整體性能，其既可實現大 量訊號之傳輸，又具有適當之剛撓性。 參見圖la，為一種具有斷差結構之多層電路板1〇〇之 結構示意圖。該多層電路板100由一雙面基板110與一單 面基板120製成，其中，該雙面基板110之導電線路111 設有貼裝區112，用於貼裝電子元件。 目前，通常採用增層法即層層疊加法製作具有斷差結 200945968 構之電路板。以多層電路板100為例，其習知之製作方法 包括：首先’提供雙面基板110、單面基板120及黏合層 130 ’請一併參閱圖la及圖lb ’該雙面基板no之一表面 形成有導電線路111 ’該黏合層130設有與貼裝區112尺寸 對應之切口 131’該單面基板120包括基材層121及導電層 122 ;其次’請參見圖lc ’利用黏合層130將單面基板120 之基材層121壓合到雙面基板11〇之導電線路in表面， 且使切口 131與貼裝區112相對，採用雷射切割設備或銑 ®刀切割掉單面基板120之導電層122及基材層121與切口 131對應之部分，從而使得貼裝區112外露；最後，於單面 基板120之剩餘導電層形成導電線路。當然，還可包括製 作貫通單面基板120與雙面基板no之導通孔以及電鍵該 導通孔孔壁等步驟。 然而，當單面基板120為硬板時，採用上述製作方法 存在以下兩弊端：（1)由於基材層121材質多為由網狀玻 ❹璃纖維及聚合物樹脂組成之複合材料，造成單面基板120 表面平整度較差’各處厚度相差較大。當採用雷射去除單 面基板120與切口 131對應之部分導電層122及部分基材 層121時’由於單面基板12〇表面不平整導致厚度差異， 使得單面基板120各處需要不同切割能量，而雷射切割工 藝採用某一確定能量進行切割，因此各處之切割深度將不 同’很可能發生切割過度，即將雙面基板11〇之貼裝區n2 對應之部分導電線路ln切斷。即使改用銑刀切割，仍會 因單面基板120之各處厚度不一，難以掌握銑刀插入深度， 8 200945968 同樣知傷雙面基板110之貼裝區112對應之導電線路ιη。 (2)貝占裝區112無任何防s，當於單面基板12〇之剩餘導 電層形成導電線路時n夜極易掉至貼裝區112内而腐 蝕貼裝區112内之導電線路U1。 有鑑於此，提供一種具有斷差結構之電路板之製作方 法，以提高電路板之製作精度及產品合格率實為必要。 【發明内容】 ❹一種具有斷差結構之電路板之製作方法，其包括下述 步驟.提供第一基板、黏合層、隔離層及第二基板，該第 一基板包括第一基材層、形成於第一基材層至少一表面之 導電線路層，該導電線路層設有貼裝區，該第二基板包括 第一基材層及开> 成於該第二基材層至少一表面之導電層； 將隔離層黏貼至第-基板之導電線路層，使其完全覆蓋貼 裝區，將第二基板切斷成複數基板段；依次疊層並壓合貼 ❹有隔離層之第一基板、黏合層及第二基板，且使該隔離層 及第二基材層分別貼於黏合層之相對兩表面，貼裝區於第 一基材層之投影位於至少一基板段於第一基材層之投影 内；去除該至少一基板段及與貼裝區對應之黏合層及隔離 層’從而製得具有斷差結構之電路板。 與先前技術相比，本技術方案之具有斷差結構之電路 板之製作方法採用隔離層保護貼裝區之導電線路並於壓合 第基板及第二基板前將第一基板切斷成含有與貼裝區尺 寸及形狀匹配之第二基板，一方面可避免採用蝕刻法於第 9 200945968 二基板之導電層形成導電線路或對貫通第一基板之第二導 電層及第二基板之導電層之導通孔孔壁進行電鍍時藥水或 電鍍液腐蝕該部分之導電線路，另一方面使得於壓合第一 基板及第二基板後去除第二基板及與貼裝區對應之黏合層 及隔離層時，由於該部分黏合層及隔離層分別由同一種材 料製成，各處厚度一致，因而容易控製切割深度，避免切 割過度而損傷貼裝區内之導電線路。因此，使用本技術方 案之具有斷差結構之電路板之製作方法能提高電路板之製 ®作精度及產品合格率。 【實施方式】 以下將結合實施例及附圖對本技術方案提供之具有斷 差結構之電路板之製作方法進行詳細說明。 本實施例提供之具有斷差結構之電路板之製作方法包 括以下步驟： ^ 第一步，提供第一基板200、第二基板300、黏合層400 及隔離層500。 請參閱圖2,第一基板200為包括至少一層導電線路之 軟基板或硬基板，其可為單面板、雙面板或多層板，其具 體結構依待製作之具有斷差結構之電路板之具體結構而 定。本實施例中，第一基板200為一雙面軟板，其包括第 一基材層210及分別位於第一基材層210相對兩表面之導 電線路層220及第一導電層230。當然，可直接提供雙面覆 銅基材，然後採用本領域常見工藝形成該導電線路層220， 200945968 如於該雙面覆銅基材之一面銅箔表面貼附幹膜，然後經曝 光、顯影、蝕刻工序形成導電線路層220。 導電線路層220表面設有貼裝區221。貼裝區221用於 後續採用表面貼裝工藝將電子元件貼裝至電路板表面，其 形狀及尺寸根據實際需要而定，其可設於導電線路層220 之端部，亦可設於導電線路層220之中部。本實施例中， 貼裝區221位於導電線路層220之中部，其對應導電線路 層 220a 。 ® 第一基材層210可為單層絕緣基材，亦可為單層導電 線路層與絕緣基材構成之複合基材。本實施例中，第一基 材層210為單層絕緣基材層。 導電線路層220及第一導電層230之材質可為銅、銀、 金或其它常見金屬。本實施例中，導電線路層220及第一 導電層230為壓延銅箔。 第二基板300可為硬基板，亦可為軟基板，可為單面 _板、雙面板或多層板，其結構根據實際需製作之具有斷差 結構之電路板而定。本實施例中，第二基板300為一單面 硬板，其包括第二基材層310及形成於第二基材層310 — 表面之第二導電層320,其具有第一表面301及與第一表面 301相對之第二表面302。其中，第一表面301對應於第二 基材層310之表面，第二表面302對應於第二導電層320 之表面。 第二基材層310可為單層絕緣基材，亦可為單層導電 線路層與絕緣基材構成之複合基材。本實施例中，第二基 11 200945968 材層310為單層絕緣樹脂與玻璃纖維之複合絕緣基材。 第二導電層320材質可為銅、銀、金或其它常見金屬， 本實施例中，其為壓延銅箔。 黏合層400為本領域常用之黏接劑，如環氧樹酯黏接 劑，其用於後續鋪設於第二基板300之第二基材層310表 ， 面，以黏接第二基板300於隔離層500。 隔離層500用於完全覆蓋貼裝區221内之導電線路層 220a，以避免後續採用蝕刻法於第二基板300之第二導電 ®層320形成導電線路時或對貫通第一基板200之第一導電 層230及第二基板300之第二導電層320之導通孔孔壁進 行電鍍藥水或電鍍液腐蝕該部分之導電線路層220a»隔離 層500可係本領域常用之加強片，即層狀聚合物樹脂，亦 可係本領域常用之覆蓋膜，還可係由加強片與黏合層之組 合體。本實施例中，隔離層500為兩層覆蓋膜之疊合體。 請一併參見圖2及圖3,本實施例之隔離層500之製作 ❹包括以下步驟：首先，提供第一覆蓋膜510，其可為本領域 常規覆蓋膜，如聚醯亞胺覆蓋膜，其包括基材層511、黏接 劑層512及離型紙513。其次，於黏接劑層512標識出貼合 區5121，貼合區5121之示出可採用雷射切斷部分離型紙 513，然後撕去該部分被切斷之離型紙，暴露出對應之部分 黏接劑層512’該部分黏接劑層之表面即為貼合區5121。 最後’提供結構與第一覆蓋膜510相同、尺寸及形狀與該 貼合區5121匹配之第二覆蓋膜520。將該第二覆蓋膜520 之離型紙（圖未示）撕去，將第二覆蓋膜520之黏接劑層 12 200945968 512與第一覆蓋膜510之黏接劑層512黏接，使第二覆蓋膜 520黏貼至貼合區5121，最後撕去第一覆蓋膜510之剩餘 離型紙513即可得到隔離層500。 貼合區5121之形狀及尺寸視實際需要而定，優選地， 貼合區5121之形狀及尺寸與貼裝區221之形狀及尺寸匹 配，即，第二隔離膜520之形狀及尺寸與貼裝區221之形 狀及尺寸匹配，以利於後續能完全覆蓋貼裝區221對應之 導電線路層220a。 ® 第二步，將隔離層500黏貼至第一基板200之導電線 路層220，使其完全覆蓋貼裝區221。 請一併參見圖2及圖4’隔離層500相對於導電線路層 220之位置應滿足其剛好能完全覆蓋貼裝區221。具體地， 隔離層500黏貼至第一基板200後應使第二隔離膜520於 導電線路層220之投影與貼裝區221於導電線路層220之 投影重合。第二隔離膜520之基材層511與貼裝區221接 ϋ觸，第一隔離膜510之黏接劑層512與貼裝區221外之導 電線路接觸並黏接。 第三步，將第二基板300切斷成複數基板段。 請參見圖5，本實施例中，沿第一切割面303及與第一 切割面303平行之第二切割面304切割第二基板300,由此 將其切斷成相互獨立之三段，即基板段300a、基板段300b 及基板段300c。其中，位於第一切割面303與第二切割面 304之間之基板段300c之尺寸大於或等於貼裝區221之尺 寸。優選地，基板段300c之尺寸及形狀與貼裝區221之尺 13 200945968 寸及形狀匹配。當然，還可將第二基板300切割成更多小 尺寸基板段，利用複數小尺寸基板段構成基板段300c。 第四步，依次層疊並壓合貼合有隔離層500之第一基 板200、黏合層400及第二基板300。 請一併參閱圖4至圖6,第一基板200、黏合層400及 第二基板300之壓合應使隔離層500及基板段300a、300b 及300c之第二基材層310分別對應地貼合於黏合層400之 相對兩表面’基板段300c之兩端分別與基板段300a及基 ®板段300b接觸’且其於第一基材層210之投影與貼裝區221 於第一基材層210之投影重合。當基板段300c之尺寸大於 貼裝區221尺寸時，應使基板段300c於第一基材層210之 投影完全覆蓋貼裝區221於第一基材層210之投影，以利 於後續去除基板段300c及與貼裝區221相對之隔離體後， 貼裝區221對應之導電線路外露出來而不被基板段3〇〇a及 基板段300b遮住。 0 第五步’去除基板段300c、與基板段300c對應之黏合 層400及隔離層500。 請一併參閱圖6至圖8,由於第二基板300於壓合前已 被切割成獨立之三段，且基板段3〇〇c之尺寸及形狀與貼裝 區221之形狀及尺寸匹配，而黏合層4〇〇及隔離層5〇〇分 別由同一種材料製成’質地均勻，各處厚度一致，需要之 切割能量相同，因此’採用常用雷射切割設備沿著基板段 300c之邊界即第一切割面303及第二切割面304切割黏合 層400及隔離層500時容易藉由控製切割能量而控製切割 200945968 深度，由此可輕易地去除基板段300c，然後繼續沿第一切 割面303及第二切割面304切割即可去除與貼裝區221對 應之黏合層400及隔離層500，從而避免切割過度，進而避 免損傷貼裝區221内之導電線路。 當然，本實施例之具有斷差結構之電路板之製作方法 還可包括以下步驟：於去除基板段300c及與貼裝區221對 應之黏合層400及隔離層500前於第一基板200之第一導 電層230形成導電線路；製作貫通第一基板200之第一導 〇電層230及第二基板300之第二導電層320之導通孔；去 除基板段300c、與基板段300c對應之黏合層400及隔離層 500後平壓基板段300a及300b使該兩基板段表面平整，再 於該兩基板段300a、300b之導電層表面形成導電線路。 與先前技術相比，本實施例之具有斷差結構之電路板 之製作方法採用隔離層500保護貼裝區221之導電線路並 於壓合第一基板200及第二基板300前將第一基板200切 φ斷成含有與貼裝區尺寸及形狀匹配之基板段300c，使得於 壓合第一基板200及第二基板300後去除基板段300c及與 貼裝區221對應之黏合層400及隔離層500時，由於該部 分黏合層400及隔離層500分別由同一種材料製成，各處 厚度一致，因而容易控製切割深度。另外，本實施例之製 作方法採用隔離層500覆蓋貼裝區221對應之導電線路， 防止了採用蝕刻法於第二基板120之第二導電層320形成 導電線路或對貫通第一基板200之第一導電層230及第二 基板300之第二導電層320之導通孔孔壁進行電鍍時藥水 15 200945968 或電鍍液腐蝕該部分之導電線路221。因此，使用本實施例 之具有斷差結構之電路板之製作方法能提高電路板之製作 精度及產品合格率。 綜上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限製本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化，皆 應涵蓋於以下申請專利範圍内。 ©【圖式簡單說明】 圖la係先前技術之一種具有斷差結構之軟硬結合板之 結構示意圖。 圖lb係製作圖la所示軟硬結合板之第一基板、第二 基板及黏合層之結構示意圖。 圖lc係具有斷差結構之電路板之習知製作方法切割第 一基板之示意圖。 ^ 圖2係本技術方案之具有斷差結構之電路板之製作方 法實施例提供之第一基板、第二基板、黏合層及隔離層之 結構示意圖。 圖3係圖2所示之隔離層之製作示意圖。 圖4係圖2所示隔離層與圖2所示之第一基板壓合示 意圖。 圖5係切斷圖2所示之第二基板之示意圖。 圖6係隔離層與第一基板及切斷後之第二基板壓合後 之示意圖。 16 200945968 圖7係圖6所示結構去除與貼裝區對應後之基板段之 示意圖。 圖8本技術方案實施例製作之具有斷差結構之電路板 之示意圖。 【主要元件符號說明】 100 110 120 111200945968 IX. Description of the invention: '[Technical field to which the invention pertains] The present invention relates to the field of circuit board manufacturing technology, and more particularly to a method of fabricating a circuit board having a stepped structure. [Prior Art] With the increasing miniaturization and high-speed performance of electronic products, more and more components are soldered on the surface of the board, and the conductive line density and signal transmission of the board are required to be larger. To meet this need, boards have evolved from single-panel to dual-panel and multi-layer boards. Among them, the double-sided circuit board and the multi-layer circuit board have a large wiring area and a high assembly density and are widely used, see the literature: Takahashi, A.; High density multilayer printed circuit board for HITAC M-880; IEEE Trans, on Components As a new type of multi-layer circuit board that has emerged in recent years, a circuit board with a faulty junction I structure has different layers in different regions, and a small number of layers has a small thickness and rigidity. The small, multi-layer area has high line density, large thickness and large rigidity, and has excellent overall performance, which can realize a large number of signal transmission and appropriate rigidity. Referring to Fig. la, it is a schematic structural view of a multilayer circuit board having a stepped structure. The multilayer circuit board 100 is formed by a double-sided substrate 110 and a single-sided substrate 120. The conductive line 111 of the double-sided substrate 110 is provided with a mounting area 112 for mounting electronic components. At present, a circuit board having a fault junction 200945968 is usually fabricated by a layer-up method, that is, a layer stacking method. Taking the multilayer circuit board 100 as an example, the conventional manufacturing method includes: firstly providing a double-sided substrate 110, a single-sided substrate 120, and an adhesive layer 130. Please refer to FIG. 1 and FIG. 1b for the surface of the double-sided substrate no. The conductive layer 111 is formed. The adhesive layer 130 is provided with a slit 131' corresponding to the size of the mounting region 112. The single-sided substrate 120 includes a substrate layer 121 and a conductive layer 122. Secondly, please refer to FIG. The substrate layer 121 of the single-sided substrate 120 is pressed onto the surface of the conductive line in of the double-sided substrate 11 and the slit 131 is opposed to the mounting area 112, and the single-sided substrate 120 is cut by a laser cutting device or a milling cutter. The conductive layer 122 and the portion of the substrate layer 121 corresponding to the slit 131 are such that the mounting region 112 is exposed; finally, the conductive layer is formed on the remaining conductive layer of the single-sided substrate 120. Of course, it is also possible to include a step of forming a via hole penetrating the one-sided substrate 120 and the double-sided substrate no, and electrically connecting the via hole. However, when the single-sided substrate 120 is a hard board, the following manufacturing methods have the following two disadvantages: (1) Since the material of the base material layer 121 is mostly a composite material composed of a mesh glass fiber and a polymer resin, The surface of the surface substrate 120 is poor in flatness, and the thickness varies greatly from place to place. When a portion of the conductive layer 122 and a portion of the substrate layer 121 corresponding to the single-sided substrate 120 and the slit 131 are removed by laser, the thickness difference is caused by the unevenness of the surface of the single-sided substrate 12, so that different cutting energy is required everywhere in the single-sided substrate 120. The laser cutting process uses a certain energy to cut, so the cutting depth will be different everywhere. It is very likely that the cutting is excessive, that is, the part of the conductive line ln corresponding to the mounting area n2 of the double-sided substrate 11 is cut. Even if the cutter is used for cutting, the thickness of each side of the single-sided substrate 120 is different, and it is difficult to grasp the depth of insertion of the cutter. 8 200945968 The conductive line corresponding to the mounting area 112 of the double-sided substrate 110 is also damaged. (2) The Baccarat loading area 112 does not have any anti-s. When the conductive layer is formed on the remaining conductive layer of the single-sided substrate 12〇, it is easy to fall into the mounting area 112 at night and corrode the conductive line U1 in the mounting area 112. . In view of the above, it is necessary to provide a method for fabricating a circuit board having a stepped structure to improve the fabrication precision and product qualification rate of the circuit board. SUMMARY OF THE INVENTION A method for fabricating a circuit board having a stepped structure includes the steps of providing a first substrate, an adhesive layer, an isolation layer, and a second substrate, the first substrate including a first substrate layer and forming a conductive circuit layer on at least one surface of the first substrate layer, the conductive circuit layer is provided with a mounting region, the second substrate includes a first substrate layer and an opening is formed on at least one surface of the second substrate layer a conductive layer; bonding the isolation layer to the conductive circuit layer of the first substrate, completely covering the mounting area, cutting the second substrate into a plurality of substrate segments; sequentially laminating and pressing the first substrate with the isolation layer The adhesive layer and the second substrate are respectively adhered to the opposite surfaces of the adhesive layer, and the projection of the mounting region on the first substrate layer is located on at least one substrate segment on the first substrate In the projection of the layer; removing the at least one substrate segment and the adhesive layer and the isolation layer corresponding to the mounting region to thereby obtain a circuit board having a stepped structure. Compared with the prior art, the method for manufacturing a circuit board having a fault structure of the present invention uses an isolation layer to protect the conductive line of the mounting area and cut the first substrate into a containing and before pressing the first substrate and the second substrate. The second substrate with the matching size and shape of the mounting area can avoid the formation of a conductive line by the etching method on the conductive layer of the second substrate of the 9th 200945968 or the conductive layer of the second conductive layer and the second substrate penetrating the first substrate. When the wall of the via hole is plated, the syrup or plating solution etches the conductive line of the portion, and on the other hand, when the first substrate and the second substrate are pressed, the second substrate and the adhesive layer and the isolation layer corresponding to the mounting area are removed. Since the part of the adhesive layer and the isolation layer are respectively made of the same material and have the same thickness everywhere, it is easy to control the cutting depth and avoid excessive cutting and damage the conductive lines in the mounting area. Therefore, the manufacturing method of the circuit board having the hysteresis structure using the present technology can improve the precision and product yield of the board. [Embodiment] Hereinafter, a method of manufacturing a circuit board having a hysteresis structure provided by the present technical solution will be described in detail with reference to the embodiments and the accompanying drawings. The manufacturing method of the circuit board having the fault structure provided by this embodiment includes the following steps: ^ In the first step, the first substrate 200, the second substrate 300, the adhesive layer 400, and the isolation layer 500 are provided. Referring to FIG. 2, the first substrate 200 is a soft substrate or a hard substrate including at least one conductive line, which may be a single-panel, double-panel or multi-layer board, and the specific structure thereof depends on the specific circuit board to be fabricated with a fault structure. The structure depends. In this embodiment, the first substrate 200 is a double-sided flexible board, and includes a first substrate layer 210 and a conductive layer 220 and a first conductive layer 230 respectively located on opposite surfaces of the first substrate layer 210. Of course, the double-sided copper-clad substrate can be directly provided, and then the conductive circuit layer 220 is formed by a common process in the art. 200945968 A dry film is attached to the surface of the copper foil of the double-sided copper-clad substrate, and then exposed and developed. The etching process forms the conductive wiring layer 220. A mounting area 221 is disposed on the surface of the conductive circuit layer 220. The mounting area 221 is used for subsequently mounting the electronic component to the surface of the circuit board by using a surface mount process. The shape and size thereof are determined according to actual needs, and may be disposed at the end of the conductive circuit layer 220 or on the conductive line. The middle of layer 220. In this embodiment, the mounting area 221 is located in the middle of the conductive circuit layer 220, which corresponds to the conductive wiring layer 220a. The first substrate layer 210 may be a single-layer insulating substrate or a composite substrate composed of a single-layer conductive circuit layer and an insulating substrate. In this embodiment, the first substrate layer 210 is a single-layer insulating substrate layer. The material of the conductive circuit layer 220 and the first conductive layer 230 may be copper, silver, gold or other common metals. In this embodiment, the conductive circuit layer 220 and the first conductive layer 230 are rolled copper foil. The second substrate 300 may be a hard substrate or a soft substrate, and may be a single-sided board, a double-sided board or a multi-layer board, and the structure thereof is determined according to a circuit board having a fault structure which is actually required to be fabricated. In this embodiment, the second substrate 300 is a single-sided hard board including a second substrate layer 310 and a second conductive layer 320 formed on the surface of the second substrate layer 310, having a first surface 301 and The first surface 301 is opposite the second surface 302. The first surface 301 corresponds to the surface of the second substrate layer 310, and the second surface 302 corresponds to the surface of the second conductive layer 320. The second substrate layer 310 may be a single-layer insulating substrate or a composite substrate composed of a single-layer conductive circuit layer and an insulating substrate. In this embodiment, the second base 11 200945968 material layer 310 is a composite insulating substrate of a single layer of insulating resin and glass fiber. The second conductive layer 320 may be made of copper, silver, gold or other common metals. In this embodiment, it is a rolled copper foil. The adhesive layer 400 is an adhesive commonly used in the art, such as an epoxy resin adhesive, which is used for subsequent deposition on the surface of the second substrate layer 310 of the second substrate 300 to adhere the second substrate 300. The isolation layer 500. The isolation layer 500 is used to completely cover the conductive circuit layer 220a in the mounting region 221 to avoid the subsequent etching of the second conductive layer 320 of the second substrate 300 to form a conductive line or the first through the first substrate 200. The conductive layer 230 and the via hole wall of the second conductive layer 320 of the second substrate 300 are plated with a plating solution or a plating solution to etch the portion of the conductive circuit layer 220a. The isolation layer 500 may be a reinforcing sheet commonly used in the art, that is, layered polymerization. The resin may also be a cover film commonly used in the art, or may be a combination of a reinforcing sheet and an adhesive layer. In this embodiment, the isolation layer 500 is a laminate of two layers of cover films. Referring to FIG. 2 and FIG. 3 together, the fabrication of the isolation layer 500 of the present embodiment includes the following steps: First, a first cover film 510 is provided, which can be a conventional cover film in the field, such as a polyimide film. It includes a substrate layer 511, an adhesive layer 512, and a release paper 513. Next, the bonding area 5121 is identified on the adhesive layer 512, and the laser cutting part separation type paper 513 can be used for the bonding area 5121, and then the part of the cut-off type paper is torn off, and the corresponding part is exposed. The surface of the adhesive layer 512' is a bonding area 5121. Finally, a second cover film 520 having the same structure, size and shape as the first cover film 510 and matching the bonding area 5121 is provided. The release paper (not shown) of the second cover film 520 is peeled off, and the adhesive layer 12 200945968 512 of the second cover film 520 is bonded to the adhesive layer 512 of the first cover film 510 to make a second The cover film 520 is adhered to the bonding area 5121, and finally the remaining release paper 513 of the first cover film 510 is peeled off to obtain the isolation layer 500. The shape and size of the bonding area 5121 are determined according to actual needs. Preferably, the shape and size of the bonding area 5121 are matched with the shape and size of the mounting area 221, that is, the shape and size of the second isolation film 520 and the mounting. The shape and size of the region 221 are matched to facilitate subsequent coverage of the conductive layer 220a corresponding to the mounting region 221. In the second step, the isolation layer 500 is adhered to the conductive wiring layer 220 of the first substrate 200 so as to completely cover the mounting region 221. Please refer to FIG. 2 and FIG. 4'. The position of the isolation layer 500 relative to the conductive circuit layer 220 should be such that it can completely cover the mounting area 221. Specifically, after the isolation layer 500 is adhered to the first substrate 200, the projection of the second isolation film 520 on the conductive circuit layer 220 and the projection of the mounting region 221 on the conductive circuit layer 220 should be coincident. The substrate layer 511 of the second isolation film 520 is in contact with the mounting area 221, and the adhesive layer 512 of the first isolation film 510 is in contact with and adhered to the conductive lines outside the mounting area 221. In the third step, the second substrate 300 is cut into a plurality of substrate segments. Referring to FIG. 5, in the embodiment, the second substrate 300 is cut along the first cutting surface 303 and the second cutting surface 304 parallel to the first cutting surface 303, thereby cutting the three substrates into three independent segments, namely The substrate segment 300a, the substrate segment 300b, and the substrate segment 300c. The size of the substrate segment 300c between the first cutting surface 303 and the second cutting surface 304 is greater than or equal to the size of the mounting region 221 . Preferably, the size and shape of the substrate segment 300c matches the size of the mounting area 221 and the shape of the surface. Of course, the second substrate 300 can also be cut into more small-sized substrate segments, and the substrate segments 300c can be formed by a plurality of small-sized substrate segments. In the fourth step, the first substrate 200, the adhesive layer 400, and the second substrate 300 to which the isolation layer 500 is bonded are laminated and pressed in this order. Referring to FIG. 4 to FIG. 6 , the first substrate 200 , the adhesive layer 400 and the second substrate 300 are pressed together so that the isolation layer 500 and the second substrate layer 310 of the substrate segments 300 a , 300 b and 300 c are respectively correspondingly attached. The opposite ends of the adhesive layer 400 are bonded to the substrate segment 300a and the base plate segment 300b, respectively, and the projection and mounting region 221 of the first substrate layer 210 is on the first substrate. The projections of layer 210 coincide. When the size of the substrate segment 300c is larger than the size of the mounting region 221, the projection of the substrate segment 300c on the first substrate layer 210 should completely cover the projection of the mounting region 221 on the first substrate layer 210, so as to facilitate subsequent removal of the substrate segment. After the 300c and the spacer opposite to the mounting area 221, the corresponding conductive lines of the mounting area 221 are exposed without being covered by the substrate segments 3a and 300b. The fifth step ' removes the substrate segment 300c, the adhesive layer 400 corresponding to the substrate segment 300c, and the isolation layer 500. Referring to FIG. 6 to FIG. 8 , since the second substrate 300 has been cut into three independent segments before pressing, and the size and shape of the substrate segment 3 〇〇 c are matched with the shape and size of the mounting region 221 , The adhesive layer 4〇〇 and the isolation layer 5〇〇 are respectively made of the same material, the texture is uniform, the thickness is uniform everywhere, and the cutting energy is required to be the same, so 'the common laser cutting device is used along the boundary of the substrate segment 300c. When the first cutting surface 303 and the second cutting surface 304 cut the adhesive layer 400 and the isolation layer 500, it is easy to control the cutting depth of the 200945968 by controlling the cutting energy, thereby easily removing the substrate segment 300c and then continuing along the first cutting surface 303. And the second cutting surface 304 is cut to remove the adhesive layer 400 and the isolation layer 500 corresponding to the mounting area 221, thereby avoiding excessive cutting, thereby avoiding damage to the conductive lines in the mounting area 221. Of course, the method for fabricating the circuit board having the stepped structure of the present embodiment may further include the steps of: removing the substrate segment 300c and the bonding layer 400 and the isolation layer 500 corresponding to the mounting region 221 before the first substrate 200 A conductive layer 230 forms a conductive line; a via hole penetrating through the first conductive layer 230 of the first substrate 200 and the second conductive layer 320 of the second substrate 300; and removing the substrate segment 300c and the adhesive layer corresponding to the substrate segment 300c After the 400 and the spacer 500 are pressed, the substrate segments 300a and 300b are flattened to form a conductive line on the surface of the conductive layer of the two substrate segments 300a and 300b. Compared with the prior art, the manufacturing method of the circuit board with the fault structure of the embodiment uses the isolation layer 500 to protect the conductive lines of the mounting area 221 and the first substrate before pressing the first substrate 200 and the second substrate 300. The 200-cut φ is broken into a substrate segment 300c matching the size and shape of the mounting region, so that the substrate segment 300c and the adhesive layer 400 corresponding to the mounting region 221 are removed after the first substrate 200 and the second substrate 300 are pressed together, and the isolation layer 400 is isolated. In the case of the layer 500, since the partial adhesive layer 400 and the isolation layer 500 are respectively made of the same material and have uniform thicknesses, it is easy to control the cutting depth. In addition, the manufacturing method of the embodiment uses the isolation layer 500 to cover the conductive lines corresponding to the mounting region 221, thereby preventing the formation of the conductive lines on the second conductive layer 320 of the second substrate 120 by etching or the first through the first substrate 200. The conductive via 230 and the via hole wall of the second conductive layer 320 of the second substrate 300 are plated with the syrup 15 200945968 or the plating solution etches the conductive trace 221 of the portion. Therefore, the fabrication method of the circuit board having the step-difference structure of the present embodiment can improve the fabrication precision and product yield of the circuit board. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the present invention are intended to be included within the scope of the following claims. © [Simple description of the drawing] Fig. la is a schematic structural view of a soft and hard bonding board having a sectional structure in the prior art. Figure lb is a schematic view showing the structure of the first substrate, the second substrate and the adhesive layer of the soft and hard bonding board shown in Figure la. Figure lc is a schematic view showing a conventional substrate for cutting a first substrate by a circuit board having a stepped structure. FIG. 2 is a schematic structural view of a first substrate, a second substrate, an adhesive layer, and an isolation layer provided by a method for fabricating a circuit board having a fault structure according to the present invention. Figure 3 is a schematic view showing the fabrication of the isolation layer shown in Figure 2. Figure 4 is a schematic illustration of the spacer layer shown in Figure 2 in press-fit with the first substrate shown in Figure 2. Fig. 5 is a schematic view showing the second substrate shown in Fig. 2 cut away. Fig. 6 is a schematic view showing the spacer layer being pressed against the first substrate and the second substrate after the cutting. 16 200945968 FIG. 7 is a schematic view showing the structure of the substrate shown in FIG. 6 after removing the substrate segment corresponding to the mounting area. FIG. 8 is a schematic diagram of a circuit board having a stepped structure fabricated by an embodiment of the present technical solution. [Main component symbol description] 100 110 120 111
多層電路板 雙面基板 基板 導電線路 112 ' 221 130 ' 400 131 121 、 511 122 200 300 500 210 220 、 220a 230 310 320 301 貼裝區 黏合層 切口 基材層 導電層 第一基板 第二基板 隔離層 第一基材層 導電線路層 第一導電層 第二基材層 第二導電層 第一表面 17 200945968 第二表面 302 第一覆蓋膜 510 黏接劑層 512 離型紙 513 貼合區 5121 第二覆蓋膜 520 第一切割面 303 第二切割面 304 ©基板段 300a、300b ' 300c ❿ 18Multilayer circuit board double-sided substrate substrate conductive line 112 '221 130 '400 131 121 , 511 122 200 300 500 210 220 , 220a 230 310 320 301 mounting area adhesive layer slit substrate layer conductive layer first substrate second substrate isolation layer First substrate layer conductive layer first conductive layer second substrate layer second conductive layer first surface 17 200945968 second surface 302 first cover film 510 adhesive layer 512 release paper 513 bonding area 5121 second cover Film 520 first cutting surface 303 second cutting surface 304 © substrate segments 300a, 300b ' 300c ❿ 18