1358977 九、發明說明： '【發明所屬之技術領域】 * 本發明涉及電路板製作技術領域，尤其涉及一種具有 斷差結構之電路板之製作方法。 【先前技術】 隨著電子產品日趨小型化及高速性能化，電路板表面 焊接之元件越來越多，要求電路板之導電線路密度及訊號 •傳輸量亦越來越大。為適應此需求，電路板已從單面板發 展為雙面板及多層板。其中，雙面電路板及多層電路板具 有較多佈線面積、較高裝配密度而得到廣泛應用，參見文 獻：Takahashi，A.; High density multilayer printed circuit board for HITAC M-880; IEEE Trans, on Components, Packaging, and Manufacturing Technology; 1992 ° 作為近年來出現之一種新型多層電路板，具有斷差結 構之電路板由於其於不同區域具有不同層數，層數少之區 域厚度小、剛性小，層數多之區域具有高線路密度、較大 厚度及較大剛度，而具有優異之整體性能，其既可達成大 量訊號之傳輸，又具有適當之剛撓性。 參見圖la，為一種具有斷差結構之多層電路板100之 結構示意圖。該多層電路板100由一雙面基板110與一單 面基板120製成，其中，該雙面基板110之第一導電線路 111表面設有用於封裝電子元件之貼裝區112。 目前，通常採用增層法即層層疊加法製作具有斷差結 1358977 構之電路板。以多層電路板100為例，其習知之製作方法 包括：首先，提供雙面基板110、單面基板120及黏合層 130，請一併參閱圖la及圖lb，該雙面基板110之第一表 面為導電線路層111，該黏合層130設有與貼裝區112尺寸 對應之切口 131;其次，請參見圖lc，利用黏合劑層130 將單面基板120之基材層121壓合到雙面基板110之第一 導電線路層111表面，由此得到電路板基板140 ;再次，參 見圖Id及圖le，於電路板基板140之外層導電層表面142 •鋪設幹膜150，採用曝光、顯影、蝕刻法製作第二導電線路 143等步驟。 然而，當雙面基板110為柔性電路基板時，由於具有 較好之撓曲性及延展性，其與單面基板120塵合時，切口 131對應處之雙面基板將朝單面基板120凹陷，引起貼附於 該處之幹膜結構發生彎曲，當曝光、顯影及蝕刻線路時， 由於切口 131對應處之幹膜150向單面基板120凹陷，將 φ引起後續藉由曝光、顯影、蝕刻導電層工藝製得之第二導 電線路143粗細不一，甚至斷線，極大地影響電路板之線 路精度及產品合格率。 有鑑於此，提供一種具有斷差結構之電路板之製作方 法，以提高電路板之製作精度及合格率實為必要。 【發明内容】 一種具有斷差結構之電路板之製作方法，其包括下述 步驟：提供第一基板、黏合層及第二基板，該第一基板包 1358977 括第A材層形成於第一基材層相對兩表面之第一導 層及第二導電層，該第二基板包括第二基材層及形成於該 第一基材層表面之第三導電層；於第-導電層形成第一導 電線路’並於該第-導電線路表面定義出貼裝區；於該黏 合層設置貫通其相對兩表面之切口’由此使得黏合層具有 第切割面及與第-切割面相對之第二切割面；提供與貼 裝區尺寸對應之加強片；將第一基板、黏合層及第二基板 依次疊層並壓合，且使該第一導電線路及第二基材層分別 緊貼於黏合層之相對兩表面，該貼裝區位於第一切割面與 第二切割面之間，該加強片收容於切口；於第二導電層形 成第二導電線路，得電路基板；沿第一切割面裁斷該電路 基板，由此製得具有斷差結構之電路板。 本技術方案提供之具有斷差結構之電路板之製作方法 藉由於黏合層設置與貼裝區尺寸匹配之切口，利用該具有 切口之黏合層黏合第一基板及第二基板，再採用加強片填 馨充切口’使得外層待佈線之導電層表面平整，避免了壓合 第一基板與苐二基板時由於切口引起之外層導電層向切口 凹陷產生落差，從而克服了先前技術之製作方法容易導致 導電線路粗細不一’甚至斷線之缺陷。因此，使用本技術 方案之製作方法可顯著地提高電路板之線路製作精度及產 品合格率。 【實施方式】 以下將結合實施例及附圖對本技術方案提供之具有斷 丄乃8977 差結構之電路板之製作方法進行詳細說明。 括例提供之具有斷差結構之電路板之製作方法包 4〇〇 第一步，提供第-基板施、第二基板3⑽及黏合層 凊參閱圖2’第一基板2〇〇為包括至少兩層導電層之柔 體Γ構依待製作之具有斷差結構之電路板: :體…構而疋。本實施例中，第—基板·為—柔性雙面 :銅層壓板’其包括第一基材層21〇及分別位於第一基材 層210相對兩表面之第一導電層220及第二導電層23〇。 第基材層210可為單層絕緣基材，亦可為單層導電 層與分別設於該單層導電層相對兩表面之絕緣基材構成之 ^合基材。本實施例巾，第—基材層細為單層絕緣基材 :，其材質為柔動性較好之材料，如選自聚醯亞胺、聚四 烯、聚硫胺、”基丙烯酸甲醋、聚碳酸醋、聚乙烯 對本H聚醯亞胺_聚乙烯對苯二甲酷共聚物中之一種 或幾種。 第-導電層220及第二導電層23〇之材質可為銅、銀、 金或其匕苇見金屬。本實施例中，第一導電㉟22〇及第二 導電層230為壓延銅箔。 第二基板3GG可為剛性基板，亦可為柔性基板，其結 ，根據實際*要製作之具有斷差結構之電路板而定。本實 施例中’第一基板3⑽為包括第二基材層及形成於第 二基材層310 一表面之第三導電層320之剛性基板，其具 1358977 有第-表面3〇1及與第-表面3〇1相對之第二表面3〇2。其 中，第-表面對應於第二基材層31〇之表面，第二表 面302對應於第三導電層32〇之表面。 第二基材層310可為單層絕緣基材，亦可 導電 層與分別設於該單層導電層相對兩* 一 π电a々日耵兩表面之絕緣基材構成之 複合基材。本實施例中’第二基材層31〇為單層絕緣基材， 其材質為剛性較好之材料，如選自聚酿亞胺、聚四氟乙稀、 聚硫胺、聚甲基丙烯酸甲醋、聚錢§旨、聚酿亞胺_聚乙稀_ 對苯二甲酯中之一種或幾種。 第三導電層320材質可為銅、銀、金或其它常見金屬， 本實施例中，其為壓延銅箔。 黏合層400用於壓合工藝中黏接第一基板2〇〇及第二 基板300，其為本領域常用《膠黏_，如環氧樹醋膝黏劑。 第二步，於第一導電層220形成第一導電線路221，並 於該第一導電線路221表面定義出貼襞區222 ^ 本實施例採用本領域常見工藝形成該第一導電線路 22：1’如於第一導電層22〇之表面貼附幹膜然後經曝光、 顯影、儀刻工序而成。 參見圖3,其為貼裝區222相對於第一導電線路221 之位置示意圖。貼裝區222用於後續採用表面貼裝工藝將 電子兀件貼裝至電路板表面，其形狀及尺寸根據實際需要 而定。本實施例中，貼裝區222呈矩形，其位於第一導電 線路221之中部。 第三步，於黏合層400開設與貼裝區222相對應之切 11 口 410。 切口 410 孔，如裁設備衝出’其可為不同形狀之通 斷成尺寸較小之兩部分二可古將黏合層400切 該兩部分之切割面相對，置伸：二“有切w面’然後將 該兩部分之間形成=。？見=’由此相當於於 爹見圖4，切口 410之尺+虛 滿足當第一導電線路g « 心 厚棚μ I 基材層31G分別緊貼黏合1358977 IX. Description of the invention: '[Technical field to which the invention pertains] * The present invention relates to the field of circuit board fabrication technology, and more particularly to a method of fabricating a circuit board having a stepped structure. [Prior Art] With the increasing miniaturization and high-speed performance of electronic products, more and more components are soldered on the surface of the circuit board, and the conductive line density and signal transmission amount of the circuit board are required to be larger. To meet this need, boards have evolved from single-panel to dual-panel and multi-layer boards. Among them, the double-sided circuit board and the multi-layer circuit board have a large wiring area and a high assembly density and are widely used, see the literature: Takahashi, A.; High density multilayer printed circuit board for HITAC M-880; IEEE Trans, on Components 1992 ° As a new type of multi-layer circuit board that has emerged in recent years, the circuit board with the fault structure has different layers in different regions, and the area with few layers is small in thickness, small in rigidity, and the number of layers. Many areas have high line density, large thickness and large rigidity, and have excellent overall performance, which can achieve a large number of signal transmission and appropriate rigidity. Referring to Fig. la, there is shown a schematic structural view of a multilayer circuit board 100 having a stepped structure. The multilayer circuit board 100 is formed by a double-sided substrate 110 and a single-sided substrate 120. The surface of the first conductive line 111 of the double-sided substrate 110 is provided with a mounting area 112 for packaging electronic components. At present, a circuit board having a fault junction 1358977 is usually fabricated by a layer-up method, that is, a layer stacking method. Taking the multilayer circuit board 100 as an example, the conventional manufacturing method includes: firstly, providing a double-sided substrate 110, a single-sided substrate 120, and an adhesive layer 130. Referring to FIGS. 1a and 1b, the first of the double-sided substrate 110 The surface is a conductive circuit layer 111. The adhesive layer 130 is provided with a slit 131 corresponding to the size of the mounting region 112. Next, referring to FIG. 1c, the substrate layer 121 of the single-sided substrate 120 is pressed to the double by the adhesive layer 130. The surface of the first conductive circuit layer 111 of the surface substrate 110 is obtained, thereby obtaining the circuit board substrate 140; again, referring to FIG. 1 and FIG. 1, the conductive layer surface 142 is disposed outside the circuit board substrate 140. • The dry film 150 is laid, and exposure and development are performed. And etching to form the second conductive line 143 and the like. However, when the double-sided substrate 110 is a flexible circuit substrate, the double-sided substrate corresponding to the slit 131 will be recessed toward the single-sided substrate 120 when it is dusted with the single-sided substrate 120 due to better flexibility and ductility. The dry film structure attached to the portion is bent. When exposing, developing, and etching the wiring, since the dry film 150 corresponding to the slit 131 is recessed toward the single-sided substrate 120, φ is caused to be subsequently exposed, developed, and etched. The second conductive line 143 obtained by the conductive layer process has different thicknesses and even broken wires, which greatly affects the circuit precision and product qualification rate of the circuit board. In view of the above, it is necessary to provide a method for fabricating a circuit board having a stepped structure to improve the fabrication accuracy and yield of the circuit board. SUMMARY OF THE INVENTION A method for fabricating a circuit board having a stepped structure includes the steps of: providing a first substrate, an adhesive layer, and a second substrate, wherein the first substrate package 1358977 includes an A material layer formed on the first base a first conductive layer and a second conductive layer on opposite surfaces of the material layer, the second substrate comprises a second substrate layer and a third conductive layer formed on the surface of the first substrate layer; forming a first layer on the first conductive layer a conductive line 'and defining a mounting area on the surface of the first conductive line; the adhesive layer is provided with a slit through the opposite surfaces thereof. Thus the adhesive layer has a first cutting surface and a second cutting opposite to the first cutting surface Providing a reinforcing sheet corresponding to the size of the mounting area; laminating and pressing the first substrate, the adhesive layer and the second substrate in sequence, and respectively bonding the first conductive line and the second substrate layer to the adhesive layer The opposite surface is located between the first cutting surface and the second cutting surface, the reinforcing sheet is received in the slit; the second conductive layer is formed on the second conductive layer to obtain the circuit substrate; and the cutting is performed along the first cutting surface The circuit substrate, Thereby preparing a circuit board having a structure of off difference. The method for manufacturing a circuit board having a fault structure provided by the technical solution is characterized in that the first layer and the second substrate are bonded by the adhesive layer having the slit, and the reinforcing sheet is used for filling the gap between the bonding layer and the mounting area. The sin-filling slits make the surface of the conductive layer to be wired on the outer layer flat, avoiding the gap between the outer conductive layer and the slit recess caused by the slit when the first substrate and the second substrate are pressed, thereby overcoming the prior art manufacturing method and easily leading to the conductive The line thickness is not the same as the defect of the wire break. Therefore, the fabrication method of the present technical solution can significantly improve the circuit fabrication precision and product yield of the circuit board. [Embodiment] Hereinafter, a method for fabricating a circuit board having a faulty structure of 8977, which is provided by the present technical solution, will be described in detail with reference to the embodiments and the accompanying drawings. The first step of providing a circuit board having a stepped structure includes a first substrate, a second substrate 3 (10), and an adhesive layer. Referring to FIG. 2, the first substrate 2 includes at least two. The flexible structure of the layer of conductive layer depends on the circuit board to be fabricated with a fault structure: body structure. In this embodiment, the first substrate is a flexible double-sided: copper laminate, which includes a first substrate layer 21 and a first conductive layer 220 and a second conductive layer respectively located on opposite surfaces of the first substrate layer 210. Layer 23〇. The first substrate layer 210 may be a single-layer insulating substrate, or may be a single-layer conductive layer and an insulating substrate respectively disposed on opposite surfaces of the single-layer conductive layer. In the towel of the embodiment, the first substrate layer is a single-layer insulating substrate: the material is a material with good flexibility, such as selected from the group consisting of polyimine, polytetraene, polythioamide, and acrylic acid. One or more of the acetonitrile, the polycarbonate, and the polyethylene, and the material of the first conductive layer 220 and the second conductive layer 23 can be copper or silver. In the present embodiment, the first conductive layer 3522〇 and the second conductive layer 230 are rolled copper foil. The second substrate 3GG may be a rigid substrate or a flexible substrate, and the junction thereof is actually *The board to be fabricated has a circuit having a stepped structure. In the present embodiment, the first substrate 3 (10) is a rigid substrate including a second substrate layer and a third conductive layer 320 formed on a surface of the second substrate layer 310. And having a first surface 3〇1 and a second surface 3〇2 opposite to the first surface 3〇1, wherein the first surface corresponds to the surface of the second substrate layer 31〇, and the second surface 302 corresponds to The surface of the third conductive layer 32. The second substrate layer 310 can be a single-layer insulating substrate, and can also be separately provided with a conductive layer. In the single-layer conductive layer, the composite substrate composed of the insulating substrate of the two surfaces is opposite to each other. In the embodiment, the second substrate layer 31 is a single-layer insulating substrate, and the material thereof is A material with good rigidity, such as selected from the group consisting of polyaniline, polytetrafluoroethylene, polythiamine, polymethyl methacrylate, polystyrene, polystyrene _polyethylene _ terephthalate The material of the third conductive layer 320 may be copper, silver, gold or other common metals. In this embodiment, it is a rolled copper foil. The adhesive layer 400 is used for bonding the first substrate in the pressing process. 2〇〇 and the second substrate 300, which is commonly used in the art as “adhesive_, such as epoxy vinegar knee adhesive. In the second step, the first conductive layer 221 is formed on the first conductive layer 220, and the first The surface of the conductive line 221 defines a contact area 222. In this embodiment, the first conductive line 22 is formed by a common process in the art: 1', the dry film is attached to the surface of the first conductive layer 22, and then exposed, developed, and illuminated. The engraving process is shown in Fig. 3, which is a schematic view of the position of the mounting area 222 with respect to the first conductive line 221. The mounting area 22 2 is used for the subsequent mounting of the electronic component to the surface of the circuit board by the surface mount process, and the shape and size thereof are determined according to actual needs. In this embodiment, the mounting area 222 is rectangular and located on the first conductive line 221 In the third step, a slit 11 is formed in the adhesive layer 400 corresponding to the mounting area 222. The slit 410 is punched out, such as a cutting device, which can be a different shape and cut into two smaller parts. The adhesive layer 400 can be cut into opposite sides of the cut surface of the two parts, and is stretched: two "with a cut surface" and then formed between the two portions =. ? See =' thus equivalent to 爹 see Figure 4, the ruler of the incision 410 + virtual satisfies when the first conductive line g « heart thick shed μ I substrate layer 31G is closely adhered
…二面時，貼裝區222相對於第二基材層310 立於切口 相對於第二基材層310之投影内。優 ^ 刀口 410之杈截面形狀及尺寸與貼裝區222之形狀 及：寸匹配。本實施例中，黏合層働被切斷成相互分離 ::::合部·及第二黏合部43〇,且第一黏合部42〇 /、有第-切割δ 421 ’第二黏合部樣具有與第—切割面 421相對之第二切割面431。第—切割面421與第二切割面 431配合形成切口 41〇。 • 第四步，提供一與貼裝區222尺寸對應之加強片5〇〇。 加強片500可直接置於切口 41〇内，亦可黏附於第二 基材310之第一表面。具體地，可先於第三導電層3加表 面定義出標識區321，並於第二基材31〇之第一表面3〇2 與標識區321相對應處貼裝加強片5〇〇。本實施例中，加強 片500貼於第一表面302與標識區321相對應之表面處。 «月一併參閱圖5至圖6 ’標識區321之示出需根據切口 41〇 之尺寸及形狀而定。優選地，標識區321之形狀及尺寸與 切口 410匹配。具體地，標識區421之示出可採用蝕刻第On both sides, the mounting area 222 is positioned relative to the second substrate layer 310 within the projection of the slit relative to the second substrate layer 310. The shape and size of the cross section of the knife edge 410 are matched with the shape of the mounting area 222 and the inch. In this embodiment, the adhesive layer is cut apart from each other:::: the joint portion and the second adhesive portion 43A, and the first adhesive portion 42〇/, having the first-cut δ 421 'second adhesive portion There is a second cutting surface 431 opposite to the first cutting surface 421. The first cutting face 421 and the second cutting face 431 cooperate to form a slit 41〇. • In the fourth step, a reinforcing sheet 5 corresponding to the size of the mounting area 222 is provided. The reinforcing sheet 500 may be directly placed in the slit 41〇 or adhered to the first surface of the second substrate 310. Specifically, the identification area 321 may be defined before the third conductive layer 3 is added to the surface, and the reinforcing sheet 5 is placed on the first surface 3〇2 of the second substrate 31〇 corresponding to the identification area 321 . In this embodiment, the reinforcing sheet 500 is attached to the surface of the first surface 302 corresponding to the marking area 321 . The indication of the "monthly reference to Fig. 5 to Fig. 6" identification area 321 depends on the size and shape of the slit 41. Preferably, the shape and size of the identification zone 321 matches the slit 410. Specifically, the identification area 421 can be illustrated by etching
< S 12 1358977 三導電層320並於第三導電層320之第一表面301形成標 識圖案之方式，亦可於第一表面301貼裝標識片，或以其 它常見方式示出，只要能起直觀識別作用即可。藉由設置 標識區321可直觀得出所需貼裝之加強片500之尺寸及定 義加強片500相對於第一表面301之位置，以便於後續於 第一表面301與該標識區221相對應處貼裝加強片500以 及後續根據標識區321除去標識區321對應之第二基材層。 加強片500用於填充切口 410，優選地，其形狀及尺寸 春與貼裝區222及切口 410之形狀及尺寸匹配，以確保後續 第一基板200與第二基板300以第一導電線路221、第二基 材層310緊貼黏合層400相對兩表面之方式壓合後，加強 片500完全填充切口 410，且貼裝區222位於第一切割面 421及第二切割面431之間。 第五步，將第一基板200、黏合層400及第二基板300 依次疊層並壓合。 鲁 請一併參閱圖4及圖7,第一基板200、黏合層400及 第二基板300之疊層及壓合應使得第二基材層310及第一 . 導電線路221分別緊貼於黏合層400相對之兩表面，且貼 裝區222位於第一切割面421與第二切割面431之間，加 強片500收容於切口 410内，並與切口 410處對應之貼裝 區222相接觸。由此，切口 410被加強片500完全填充， 第二導電層230與切口 410對應之部分不再朝第二基材層 310凹陷，即，藉由設置加強片500填充切口之方式使得第 二導電層230表面平整度提高，不再存有較大落差。 13 1358977 第六步，於第二導電層230形成第二導電線路231，得 電路基板700。 參閱圖8及圖9,第二導電線路231之形成可採用蝕刻 工藝，其具體包括於第二導電層230表面貼幹膜600、曝 光、顯影、蝕刻等步驟。另外，參見圖10，於第二導電線 路231之圖案形成之前或之後，還可包括一鑽貫通第二導 電層230及第三導電層320之通孔、將通孔孔壁電鍍之步 驟，以導通第二導電層230與第三導電層320,使得第二導 ®電層230與第三導電層320之間可達成訊號傳輸。如果通 孔孔壁電鍍工藝係於第二導電線路231之圖案形成之後進 行，則進行孔壁電鍍之前應於第二導電層230之表面貼覆 幹膜以保護線路圖案。 第七步，沿第一切割面421裁切電路板基板700。 於裁切電路板基板700前可取出加強片500,然後再沿 第一切割面421裁切電路板基板700，亦可不取出加強片 | 500，而直接採用切割設備裁切電路板基板700。請一併參 閱圖11至圖13，本實施例中，裁切電路板基板700前藉由 除去標識區321對應之第三導電層，暴露出部分第二基材 層310，除去該部分第二基材層310，而取出加強片500。 參見圖11，導電層可採用蝕刻方式，亦可採用摻鈥釔 鋁石榴石Nd:YAG鐳射切割。請一併參閱圖11及圖12，該 部分第二基材層310可藉由鐳射切割去除。鐳射種類根據 第二基材層310之材質進行相應選擇。一般來說，摻鈥釔 鋁石榴石Nd:YAG鐳射器發射之鐳射波長較短，屬紫外波 14 1358977 段，脈衝頻率較高，可用於㈣導電層及絕緣層。⑺ 器發射之錯射波長較長，屬中紅外波段，通常僅射 割絕緣層。當然，亦可選擇混合鐳射系統，即，以職= 鐳射切割導電層’ α 〇)2鐳射切割絕緣層。本實施例中， 第二基材層31G為絕緣層，故以c〇2鐘射進行㈣即可。< S 12 1358977 The three conductive layers 320 form a marking pattern on the first surface 301 of the third conductive layer 320, and may also be mounted on the first surface 301, or in other common manners, as long as Visual recognition can be done. The size of the reinforcing sheet 500 to be mounted can be visually determined by setting the marking area 321 and the position of the reinforcing sheet 500 relative to the first surface 301 can be defined so as to be subsequently corresponding to the marking area 221 of the first surface 301. The reinforcing sheet 500 is mounted and the second substrate layer corresponding to the marking area 321 is removed according to the marking area 321 . The reinforcing sheet 500 is used to fill the slit 410. Preferably, the shape and size of the reinforcing sheet 500 are matched with the shape and size of the mounting area 222 and the slit 410 to ensure that the first first substrate 200 and the second substrate 300 are in the first conductive line 221, After the second substrate layer 310 is pressed against the two surfaces of the adhesive layer 400, the reinforcing sheet 500 completely fills the slit 410, and the mounting region 222 is located between the first cutting surface 421 and the second cutting surface 431. In the fifth step, the first substrate 200, the adhesive layer 400, and the second substrate 300 are sequentially laminated and pressed. Referring to FIG. 4 and FIG. 7 together, the lamination and pressing of the first substrate 200, the adhesive layer 400 and the second substrate 300 are such that the second substrate layer 310 and the first conductive line 221 are respectively adhered to the bonding. The surface 400 is opposite to the two surfaces, and the mounting area 222 is located between the first cutting surface 421 and the second cutting surface 431. The reinforcing sheet 500 is received in the slit 410 and is in contact with the corresponding mounting area 222 at the slit 410. Thereby, the slit 410 is completely filled by the reinforcing sheet 500, and the portion of the second conductive layer 230 corresponding to the slit 410 is no longer recessed toward the second base material layer 310, that is, the second conductive layer is made by providing the reinforcing sheet 500 to fill the slit. The surface flatness of the layer 230 is increased, and there is no longer a large drop. 13 1358977 In the sixth step, the second conductive line 231 is formed on the second conductive layer 230 to obtain the circuit substrate 700. Referring to FIG. 8 and FIG. 9, the second conductive line 231 may be formed by an etching process, which specifically includes the steps of adhering the film 600, exposing, developing, etching, etc. to the surface of the second conductive layer 230. In addition, referring to FIG. 10, before or after the pattern formation of the second conductive line 231, a step of drilling through the via holes of the second conductive layer 230 and the third conductive layer 320 and plating the via hole walls may be further included. The second conductive layer 230 and the third conductive layer 320 are turned on, so that signal transmission can be achieved between the second conductive layer 230 and the third conductive layer 320. If the via hole wall plating process is performed after the patterning of the second conductive line 231, the dry film should be applied to the surface of the second conductive layer 230 to protect the line pattern before the hole wall plating. In the seventh step, the circuit board substrate 700 is cut along the first cutting surface 421. The reinforcing sheet 500 may be taken out before the cutting of the circuit board substrate 700, and then the circuit board substrate 700 may be cut along the first cutting surface 421, or the circuit board substrate 700 may be directly cut by a cutting device without taking out the reinforcing sheet| Referring to FIG. 11 to FIG. 13 , in this embodiment, a portion of the second substrate layer 310 is exposed by removing the third conductive layer corresponding to the identification region 321 before the circuit board substrate 700 is cut, and the second substrate layer 310 is removed. The base material layer 310 is taken out and the reinforcing sheet 500 is taken out. Referring to Fig. 11, the conductive layer may be etched or ytterbium-doped aluminum garnet Nd:YAG laser cut. Referring to Figures 11 and 12 together, the portion of the second substrate layer 310 can be removed by laser cutting. The laser type is selected according to the material of the second substrate layer 310. In general, the erbium-doped aluminum garnet Nd:YAG laser emits a shorter laser wavelength, which belongs to the ultraviolet wave 14 1358977 segment, and has a higher pulse frequency, which can be used for (iv) conductive layer and insulating layer. (7) The transmitter emits a long wavelength with a wrong wavelength, which belongs to the mid-infrared band and usually only injects the insulating layer. Of course, a hybrid laser system can also be selected, that is, a laser-cut insulating layer of a laser-cut conductive layer 'α 〇)2. In the present embodiment, the second base material layer 31G is an insulating layer, so that it may be carried out by c〇2 clocking (four).
當然，還可根據需要，於第三導電層32〇製作第三 電線路。第三導電線路之製作可與第二導電線路231 ^ 製作，亦可於取出加強片5〇〇後製作。 ， 參見圖12及圖13,沿第一切割面421 一併裁斷第— 電線路221、第-基材層21〇及第二導電線路231即可得 具有斷差結構之電路板。 本實施例之具有斷差結構之電路板之製作方法藉由設 置加強片500填充切口 41〇，使得待佈線之第二導電層 表面平整’避免了壓合第—基板勘與第二基板鳩時由 於切口 410引起之第一導電層230沿切口 41〇凹陷產生落 差，從而克服了先前技術之製作方法容易導致導電線路粗 細不一，甚至斷線之缺陷。因此，使用本技術方案之製作 方法可顯著地提高電路板之線路製作精度及產品合格率。 日綜上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限製本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化，皆 應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 15 1358977 圖la至圖le係習知斷差結構之電路板製作方法中壓 合及形成電路之示意圖。 圖2至圖13係本技術方案之實施例提供之具有斷差結 構之電路板製作方法之示意圖。 【主要元件符號說明】 多層電路板 100 雙面基板 110 單面基板 120 第一導電線路 111 、 221 貼裝區 112、222 黏合層 130、 400 切口 131 、 410 基材層 121 電路板基板 140、700 導電層表面 142 幹膜 150、600 第二導電線路 143 、 231 第一基板 200 < 第二基板 300 第一基材層 210 第一導電層 220 第二導電層 230 第二基材層 310 16 1358977 第三導電層 320 第一表面 301 第二表面 302 第一黏合部 420 第二黏合部 430 第一切割面 421 第二切割面 431 加強片 500 標識區 321 17Of course, a third electrical line can also be fabricated on the third conductive layer 32〇 as needed. The third conductive line can be fabricated with the second conductive line 231^ or after the reinforcing sheet 5 is removed. Referring to Fig. 12 and Fig. 13, the first electric circuit 221, the first substrate layer 21, and the second conductive line 231 are cut together along the first cutting surface 421 to obtain a circuit board having a stepped structure. The manufacturing method of the circuit board with the fault structure of the present embodiment is such that the surface of the second conductive layer to be wired is flattened by the provision of the reinforcing sheet 500 to fill the slit 41 ' to avoid the pressing of the first substrate and the second substrate The first conductive layer 230 is caused to fall along the slit 41 by the slit 410, thereby overcoming the defect that the manufacturing method of the prior art is liable to cause the thickness of the conductive line to be different or even broken. Therefore, the fabrication method of the technical solution can significantly improve the circuit fabrication precision and product qualification rate of the circuit board. As mentioned above, the present invention has indeed met the requirements of the invention patent, and has filed a patent application in accordance with the law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the present invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS 15 1358977 FIG. 1A to FIG. 3 are schematic diagrams showing a process of forming and forming a circuit in a circuit board manufacturing method of a conventional differential structure. 2 to FIG. 13 are schematic diagrams showing a method of fabricating a circuit board having a fault structure according to an embodiment of the present technical solution. [Main component symbol description] Multi-layer circuit board 100 Double-sided substrate 110 Single-sided substrate 120 First conductive line 111, 221 Mounting area 112, 222 Adhesive layer 130, 400 Notch 131, 410 Substrate layer 121 Circuit board substrate 140, 700 Conductive layer surface 142 dry film 150, 600 second conductive line 143, 231 first substrate 200 < second substrate 300 first substrate layer 210 first conductive layer 220 second conductive layer 230 second substrate layer 310 16 1358977 Third conductive layer 320 first surface 301 second surface 302 first adhesive portion 420 second adhesive portion 430 first cut surface 421 second cut surface 431 reinforcing sheet 500 identification region 321 17