JP2017073516A - Manufacturing method of one-side circuit board and manufacturing method of multilayer circuit board using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a one-side circuit board and a manufacturing method of a multilayer circuit board using the same, which can reduce a poor connection.SOLUTION: A manufacturing method of a one-side circuit board 10 of the present invention, includes steps of: laminating copper foils 35 and 37 on both surfaces of back and front of an insulation circuit board 11; forming a non-penetration hole 41 that penetrates the copper foil 37 on one side of back and front of the insulation circuit board 11 and the insulation circuit board 11 and has, as a bottom part, the copper foil 35 on the other side; forming a concave part 42 from the non-penetration hole 41 side in the copper foil 35; forming a first electrolytic plating layer 45 in the concave part 42; forming a second electrolytic plating layer 47 that electrically connects the first electrolytic plating layer 45 and the copper foil 37 in the non-penetration hole 41; removing the copper foil 35 and forming a conductive bump 13 by the second electrolytic plating layer 45 projecting from a surface on the other side of insulation circuit board 11; and removing a part of the copper foil 37 and forming a conductor circuit layer 12.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a method for manufacturing a single-sided circuit board in which a conductor circuit layer is formed on one side of an insulating layer, and a method for manufacturing a multilayer circuit board using the single-sided circuit board.

  Conventionally, as a method for manufacturing this type of single-sided circuit board, a conductive circuit layer is formed on the front side surface of the insulating layer, and then a non-through hole is formed from the back side surface of the insulating layer toward the conductive circuit layer. A method of forming a conductive bump protruding from the back side surface of an insulating layer by filling a through hole with plating is known (see, for example, Patent Document 1).

JP 2004-311705 A (paragraphs [0156] to [0158], FIGS. 1 and 7)

  However, when manufacturing a multilayer circuit board by directing the conductive bumps of the above-mentioned single-sided circuit board to the conductor circuit layer of another circuit board and bonding the single-sided circuit board and another circuit board with a bonding sheet, There may be a problem that a connection failure occurs between the conductive bump and the conductor circuit layer.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a single-sided circuit board capable of reducing connection failures and a method for manufacturing a multilayer circuit board using the same.

  In the method for manufacturing a single-sided circuit board according to the present invention, the first conductor layer is formed on both the front and back surfaces of the insulating layer, and the first conductor layer and the insulating layer on one side of the front and back surfaces of the insulating layer are formed. Forming a non-through hole penetrating and having the first conductor layer on the other side as a bottom; forming a recess in the first conductor layer on the other side from the non-through hole side; Forming a two-conductor layer, forming an interlayer connection conductor that electrically connects the second conductor layer and the first conductor layer on the one side in the non-through hole, and the other side Removing the first conductor layer, forming a conductive bump with the second conductor layer protruding from the other surface of the insulating layer, and removing a portion of the first conductor layer on the one side; Forming a conductor circuit layer. A method for manufacturing a single-sided circuit board.

Sectional drawing of the single-sided circuit board based on one Embodiment of this invention Sectional drawing which shows the manufacturing process of a single-sided circuit board Sectional drawing which shows the manufacturing process of a single-sided circuit board Sectional drawing which shows the manufacturing process of a single-sided circuit board Sectional drawing which shows the manufacturing process of a single-sided circuit board Sectional drawing which shows the manufacturing process of a single-sided circuit board Sectional drawing which shows the manufacturing process of a single-sided circuit board Sectional drawing which shows the manufacturing process of a single-sided circuit board Cross section of multilayer circuit board Sectional view showing manufacturing process of multilayer circuit board Sectional drawing of the multilayer circuit board which concerns on other embodiment (A) Cross-sectional view of multilayer circuit board according to another embodiment, (B) Cross-sectional view of multilayer circuit board according to another embodiment.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a single-sided circuit board 10 of the present embodiment. The single-sided circuit board 10 includes an insulating base material 11 corresponding to the “insulating layer” of the present invention, and a conductor circuit layer 12 laminated on a circuit forming surface 111 that is one of the front and back sides of the insulating base material 11. And the conductive bump 13 protruding from the bump forming surface 112 which is the surface on the other side of the front and back sides of the insulating base material 11. The insulating substrate 11 is made of an insulating resin sheet (for example, a prepreg containing a reinforcing material such as glass fiber).

  A conductive through hole 14 is formed in the insulating base material 11. The conductive through hole 14 has a tapered shape that is reduced in diameter toward the bump formation surface 112 side. The conductive through hole 14 is filled with electrolytic plating to form a via conductor 15, and the conductive bump 13 and the conductor circuit layer 12 are connected by the via conductor 15.

  The conductive bump 13 is made of a metal different from the conductor circuit layer 12. On the other hand, the via conductor 15 is made of the same metal as the conductor circuit layer 12. The conductor circuit layer 12 is made of copper, and the conductive bumps 13 are made of tin.

  The conductive bump 13 is made of electrolytic tin plating and constitutes the first electrolytic plating layer 45. The conductor circuit layer 12 includes a copper foil 37 and an electrolytic plating film 47 </ b> M laminated on the copper foil 37. The electrolytic plating film 47 </ b> M of the conductor circuit layer 12 disposed on the via conductor 15 is formed integrally with the via conductor 15. Specifically, the electrolytic plating film 47M and the via conductor 15 are both made of electrolytic copper plating, and constitute the second electrolytic plating layer 47. The second electrolytic plating layer 47 electrically connects the conductive bump 13 and the copper foil 37 to constitute the interlayer connection conductor 17 according to the present invention.

The single-sided circuit board 10 of this embodiment is manufactured as follows.
(1) As shown to FIG. 2 (A), the peeling film 31, the copper foil 33 with a carrier, the insulating base material 11, and the copper foil 37 are laminated | stacked on the both surfaces of the front and back of the support substrate 30 in order. The support substrate 30 is made of an insulating resin sheet (for example, a prepreg including a reinforcing material such as glass fiber), like the insulating base material 11. The carrier-attached copper foil 33 has a structure in which the carrier 34 and the copper foil 35 are bonded together, and the carrier-attached copper foil 33 that is superimposed on the F surface 30F that is the surface on the front side of the support substrate 30 has the carrier 34 on the F surface. The copper foil 33 with a carrier that is disposed toward the 30F side and is superimposed on the S surface 30S that is the surface on the back side of the support substrate 30 is disposed with the carrier 34 facing the S surface 30S side. Moreover, the copper foil 33 with a carrier adhere | attaches the outer peripheral parts of the carrier 34 and the copper foil 35, and insulating property is provided in the center part to which the carrier 34 and the copper foil 35 are not adhere | attached among the copper foils 33 with a carrier. The base material 11 and the copper foil 37 are overlaid. The release film 31 has substantially the same size as the insulating base material 11 and is disposed at a position directly below the insulating base material 11. The copper foil 37 is thicker than the copper foil 35 of the carrier-attached copper foil 33. Specifically, the thickness of the copper foil 37 is about 18 μm, and the thickness of the copper foil 35 is about 9 μm. The copper foil 35 and the copper foil 37 correspond to the “first conductor layer” of the present invention.

  (2) As shown in FIG. 2 (B), a heat press process is performed, and the support substrate 30, the peeling film 31, the copper foil 33 with a carrier, the insulating base material 11, and the copper foil 37 are integrated. At this time, the release film 31 on the F surface 30F side of the support substrate 30 is buried in the F surface 30F and is flush with the F surface 30. The same applies to the release film 31 on the S surface 30S side.

  (3) As shown in FIG. 3A, the copper foil 37 is irradiated with, for example, a CO2 laser from the F surface 30F side and the S surface 30S side of the support substrate 30, and the copper foil 37 and the insulating base material 11 and a non-through hole 41 having a copper foil 35 as a bottom is formed. Next, desmear processing is performed to remove the resin residue remaining on the side and bottom surfaces of the non-through holes 41. As shown in an enlarged view in FIG. 3B, the non-through hole 41 is formed in a tapered shape in which the diameter of the support substrate 30 is reduced.

  (4) Etching is performed, and a bowl-shaped recess 42 is formed in the copper foil 35 exposed in the non-through hole 41 as shown in FIG. At this time, the copper foil 37 is also etched by the etching solution for forming the recess 42 in the copper foil 35. As a result, as shown in the change from FIG. 3B to FIG. 4A, the copper foil 37 becomes thinner.

  (5) As shown in FIG. 4B, a predetermined pattern of plating resist 43 is formed on the copper foil 37.

  (6) An electrolytic tin plating process using the copper foil with carrier 33 as a plating lead is performed, and as shown in FIG. 5, the electrolytic tin plating is filled in the recesses 42 and the first electrolytic plating layer 45 (“ Corresponds to the “second conductor layer”). At this time, the first electrolytic plating layer 45 also enters the non-through hole 41.

  (7) Next, an electrolytic copper plating process using the copper foil with carrier 33 as a plating lead is performed, and as shown in FIG. 6 (A), the electrolytic copper plating is filled in the non-through holes 41, and the first electrolysis is performed. A second electrolytic plating layer 47 that electrically connects the plating layer 45 and the copper foil 37 is formed, and an electrolytic plating film 47M is formed on a portion of the copper foil 37 exposed from the plating resist 43. The

  (8) An electrolytic tin plating process is performed using the copper foil with carrier 33 as a plating lead, and a metal resist 48 is formed on the electrolytic plating film 47M as shown in FIG. 6B. The metal resist 48 corresponds to the “third conductor layer” of the present invention, and is formed of the same metal as the first electrolytic plating layer 45, that is, tin.

  (9) As shown in FIG. 7A, the plating resist 43 is peeled off.

  (10) As shown in FIG. 7B, the center part of the copper foil 35 in the copper foil 33 with the carrier is cut off from the outer peripheral part, and the intermediate base material is formed from the F surface 30F side and the S surface 30S side of the support substrate 30. 50 is obtained one by one. In the example of FIG. 7B, the intermediate substrate 50 on the S surface 30S side has the same structure as the intermediate substrate 50 on the F surface 30F side, but may have a different structure.

  (11) As shown in FIG. 8A, etching treatment is performed on both the front and back surfaces of the intermediate base material 50, and the metal resist 48 in the copper foil 37 is used on the circuit forming surface 111 side of the insulating base material 11. The uncovered portion is removed, and the copper foil 35 is removed on the bump forming surface 112 side of the insulating substrate 11. In this etching process, an alkaline etching solution is used, and the copper foil 37 formed of copper is selectively etched with respect to the metal resist 48 formed of tin.

  (12) A peeling solution is sprayed on the front side and the back side of the intermediate base material 50, and as shown in FIG. 8B, the metal resist 48 is removed, and the copper foil 37 and the second electrolytic plating layer 47 are removed. The conductor circuit layer 12 is formed by a part of (a portion disposed outside the circuit forming surface 111 of the insulating base material 11). At this time, the first electrolytic plating layer 45 protruding from the bump forming surface 112 of the insulating base material 11 is partly shaved to form the conductive bump 13. Thus, the single-sided circuit board 10 is completed.

  The single-sided circuit board 10 is used for manufacturing the multilayer circuit board 100 shown in FIG. The multilayer circuit board 100 is formed by laminating a plurality of single-sided circuit boards 10 on both front and back surfaces of a double-sided circuit board 70. The double-sided circuit board 70 includes an insulating base 71 made of an insulating resin sheet (for example, a prepreg containing a reinforcing material such as glass fiber), and an F side 71F on the front side and the back side of the insulating base 71. Conductor circuit layers 72 and 72 formed on the S surface 71S. The conductor circuit layers 72 and 72 are electrically connected by a via conductor 75 that penetrates the insulating base 71.

  The plurality of single-sided circuit boards 10 on the F-side 71F side of the insulating base 71 are arranged with the conductive bumps 13 facing the double-sided circuit board 70 and are separated from the double-sided circuit board 70. The ten conductive bumps 13 are connected to the conductor circuit layer 12 of the single-sided circuit board 10 that is one inner side than the single-sided circuit board 10 (on the double-sided circuit board 70 side). The conductive bump 13 of the innermost single-sided circuit board 10 among the plurality of single-sided circuit boards 10 is connected to the conductor circuit layer 72 of the double-sided circuit board 70. An adhesive layer 77 is provided between the insulating base materials 11 and 11 of the single-sided circuit boards 10 and 10 and between the insulating base material 11 of the single-sided circuit board 10 and the insulating base material 71 of the double-sided circuit board 70. It is glued. The adhesive layer 77 disposed between the insulating base materials 11 and 11 has substantially the same thickness as the conductor circuit layer 12, and is between the insulating base material 11 and the insulating base material 71. The adhesive layer 77 to be disposed has substantially the same thickness as the conductor circuit layer 72.

  The plurality of single-sided circuit boards 10 on the S surface 71S side of the insulating base 71 has the same structure as the above-described plurality of single-sided circuit boards 10 on the F surface 71F side. Also on the S surface 71S side, the single-sided circuit boards 10 and 10 and the single-sided circuit board 10 and the double-sided circuit board 70 are bonded by an adhesive layer 77.

The multilayer circuit board 100 is manufactured as follows.
(1) As shown in FIG. 10, a plurality of single-sided circuit boards 10 and a plurality of adhesive layers 77 are alternately laminated on the F surface 71F and the S surface 71S of the insulating base 71 in the double-sided circuit board 70. . In this lamination, pins are inserted into pin insertion holes (not shown) formed in the double-sided circuit board 70 and the plurality of single-sided circuit boards 10, so that the double-sided circuit board 70 and the plurality of single-sided circuit boards 10 are connected. Aligned horizontally. The single-sided circuit board 10 is arranged with the conductive bumps 13 facing the double-sided circuit board 70 side. Here, a bump insertion hole 77A is formed through the adhesive layer 77, and the conductive bump 13 is inserted through the bump insertion hole 77A.

  (2) The single-sided circuit board 10 and the double-sided circuit board 70 are bonded to each other by the adhesive layer 77 by heat pressing, and the conductive bumps 13 of the single-sided circuit board 10 are pressure-bonded to the conductor circuit layer 72 of the double-sided circuit board 70. Thus, the conductive bump 13 and the conductor circuit layer 72 are electrically connected. The single-sided circuit boards 10 and 10 are bonded to each other by the adhesive layer 77, and the conductive bumps 13 of the single-sided circuit board 10 on the side far from the double-sided circuit board 70 are inserted into the bump insertion holes 77A. The conductive bump 13 and the conductor circuit layer 12 are electrically connected to each other by being crimped to the conductor circuit layer 12 of the single-sided circuit board 10 on the side close to. Thus, the multilayer circuit board 100 is completed.

  According to the method for manufacturing the single-sided circuit board 10 of the present embodiment, the first electrolytic plating layer 45 and the second electrolytic plating layer 47 (interlayer connection conductor 17) are sequentially formed from the bump forming surface 112 side of the insulating base material 11. Therefore, compared with the case where the second electrolytic plating layer 47 and the first electrolytic plating layer 45 are sequentially formed from the circuit forming surface 111 side as in the conventional method of manufacturing the single-sided circuit board 10, the single-sided circuit board 10 It becomes easy to protrude the conductive bump 13 from the S surface 10S. Thereby, in the multilayer circuit board 100 manufactured using the single-sided circuit board 10, it is possible to suppress poor connection of the conductive bumps 13. In addition, since the non-through hole 41 has a tapered shape in which the diameter of the bump forming surface 112 is reduced, air is prevented from entering when the non-through hole 41 is filled with plating, and is formed in the non-through hole 41. It is possible to improve the electrical connectivity of the interlayer connection conductor 17 (via conductor 15).

  Further, according to the method for manufacturing the single-sided circuit board 10 of the present embodiment, the intermediate base material 50 is formed on the front side and the back side of the support substrate 30, and the single-sided circuit board 10 is obtained from each intermediate base material 50. Therefore, the production efficiency of the single-sided circuit board 10 can be improved.

  In the manufacturing method of the multilayer circuit board 100 of the present embodiment, the single-sided circuit board is attached to the adhesive layer 77 that bonds the single-sided circuit boards 10 and 10 and between the single-sided circuit board 10 and the double-sided circuit board 70. Since the bump insertion holes 77A through which the ten conductive bumps 13 are inserted are formed so as to penetrate, the conductive bumps 13 can be easily pressed onto the conductor circuit layer 12 of the single-sided circuit board 10 and the conductor circuit layer 72 of the double-sided circuit board 70. Accordingly, it is possible to suppress a connection failure between the conductive bump 13 and the conductor circuit layers 12 and 72.

[Other Embodiments]
The present invention is not limited to the above-described embodiment. For example, the embodiments described below are also included in the technical scope of the present invention, and various modifications are possible within the scope of the invention other than the following. It can be changed and implemented.

  (1) In the method of manufacturing the multilayer circuit board 100 of the above embodiment, the number of single-sided circuit boards 10 stacked on the front side and the back side of the double-sided circuit board 70 is the same, but may be different (FIG. 11 reference).

  (2) In the multilayer circuit board 100 of the above embodiment, the single-sided circuit board 10 may be laminated only on one side of the front and back of the double-sided circuit board 70. At that time, a plurality of single-sided circuit boards 70 may be stacked (see FIG. 12A) or only one (see FIG. 12B).

  (3) In the method for manufacturing the single-sided circuit board 10 of the above embodiment, the metal resist 48 is formed by electrolytic plating, but a resin protective film may be formed instead of the metal resist 48.

DESCRIPTION OF SYMBOLS 10 Single-sided circuit board 11 Insulating base material 12 Conductor circuit layer 13 Conductive bump 17 Interlayer connection conductor 30 Support substrate 35, 37 Copper foil (1st conductor layer)
41 Non-through hole 42 Concave portion 45 First electrolytic plating layer (second conductor layer)
47 Second electrolytic plating layer 48 Metal resist (third conductor layer)
77 Adhesive layer 77A Bump insertion hole 100 Multilayer circuit board

Claims (9)

Forming a first conductor layer on both sides of the insulating layer;
Forming a non-through hole with the bottom of the first conductor layer on the other side penetrating the first conductor layer and the insulating layer on one side of the front and back of the insulating layer;
Forming a recess communicating with the non-through hole in the first conductor layer on the other side;
Forming a second conductor layer in the recess;
Forming an interlayer connection conductor for electrically connecting the second conductor layer and the first conductor layer on the one side in the non-through hole;
Removing the first conductor layer on the other side and forming a conductive bump with the second conductor layer protruding from the other side surface of the insulating layer;
A method for producing a single-sided circuit board, comprising: removing a part of the first conductor layer on one side to form a conductor circuit layer. It is a manufacturing method of the single-sided circuit board according to claim 1,
In forming the first conductor layer on both the front and back surfaces of the insulating layer, the other side first conductor layer, the insulating layer, and the one side first conductor layer are formed on both the front and back surfaces of the support substrate. , In order,
After forming the non-through hole, the second conductor layer, and the interlayer connection conductor on both the front side and the back side of the support substrate, the first conductor layer on the other side is peeled off from the support substrate. A method for producing a single-sided circuit board according to claim 1 or 2,
In forming the conductor circuit layer, an etching resist is further formed on the first conductor layer on the one side and the interlayer connection conductor with a third conductor layer made of the same material as the second conductor layer, Selectively etching the first conductor layer with respect to the third conductor layer. A method for producing a single-sided circuit board according to claim 3,
The removal of the first conductor layer on the other side and the formation of the conductor circuit layer are performed in the same etching process. A method for manufacturing a single-sided circuit board according to any one of claims 1 to 4,
In forming the non-through hole, the non-through hole is formed in a shape that gradually decreases in diameter toward the first conductor layer on the other side. Forming a single-sided circuit board according to any one of claims 1 to 5,
Stacking a double-sided circuit board having conductor circuit layers on both sides of the front and back with an adhesive layer sandwiched between the other side of the single-sided circuit board;
A method of manufacturing a multilayer circuit board, comprising: integrating the single-sided circuit board and the double-sided circuit board by pressing. A method for producing a multilayer circuit board according to claim 6,
Stacking the single-sided circuit board with the adhesive layer sandwiched between both sides of the double-sided circuit board,
The double-sided circuit board and the plurality of single-sided circuit boards are integrated in a multilayer shape by pressing. A method for producing a multilayer circuit board according to claim 6 or 7,
When stacking the single-sided circuit board and the double-sided circuit board, a plurality of the single-sided circuit boards are stacked on at least one of the front side and the back side of the double-sided circuit board, and the adhesive layer is sandwiched between the single-sided circuit boards. Overlapping. A method for manufacturing a multilayer circuit board according to any one of claims 6 to 8,
Before the adhesive layer is stacked on the other surface of the single-sided circuit board, a bump insertion hole through which the conductive bump is inserted is formed through the adhesive layer.

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