TWI358976B - Substrate of printed circuit board and method for - Google Patents
Substrate of printed circuit board and method for Download PDFInfo
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- TWI358976B TWI358976B TW97114143A TW97114143A TWI358976B TW I358976 B TWI358976 B TW I358976B TW 97114143 A TW97114143 A TW 97114143A TW 97114143 A TW97114143 A TW 97114143A TW I358976 B TWI358976 B TW I358976B
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- substrate
- layer
- removal
- circuit board
- conductive
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- 239000000758 substrate Substances 0.000 title claims description 214
- 238000000034 method Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims description 156
- 238000005520 cutting process Methods 0.000 claims description 41
- 239000012790 adhesive layer Substances 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 15
- 150000001875 compounds Chemical class 0.000 claims description 9
- 239000002131 composite material Substances 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000003698 laser cutting Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000012937 correction Methods 0.000 description 3
- 238000003801 milling Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229910019655 synthetic inorganic crystalline material Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- JNDMLEXHDPKVFC-UHFFFAOYSA-N aluminum;oxygen(2-);yttrium(3+) Chemical compound [O-2].[O-2].[O-2].[Al+3].[Y+3] JNDMLEXHDPKVFC-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 229910019901 yttrium aluminum garnet Inorganic materials 0.000 description 1
Landscapes
- Structure Of Printed Boards (AREA)
Description
1358976 _._二 ‘ . 4 100年06月15日修正賴頁 六、發明說明: 【發明所屬之技術領域】 [0001] 本發明涉及電路板製作技術領域,尤其涉及一種電路板 基板及具有斷差結構之電路板之製作方法。 【先前技術】1358976 _._二' . 4100 June 15th revised Lai page VI, invention description: [Technical field of invention] [0001] The present invention relates to the field of circuit board fabrication technology, and more particularly to a circuit board substrate and having a break A method of manufacturing a circuit board with a poor structure. [Prior Art]
[0002] 隨著電子產品日趨小型化及高速性能化,電路板表面焊 接之元件越來越多,要求電路板之導電線路密度及訊號 傳輸量亦越來越大。為適應此需求,電路板已從單面板 發展為雙面板及多層板。其中,雙面電路板及多層電路 板具有較多佈線面積、較高裝配密度而得到廣泛應用, 參見文獻:Takahashi,A. ; High density multilayer printed circuit board for HITAC M-880; IEEE Trans, on Components, Packaging, and Manufacturing Technology; 1992 o [0003] 作為近年來出現之一種新型多層電路板,具有斷差結構 之電路板由於其於不同之區域具有不同之層數,層數少 之區域厚度小、剛性小,層數多之區域線路密度高、厚 度及剛度大,因而既可傳輸大量資訊又具有適當剛撓性 [0004] 參見圖la,為一種具有斷差結構之多層電路板100之結構 示意圖。該多層電路板100由一雙面基板11+0與一單面基 板120製成,其中,該雙面基板110之第一導電線路111 設有貼裝區112,用於貼裝電子元件。 [0005] 目前,通常採用增層法即層層疊加法製作具有斷差結構 之電路板。以多層電路板100為例,其習知之製作方法包 097114143 表單编號 A0101 第 4 頁/共 30 頁 100321304卜0 1358976 —— 3 - 1100年.06月 15 日 括〔首先,提供雙面基板110、單面基板120及黏合劑層 130 ’諳一併參閱圖ia及圖ib,該雙面基板11〇之表面形 成有第一導電線路111,該第一導電線路111設有貼裝區 112 ’該黏合劑層130設有與貼裝區112尺寸對應之切口 131 ’該單面基板120包括基材層121及導電層122 ;其次 ’請參見圖lc,利用黏合劑層130將單面基板120之基材 層121壓合到雙面基板11〇之第一導電線路hi表面,且 使得切口 131與貼裝區112相對,採用雷射切割設備或銑 刀切割掉單面基板120之導電層122及基材層121與切口 ® 131對應之部分,從而使得貼裝區112外露;最後,於單 面基板120之剩餘導電層形成導電線路。當然,還可製作 貫通單面基板120與雙面基板11〇之導通孔以及電鑛該導 通孔孔壁。 [0006]然而,當單面基板120為硬板時,由於其基材層121材質 多為由網狀玻璃纖維及聚合物樹脂組成之複合材料,造 成單面基板120表面平整度較差,各處厚度相差較大。當 φ 採用雷射去除單面基板120與切口 131對應之部分導電層 122及部分基材層121時,由於單面基板12〇表面不平整 導致厚度差異,使得單面基板120各處需要不同之切割能 量,而雷射切割工藝採用某一確定之能量進行切割,因 此各處之切割深度將不同,很可能發生切割過度,即將 雙面基板110之貼裝區112對應之部分第一導電線路hi 切斷。若改用銑刀切割,仍會因單面基板12〇之各處厚度 不一,難以掌握銑刀插入深度,損傷雙面基板11〇之貼裝 區112對應之第一導電線路in,導致該部分第一導電線 097114143 表單編號A0101 第5頁/共30頁 1003213041-0 1358976 100年06月15日俊正赛涣百 路斷線,從而降低後續電路板產品之合格率,浪費生產 原料。 [0007] 有鑑於此,提供一種電路板基板及格具有斷差結構之電 路板之製作方法,以提高電路板之製作精度及合格率實 為必要。 【發明内容】[0002] With the increasing miniaturization and high-speed performance of electronic products, more and more components are soldered on the surface of the circuit board, and the conductive line density and signal transmission amount of the circuit board are required to be larger and larger. To meet this demand, boards have evolved from single-panel to dual-panel and multi-layer boards. Among them, the double-sided circuit board and the multi-layer circuit board have a large wiring area and a high assembly density and are widely used, see the literature: Takahashi, A.; High density multilayer printed circuit board for HITAC M-880; IEEE Trans, on Components , Packaging Technology, 1992 o [0003] As a new type of multilayer circuit board that has emerged in recent years, a circuit board having a stepped structure has a small number of layers in a small number of layers due to its different layers in different regions. The rigidity is small, and the area with a large number of layers has high line density, large thickness and rigidity, so that it can transmit a large amount of information and has appropriate rigid flexibility. [0004] Referring to FIG. 1a, a schematic diagram of a multilayer circuit board 100 having a fault structure is shown. . The multilayer circuit board 100 is formed by a double-sided substrate 11+0 and a single-sided substrate 120. The first conductive line 111 of the double-sided substrate 110 is provided with a mounting area 112 for mounting electronic components. [0005] At present, a circuit board having a stepped structure is usually produced by a build-up method, that is, a layer stacking method. Taking the multilayer circuit board 100 as an example, the conventional manufacturing method package 097114143 Form No. A0101 Page 4 of 30 100321304 Bu 0 1358976 - 3 - 1100. 06.15 [Firstly, the double-sided substrate 110 is provided. The single-sided substrate 120 and the adhesive layer 130 ′′ refer to FIG. 1A and FIG. 2B. The surface of the double-sided substrate 11 is formed with a first conductive line 111, and the first conductive line 111 is provided with a mounting area 112 ′. The adhesive layer 130 is provided with a slit 131 corresponding to the size of the mounting region 112. The single-sided substrate 120 includes a substrate layer 121 and a conductive layer 122. Next, please refer to FIG. 1c, the single-sided substrate 120 is formed by the adhesive layer 130. The substrate layer 121 is pressed onto the surface of the first conductive line hi of the double-sided substrate 11 and the slit 131 is opposite to the mounting area 112. The conductive layer 122 of the single-sided substrate 120 is cut by a laser cutting device or a milling cutter. And the portion of the substrate layer 121 corresponding to the slits 131, so that the mounting region 112 is exposed; finally, the conductive layer is formed on the remaining conductive layer of the single-sided substrate 120. Of course, it is also possible to fabricate via holes penetrating the one-sided substrate 120 and the double-sided substrate 11 and the walls of the via holes. [0006] However, when the single-sided substrate 120 is a hard plate, since the material of the base material layer 121 is mostly a composite material composed of a mesh glass fiber and a polymer resin, the surface flatness of the single-sided substrate 120 is poor. The thickness varies greatly. When φ is used to remove a portion of the conductive layer 122 and a portion of the substrate layer 121 corresponding to the single-sided substrate 120 and the slit 131, the thickness difference is different due to the unevenness of the surface of the single-sided substrate 12, so that the single-sided substrate 120 needs to be different everywhere. Cutting energy, and the laser cutting process uses a certain energy to cut, so the cutting depth will be different everywhere, and it is very likely that the cutting is excessive, that is, a part of the first conductive line corresponding to the mounting area 112 of the double-sided substrate 110 Cut off. If the milling cutter is used instead, the thickness of each side of the single-sided substrate 12 is different, and it is difficult to grasp the insertion depth of the milling cutter, and damage the first conductive line in corresponding to the mounting area 112 of the double-sided substrate 11〇, resulting in the Part of the first conductive line 097114143 Form No. A0101 Page 5 / Total 30 pages 1003213041-0 1358976 On June 15th, 100th, Junzheng Saibai Road was broken, which reduced the pass rate of subsequent circuit board products and wasted production materials. In view of the above, it is necessary to provide a method for fabricating a circuit board substrate and a circuit board having a stepped structure, so as to improve the fabrication accuracy and the pass rate of the circuit board. [Summary of the Invention]
[0008] 一種電路板基板,其用於製作具有斷差結構之電路板。 該電路板基板包括依次壓合第一基板、黏合層及第二基 板。該第一基板包括第一基材層、形成於第一基材層至 少一表面之導電線路層。該導電線路層設有貼裝區。該 第二基板包括第二基材層及形成於該第二基材層至少一 表面之導電層。該黏合層設有貫通其相對兩表面之切口 。該導電線路層及第二基材層分別貼於黏合層之相對兩 表面,且貼裝區與切口相對。該導電層表面中部設有去 除區。該去除區包括第一去除區、第二去除區及位於第 一去除區及第二去除區之間且與第一去除區、第二去除 區相連之第三去除區。該第三去除區之相對兩端開設有 貫通第二基板之第一切槽及第二切槽,其於第一基材層 之投影與貼裝區於第一基材層之投影重合,並位於切口 於第一基材層之投影内。該第一切槽及第二切槽均與第 一去除區及第二去除區相連,且與切口相通。 [0009] 一種具有斷差結構之電路板之製作方法,其包括下述步 驟:提供第一基板、黏合層及第二基板,該第一基板包 括第一基材層、形成於第一基材層至少一表面之導電線 路層,該導電線路層設有貼裝區,該第二基板包括第二 097114143 表單编號A0101 第6頁/共30頁 1003213041-0 1358976[0008] A circuit board substrate for fabricating a circuit board having a stepped structure. The circuit board substrate includes a first substrate, an adhesive layer, and a second substrate. The first substrate includes a first substrate layer, and a conductive circuit layer formed on at least one surface of the first substrate layer. The conductive circuit layer is provided with a mounting area. The second substrate includes a second substrate layer and a conductive layer formed on at least one surface of the second substrate layer. The adhesive layer is provided with slits extending through opposite surfaces thereof. The conductive circuit layer and the second substrate layer are respectively attached to opposite surfaces of the adhesive layer, and the mounting area is opposite to the slit. A removal area is provided in the middle of the surface of the conductive layer. The removal zone includes a first removal zone, a second removal zone, and a third removal zone between the first removal zone and the second removal zone and connected to the first removal zone and the second removal zone. a first slot and a second slot extending through the second substrate are formed at opposite ends of the third removal region, and the projection of the first substrate layer coincides with the projection of the mounting region on the first substrate layer, and Located within the projection of the slit in the first substrate layer. The first slit and the second slit are connected to the first removal zone and the second removal zone, and communicate with the slit. [0009] A method for fabricating a circuit board having a stepped structure, comprising the steps of: providing a first substrate, an adhesive layer, and a second substrate, the first substrate comprising a first substrate layer, formed on the first substrate a conductive circuit layer of at least one surface of the layer, the conductive circuit layer is provided with a mounting area, and the second substrate comprises a second 097114143 Form No. A0101 Page 6 / Total 30 Page 1003213041-0 1358976
[0010] 100年.06月i5日修正替#頁 基材層及形成於該第二基材層至少一表面之導電層,該 黏合層設有貫通其相對兩表面之切口;於該導電層表面 t部定義出第一去除區、第二去除區及位於第一去除區 及第二去除區之間且與第一去除區、第二去除區相連之 第三去除區,該第三去除區之形狀及尺寸與貼裝區之形 狀及尺寸匹配,於第三去除區之相對兩端開設貫通第二 基板之第一切槽及第二切槽,該第一切槽及第二切槽之 邊緣均與第一去除區及第二去除區之邊緣相交;將第一 基板、黏合層及第二基板依次疊層並壓合,且使該導電 線路層及第二基材層分別緊貼於黏合層之相對兩表面, 該第三去除區於第一基材層之投影與貼裝區於第一基材 層之投影重合,並位於切口於第一基材層之投影内;向 第一切槽或第二切槽内注入膠料,使膠料填充切口,並 固化膠料;沿第一去除區及第二去除區之邊緣切割,以 除去第一去除區及第二去除區對應之第一基板及第二基 板,去除第三去除區對應之第二基板;去除膠料,從而 製得具有斷差結構之電路板。 本技術方案之具有斷差結構之電路板之製作方法藉由於 壓合第一基板及第二基板前於第二基板之導電層表面中 部定義出包括第一去除區、第二去除區及與預定貼裝區 形狀及尺寸匹配之第三去除區之去除區,並於第三去除 區相對兩端部開設貫通第二基板相對兩表面且分別與第 一去除區及第二去除區相連之第一切槽及第二切槽,於 壓合後採用固化後易剝離之膠料填充切口之方式,使得 去除第一去除區、第二去除區對應之第一基板及第二基 097114143 表單編號A0101 第7頁/共30頁 1003213041-0 1358976 [0011] [0012] [0013] [0014] 100年06月1Ξ日修正替_頁 板後,第三去除區對應之第二基板處於獨立狀態,將第 三去除區對應之第二基板與膠料分離,並移走膠料即可 得到具有斷差結構之電路板,從而克服了先前技術之製 作方法於去除貼裝區對應之第二基板時容易損傷貼裝區 内之導電線路從而導致導電線路粗細不一,甚至斷線之 缺陷。並且,由於本製作方法採用膠料填充切口,有效 避免了後續對該具有斷差結構之電路板進行電鍍及以濕 法製作導電線路時,電鍍液及蝕刻液與貼裝區内之導電 線路層接觸從而損傷該部分導電線路層。因此,使用本 技術方案之製作方法可顯著地提高電路板之線路製作精 < 度及產品合格率β 【實施方式】 以下將結合實施例及附圖對本技術方案提供之具有斷差 結構之電路板之製作方法進行詳細說明。 本實施例提供之具有斷差結構之電路板之製作方法包括 以下步驟: 第一步,提供第-基板2〇〇、第二基板3〇〇及點合層4〇〇 i 〇 請參閱圖2,第-基板2〇〇為包括至少一層導電線路之軟 板或硬板’其可為單面板 '雙面板或多層板其具體結 構依待製作之具有斷差結構之電路板之結構而定。本實 施例中,第-基板200為一雙面軟板’其包括第一基材層 210及分別位於第一基材層21〇相對兩表面之第一導電線 路層220及第二導電線路層230。 097114143 表單编號A0101 第8頁/共30頁 1003213041-0 1358976 [0015] 100年_06月15日按正_換頁 第'·~基材層210可為早層絕緣基材’亦可為早層導電線路 層與絕緣基材構成之複合基材。本實施例中,第一基材 層210為單層絕緣基材層。 [0016] 第一導電線路層220及第二導電線路層230之材質可為銅 、銀、金或其它常見金屬。本實施例中,第一導電線路 層220及第二導電線路層230為壓延銅箔經曝光、顯影、 蝕刻等工藝製成。當然,可直接提供具有雙面銅箔之覆 銅基材,然後再藉由分別於兩面銅箔表面鋪設乾膜、曝 光、顯影、蝕刻等工序形成第一導電線路層220及第二導 電線路層230。第一導電線路層220設有貼裝區221。 [0017] 請一併參閱圖2及圖3,貼裝區221用於後續採用表面貼裝 工藝將電子元件貼裝至電路板表面,其形狀及尺寸根據 實際需要而定。本實施例中,貼裝區221呈矩形,其位於 第一導電線路層220之中部。[0010] 100 years. 06 months i5 days to replace the # page substrate layer and a conductive layer formed on at least one surface of the second substrate layer, the adhesive layer is provided with a slit penetrating the opposite surfaces thereof; The surface t portion defines a first removal region, a second removal region, and a third removal region between the first removal region and the second removal region and connected to the first removal region and the second removal region, the third removal region The shape and the size are matched with the shape and the size of the mounting area, and the first slot and the second slot extending through the second substrate are formed at opposite ends of the third removal region, and the first slot and the second slot are The edges intersect with the edges of the first removal region and the second removal region; the first substrate, the adhesive layer and the second substrate are sequentially laminated and pressed, and the conductive circuit layer and the second substrate layer are respectively adhered to The opposite surfaces of the adhesive layer, the projection of the third removal region on the first substrate layer coincides with the projection of the mounting region on the first substrate layer, and is located in the projection of the slit in the first substrate layer; Injecting the compound into the grooving or the second grooving to fill the slit and solidify the rubber compound; Cutting along the edges of the first removal region and the second removal region to remove the first substrate and the second substrate corresponding to the first removal region and the second removal region, removing the second substrate corresponding to the third removal region; removing the rubber compound, Thus, a circuit board having a stepped structure is obtained. The manufacturing method of the circuit board with the fault structure of the present invention is defined by including the first removal area, the second removal area, and the predetermined portion by the middle of the surface of the conductive layer of the second substrate before pressing the first substrate and the second substrate a removal area of the third removal area matching the shape and the size of the mounting area, and opening opposite ends of the second removal substrate at opposite ends of the third removal area and respectively connected to the first removal area and the second removal area The grooving and the second grooving are filled in the slit after the pressing, and the first substrate and the second substrate corresponding to the first removal region and the second removal region are removed, so as to remove the first removal region and the second removal region corresponding to the first substrate and the second substrate 097114143 7 pages / total 30 pages 1003213041-0 1358976 [0012] [0014] [0014] After the correction of the _ page board on June 1st, 100, the second substrate corresponding to the third removal area is in an independent state, The second substrate corresponding to the three removal regions is separated from the rubber material, and the rubber material is removed to obtain a circuit board having a fault structure, thereby overcoming the prior art manufacturing method, which is easy to damage when removing the second substrate corresponding to the mounting area. Mounting area The conductive lines inside cause the thickness of the conductive lines to be different, and even the defects of the broken lines. Moreover, since the manufacturing method uses the rubber material to fill the slit, the plating circuit and the etching liquid and the conductive circuit layer in the mounting region are effectively avoided when the circuit board with the fault structure is subsequently plated and the conductive circuit is formed by the wet method. Contact to damage the portion of the conductive circuit layer. Therefore, the manufacturing method of the technical solution can significantly improve the circuit fabrication precision of the circuit board and the product yield rate β. [Embodiment] The circuit with the fault structure provided by the technical solution will be provided below with reference to the embodiments and the accompanying drawings. The method of making the board will be described in detail. The manufacturing method of the circuit board with the fault structure provided by this embodiment includes the following steps: First, the first substrate 2, the second substrate 3, and the puncture layer 4〇〇i are provided. The first substrate 2 is a flexible board or a hard board including at least one layer of conductive lines. It may be a single-panel 'double-panel or multi-layer board. The specific structure depends on the structure of the circuit board having a stepped structure to be fabricated. In this embodiment, the first substrate 200 is a double-sided flexible board, which includes a first substrate layer 210 and first conductive circuit layers 220 and second conductive circuit layers respectively located on opposite surfaces of the first substrate layer 21 230. 097114143 Form No. A0101 Page 8 / Total 30 Page 1003213041-0 1358976 [0015] 100 years _ June 15th according to positive _ page change '·~substrate layer 210 can be early layer insulation substrate' can also be early A composite substrate composed of a layer of a conductive circuit layer and an insulating substrate. In this embodiment, the first substrate layer 210 is a single-layer insulating substrate layer. [0016] The material of the first conductive circuit layer 220 and the second conductive circuit layer 230 may be copper, silver, gold or other common metals. In this embodiment, the first conductive wiring layer 220 and the second conductive wiring layer 230 are formed by exposing, developing, etching, etc. the rolled copper foil. Of course, the copper-clad substrate having the double-sided copper foil can be directly provided, and then the first conductive wiring layer 220 and the second conductive wiring layer can be formed by laying a dry film, exposing, developing, etching, etc. on the surface of the copper foil on both sides. 230. The first conductive wiring layer 220 is provided with a mounting area 221. [0017] Referring to FIG. 2 and FIG. 3 together, the mounting area 221 is used for subsequently mounting the electronic components on the surface of the circuit board by using a surface mount process, and the shape and size thereof are determined according to actual needs. In this embodiment, the mounting area 221 has a rectangular shape and is located in the middle of the first conductive wiring layer 220.
[0018] 第二基板300可為硬基板,亦可為軟基板,其結構根據實 際需要製作之具有斷差結構之電路板而定。本實施例中 ,第二基板300為一單面硬板,其包括第二基材層310及 形成於第二基材層310 —表面之導電層320,其具有第一 表面301及與第一表面301相對之第二表面302。其中, 第一表面301對應於第二基材層310之表面,第二表面 302對應於導電層320之表面。 [0019] 第二基材層310可為單層絕緣基材,亦可為單層導電線路 層與絕緣基材構成之複合基材。本實施例中,第二基材 層300為由單層絕緣樹脂與玻璃纖維組成之複合絕緣基材 097114143 表單編號A0101 第9頁/共30頁 1003213041-0 1358976 [0020] [0021] [0022] 097114143[0018] The second substrate 300 may be a hard substrate or a soft substrate, and the structure thereof is determined according to a circuit board having a stepped structure which is actually required to be fabricated. In this embodiment, the second substrate 300 is a single-sided hard board, and includes a second substrate layer 310 and a conductive layer 320 formed on the surface of the second substrate layer 310, having a first surface 301 and first Surface 301 is opposite second surface 302. The first surface 301 corresponds to the surface of the second substrate layer 310, and the second surface 302 corresponds to the surface of the conductive layer 320. [0019] The second substrate layer 310 may be a single-layer insulating substrate, or may be a composite substrate composed of a single-layer conductive wiring layer and an insulating substrate. In this embodiment, the second substrate layer 300 is a composite insulating substrate composed of a single layer of insulating resin and glass fibers 097114143. Form No. A0101 Page 9 of 30 pages 1003213041-0 1358976 [0022] [0022] 097114143
IdO年C6月15日核正替換頁 導電層320之材質為銅、銀、金或其它常見金屬,本實施 例中,其為壓延銅箔。 黏合層400用於後續壓合工藝中黏接第一基板200及第二 基板300,其為本領域常用之膠黏劑,如環氧樹酯膠黏劑 。黏合層400開設有與貼裝區221相對應之切口 410。 切口 410可採用衝裁設備衝出,其可為不同形狀之通孔, 如圓形、矩形或其它多切割線形等。切口410相對於黏合 層400之位置根據貼裝區221相對第一導電線路層220之 位置而定,但應滿足後續壓合第一基板200及第二基板 300時,設有切口 410之黏合層400能完全黏附第二基材 層310之第一表面301及第一導電線路層220。請參閱圖2 、圖3及圖4,切口410之尺寸應滿足當第一導電線路層 220及第二基材層310之第一表面301分別緊貼於黏合層 400之相對兩表面時,貼裝區221相對於第一基材層210 之投影位於切口 410相對於第一基材層210之投影内。優 選地,切口410之橫截面形狀及尺寸與貼裝區221之形狀 及尺寸匹配。本實施例中,黏合層400被切斷成第一黏合 部420及與第一黏合部420相對設置之第二黏合部430。 第一黏合部420具有第一切割面421,第二黏合部430具 有與第一切割面421相對之第二切割面431。第一切割面 421與第二切割面431配合形成切口 410。 第二步,於第二基板300之第二表面302之中部定義出去 除區303,該去除區30 3包括第一去除區3021、第二去除 表單编號A0101 第10頁/共30頁 1003213041-0IdO Year C June 15 Nuclear Replacement Page The conductive layer 320 is made of copper, silver, gold or other common metals. In this embodiment, it is a rolled copper foil. The adhesive layer 400 is used for bonding the first substrate 200 and the second substrate 300 in a subsequent pressing process, which is an adhesive commonly used in the art, such as an epoxy resin adhesive. The adhesive layer 400 is provided with a slit 410 corresponding to the mounting area 221. The slit 410 can be punched out by a punching device, which can be a through hole of a different shape, such as a circular, rectangular or other multi-cut line shape or the like. The position of the slit 410 relative to the adhesive layer 400 depends on the position of the mounting region 221 relative to the first conductive wiring layer 220, but should satisfy the adhesive layer provided with the slit 410 when the first substrate 200 and the second substrate 300 are subsequently pressed. 400 can completely adhere the first surface 301 of the second substrate layer 310 and the first conductive wiring layer 220. Referring to FIG. 2, FIG. 3 and FIG. 4, the size of the slit 410 is such that when the first surface 301 of the first conductive circuit layer 220 and the second substrate layer 310 are respectively adhered to opposite surfaces of the adhesive layer 400, The projection of the loading region 221 relative to the first substrate layer 210 is within the projection of the slit 410 relative to the first substrate layer 210. Preferably, the cross-sectional shape and size of the slit 410 matches the shape and size of the mounting area 221 . In this embodiment, the adhesive layer 400 is cut into a first adhesive portion 420 and a second adhesive portion 430 disposed opposite to the first adhesive portion 420. The first bonding portion 420 has a first cutting surface 421, and the second bonding portion 430 has a second cutting surface 431 opposite to the first cutting surface 421. The first cutting face 421 cooperates with the second cutting face 431 to form a slit 410. In the second step, a removal area 303 is defined in the middle of the second surface 302 of the second substrate 300. The removal area 30 3 includes a first removal area 3021, a second removal form number A0101, a 10th page, a total of 30 pages, 1003213041- 0
[0023] 1358976 :1加年:06月立5日慘正_^ 區30 22及位於第一去除區3021及第二去除區3022之間並 與第一去除區3021及第二去除區3022相連之第三去除區 3031,並於第三去除區3031之相對兩端開設貫通第一表 面301及第二表面302且與第一去除區3021及第二去除區 3022相連之第一切槽3023及第二切槽3024。[0023] 1358976: 1 plus year: June 5th is ugly _^ zone 30 22 and located between the first removal zone 3021 and the second removal zone 3022 and is connected to the first removal zone 3021 and the second removal zone 3022 a third removal region 3031, and a first slot 3023 extending through the first surface 301 and the second surface 302 and connected to the first removal region 3021 and the second removal region 3022 at opposite ends of the third removal region 3031 and The second slot 3024.
[0024] 請一併參閱圖3及圖4,去除區303之定義可採用蝕刻導電 層320表面而成,亦可直接於第二表面302劃標誌線,只 要能起到標識作用即可。本實施例中,去除區303位於導 電層320之中部,且其一組對邊與導電層320之一組對邊 共邊。具體地,第一去除區3021呈矩形,其由首尾依次 相連之第一切割線3025、第二切割線3026及第三切割線 3027及與第二表面302之一邊圍合而成。第二去除區 3022由首尾依次相連之第四切割線3028、第五切割線 3029、第六切割線3030及於第二表面302之一邊圍合而 成。第三去除區3031與第一去除區3021相交於第二切割 線3026,與第二去除區3022相交於第五切割線3029,其 相對於第一基材層210之投影與貼裝區221相對於第一基 材層210之投影重合。當然,去除區303亦可不與第二表 面302之邊緣共邊。 [0025] 第三步,將第一基板200、黏合層400及第二基板30 0依 次疊層並壓合。 [0026] 請一併參閱圖3、圖4及圖5,第一基板200、黏合層400 及第二基板300之疊層及壓合應使得第二基材層310及第 一導電線路層220分別緊貼於黏合層400相對之兩表面, 且貼裝區221與切口 410及第三去除區3031相對應,亦即 097114143 表單編號A0101 第11頁/共30頁 1003213041-0 1358976 100年.06月15日修正替換頁 第三去除區3031相對於第一基材層210之投影與貼裝區 221於第一基材層210之投影重合,貼裝區221對第一基 材層210之投影位於切口 410對第一基材層210之投影内 ,由此得電路板基板700。 [0027] 第四步,向電路板基板700之第一切槽3023或第二切槽 3024内注入膠料500,使其填充切口 410,並固化膠料 500 » [0028] 請一併參閱圖4、圖5及圖6,第一基板200、第二基板Referring to FIG. 3 and FIG. 4 together, the definition of the removal region 303 may be formed by etching the surface of the conductive layer 320, or may be directly marked on the second surface 302, as long as it can function as a mark. In this embodiment, the removal region 303 is located in the middle of the conductive layer 320, and a pair of opposite sides is co-edge with a pair of opposite sides of the conductive layer 320. Specifically, the first removal area 3021 has a rectangular shape, and is formed by a first cutting line 3025, a second cutting line 3026, and a third cutting line 3027 which are sequentially connected end to end and one side of the second surface 302. The second removal zone 3022 is formed by a fourth cutting line 3028, a fifth cutting line 3029, a sixth cutting line 3030, and one side of the second surface 302, which are sequentially connected end to end. The third removal zone 3031 intersects the first removal zone 3021 at the second cutting line 3026, and the second removal zone 3022 intersects the fifth cutting line 3029, and the projection relative to the first substrate layer 210 is opposite to the placement area 221 The projections on the first substrate layer 210 coincide. Of course, the removal zone 303 may also not be co-edge with the edge of the second surface 302. [0025] In the third step, the first substrate 200, the adhesive layer 400, and the second substrate 30 0 are sequentially laminated and pressed. Referring to FIG. 3, FIG. 4 and FIG. 5, the first substrate 200, the adhesive layer 400 and the second substrate 300 are laminated and pressed so that the second substrate layer 310 and the first conductive circuit layer 220 are formed. They are respectively adhered to the opposite surfaces of the adhesive layer 400, and the mounting area 221 corresponds to the slit 410 and the third removal area 3031, that is, 097114143 Form No. A0101 Page 11 of 30 1003213041-0 1358976 100 years.06 On the 15th of the month, the projection of the third removal region 3031 with respect to the first substrate layer 210 coincides with the projection of the mounting region 221 on the first substrate layer 210, and the projection of the mounting region 221 to the first substrate layer 210 is performed. Located within the projection of the slit 410 to the first substrate layer 210, the circuit board substrate 700 is thereby obtained. [0027] In the fourth step, the rubber 500 is injected into the first slot 3023 or the second slot 3024 of the circuit board substrate 700 to fill the slit 410 and cure the rubber 500 » [0028] Please refer to the figure together 4, FIG. 5 and FIG. 6, the first substrate 200 and the second substrate
300及黏合層400壓合後,第一切槽3023及第二切槽3024 與切口 410相通。膠料500用以填充切口 410,以遮蓋貼 裝區221對應之第一導電線路層220,進而防止後續進行 濕法製作如於導電層320形成導電線路時,蝕刻液沿第一 切槽3023及第二切槽3024進入貼裝區221腐蝕貼裝區221 對應之第一導電線路層220。膠料500可以印刷方式填入 ,亦可採用本領域常見之其它方式注入,優選地,其用 量以剛好與第二表面302相平為宜。膠料500選用經紫外 光照或微熱可固化,且固化後容易被剝離之黏接性材料 。本實施例中,膠料500選用本領域常用之紫外光固化膠 料,且其填滿第一切槽3023、第二切槽3024及切口 410 [0029] 第五步,沿第一去除區3021及第二去除區3022之邊緣切 割,以除去第一去除區3021及第二去除區3022對應之第 一基板200及第二基板300,移除第三去除區3031對應之 第二基板300。 097114143 表單编號A0101 第12頁/共30頁 100321304卜0 1358976 [0030]After the 300 and the adhesive layer 400 are pressed together, the first slit 3023 and the second slit 3024 communicate with the slit 410. The rubber material 500 is used to fill the slit 410 to cover the first conductive circuit layer 220 corresponding to the mounting region 221, thereby preventing subsequent wet processing. When the conductive layer 320 forms a conductive line, the etching liquid is along the first slit 3023 and The second slit 3024 enters the first conductive layer 220 corresponding to the affixing area 221 of the mounting area 221 . The size 500 can be filled in by printing or by other means common in the art, preferably in a level that is just as level as the second surface 302. The compound 500 is made of an adhesive material which is curable by ultraviolet light or micro heat and which is easily peeled off after curing. In this embodiment, the rubber 500 is selected from the ultraviolet curing compound commonly used in the art, and fills the first slit 3023, the second slit 3024, and the slit 410 [0029]. The fifth step is along the first removal region 3021. And cutting the edge of the second removal region 3022 to remove the first substrate 200 and the second substrate 300 corresponding to the first removal region 3021 and the second removal region 3022, and removing the second substrate 300 corresponding to the third removal region 3031. 097114143 Form No. A0101 Page 12 of 30 100321304 Bu 0 1358976 [0030]
, loo年.od is自修正_頁 請一併參見圖4及圖7,由於第一去除區3021及第二去除 區3022之一邊邊緣分別與第二表面3〇2之一邊共邊,因此 ,第一去除區3021對應之第一基板200及第二基板300可 沿第一切割線3025、第二切割線3026及第三切割線3027 裁切或雷射切割得以去除,第二去除區3022對應之第一 基板200及第二基板300可沿第四切割線3028、第五切割 線3 029及第六切割線3030裁切或雷射切割來去除。其中 ’雷射種類應根據第二基材層310之材質進行相應選擇。 一般來說,摻鉉釔鋁石榴石Nd:YAG雷射器發射之雷射波 長較短,屬紫外波段,脈衝頻率較高,可用於切割導電 層及絕緣層。當然,亦可選擇混合雷射系統,即,以 Nd:YAG雷射切割導電層,以(:〇2雷射切割絕緣層。本實施 例中’以Nd:YAG雷射切割第一去除區3021及第二去除區 3022對應之第一基板200及第二基板300。 [0031] 請一併參閱圖4、圖6及圖7,由於第三去除區3031内設置 有與第一去除區3021之一邊邊緣即第二切割線3026及第 二去除區3022之一邊邊緣即第四切割線3029相連之第一 切槽3023及第二切槽3024,因此當沿第二切割線3026及 第四切割線3029去除第一去除區3021及第二去除區3022 對應之第一基板200及第二基板300後,第三去除區3031 對應之第二基板3〇〇將處於獨立狀態,而膠料500固化後 黏接性較差,此時直接將第三去除區3031對應之第二基 板200與膠料500相分離即可移走該部分第二基板200。 [0032] 第五步,除去膠料5〇〇,從而製得具有斷差結構之電路板 600 〇 097114143 表單編號A0101 第13頁/共30頁 1003213041-0 1358976 " 100年06月15日节正替#頁 [0033]請一併參閱圖7及圖8,由於膠料5〇〇固化後易剝離,因此 ,直接撕去膠料500即可。, loo year.od is self-correcting_page Please refer to FIG. 4 and FIG. 7 together, since one edge of the first removal area 3021 and the second removal area 3022 is respectively co-edge with one side of the second surface 3〇2, therefore, The first substrate 200 and the second substrate 300 corresponding to the first removal region 3021 can be cut along the first cutting line 3025, the second cutting line 3026 and the third cutting line 3027 or the laser cutting is removed, and the second removal area 3022 corresponds to The first substrate 200 and the second substrate 300 may be removed by cutting or laser cutting along the fourth cutting line 3028, the fifth cutting line 3 029, and the sixth cutting line 3030. Wherein 'the type of laser should be selected according to the material of the second substrate layer 310. In general, the erbium-doped yttrium aluminum garnet Nd:YAG laser emits a short laser wave length, which is in the ultraviolet band and has a high pulse frequency, which can be used to cut the conductive layer and the insulating layer. Of course, a hybrid laser system may also be selected, that is, the conductive layer is cut by Nd:YAG laser to cut the insulating layer by (: 〇 2 laser. In the present embodiment, the first removal area 3021 is cut by Nd:YAG laser. And the first substrate 200 and the second substrate 300 corresponding to the second removal region 3022. [0031] Please refer to FIG. 4, FIG. 6 and FIG. 7 together, because the third removal region 3031 is provided with the first removal region 3021. The first cutting groove 3023 and the second cutting groove 3024 are connected to one edge, that is, the second cutting line 3026 and the second cutting line 3022, and thus are along the second cutting line 3026 and the fourth cutting line. After the first substrate 200 and the second substrate 300 corresponding to the first removal region 3021 and the second removal region 3022 are removed, the second substrate 3 corresponding to the third removal region 3031 will be in an independent state, and after the rubber 500 is cured. The adhesiveness is poor. In this case, the second substrate 200 corresponding to the third removal region 3031 is directly separated from the rubber 500 to remove the portion of the second substrate 200. [0032] In the fifth step, the rubber is removed. , thereby producing a circuit board with a fault structure 600 〇 097114143 Form No. A0101 No. 13 / Total 30 pages 1003213041-0 1358976 " 100 years of June 15th section for the replacement #页[0033] Please refer to Figure 7 and Figure 8, because the rubber 5 易 is easy to peel after curing, therefore, directly tear off The compound 500 can be used.
[0034] 本實施例之具有斷差結構之電路板6〇〇還可包括於導電層 320表面貼乾臈、曝光、顯影、蝕刻形成導電線路之步驟 。另外,還可包括製作貫通導電層320及第二導電線路層 230之通孔、將通孔孔壁電鍍之步驟,以導通導電層32〇 與第二導電線路層230,使得第二導電線路層230與導電 層320之間可達成訊號傳輸。如果通孔孔壁電鍍工藝係於 導電層320之線路圖案形成之後進行,則進行孔壁電鍍之 前應於導電層320之線路、第一導電線路層220及第二導 電線路層230之表面貼覆乾膜以保護線路圖案。 [0035] 综上所述,本發明嫁已符合發明專利之要件’遂依法提 出專利申請。惟,以上所述者僅為本發明之較佳實施方 式,自不能以此限制本案之申請專利範圍。舉凡熟悉本 案技藝之人士援依本發明之精神所作之等效修飾或變化 ,皆應涵蓋於以下申請專利範圍内》 【圖式簡單說明】 [0036] 圖la係先前技術之一種具有斷差結構之軟硬結合板之結 構示意圖。 [0037] 圖lb係圖la所示軟硬結合板之第一基板、第二基板及黏 合層之結構示意圖。 [0038] 圖lc係圖la所示軟硬結合板之習知製作方法中壓合及切 割第一基板之示意圖。 [0039] 圖2係本技術方案實施例提供之第一基板、第二基板及黏 097114143 表單编號A0101 第14頁/共30頁 1003213041-0 1358976 年06月i5·日修正替^頁 合層之結構示意圖。 [0040] 圖3係於圖2所示之第二基板設置第一切槽及第二切槽後 之立體圖。 [0041] 圖4係圖2所示之第一基板、黏合層與圖3所示之第二基板 壓合後得到之電路板基板之結構示意圖。 [0042] 圖5係圖4所示電路板基板沿V-V線之剖示圖。 [0043] 圖6係圖5所示電路板基板填充膠料後之示意圖。[0034] The circuit board 6 of the present embodiment having a stepped structure may further include the steps of: coating, exposing, developing, and etching the conductive layer on the surface of the conductive layer 320 to form a conductive line. In addition, the method further includes: forming a through hole penetrating the conductive layer 320 and the second conductive circuit layer 230, and plating the through hole hole wall to turn on the conductive layer 32 and the second conductive circuit layer 230, so that the second conductive circuit layer Signal transmission can be achieved between 230 and conductive layer 320. If the via hole wall plating process is performed after the formation of the wiring pattern of the conductive layer 320, the surface of the conductive layer 320, the first conductive wiring layer 220, and the second conductive wiring layer 230 should be pasted before the hole wall plating. Dry film to protect the line pattern. [0035] In summary, the present invention has been in compliance with the requirements of the invention patent 遂 提 patent application. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are intended to be included in the scope of the following claims. [Simplified Description of the Drawings] [0036] Figure la is a prior art one having a fault structure Schematic diagram of the structure of the soft and hard board. [0037] FIG. 1b is a schematic structural view of the first substrate, the second substrate, and the adhesive layer of the soft and hard bonding board shown in FIG. [0038] FIG. 1c is a schematic view of a first substrate in which a first substrate is pressed and cut in a conventional manufacturing method of the soft and hard bonding plate shown in FIG. 2 is a first substrate, a second substrate, and an adhesive 097114143 provided in an embodiment of the present technical solution. Form No. A0101 Page 14/Total 30 Page 1003213041-0 1358976 June i5·Day Correction Schematic diagram of the structure. 3 is a perspective view of the second substrate shown in FIG. 2 after the first slit and the second slit are provided. 4 is a schematic structural view of a circuit board substrate obtained by laminating a first substrate, an adhesive layer, and a second substrate shown in FIG. 5 is a cross-sectional view of the circuit board substrate shown in FIG. 4 taken along line V-V. 6 is a schematic view of the circuit board substrate shown in FIG. 5 after filling the rubber compound.
[0044] 圖7係圖6所示結構移去第三去除區對應之第二基板後之 示意圖。 [0045] 圖8係本技術方案實施例製作之具有斷差結構之電路板之 示意圖。 【主要元件符號說明】 [0046] 多層電路板:1 00 [0047] 雙面基板:1107 is a schematic view showing the structure shown in FIG. 6 after the second substrate corresponding to the third removal region is removed. 8 is a schematic diagram of a circuit board having a stepped structure fabricated by an embodiment of the present technical solution. [Main component symbol description] [0046] Multilayer circuit board: 1 00 [0047] Double-sided substrate: 110
[0048] 單面基板:120 [0049] 第一導電線路:111 [0050] 貼裝區:112、221 [0051] 黏合劑層:130 [0052]切口 : 1 31、41 0 [0053] 基材層:121 [0054] 導電層:122、320 097114143 表單編號A0101 第15頁/共30頁 1003213041-0 1358976 " 100年.06月15日核正_«百 [0055] 第一基板:200 [0056] 第二基板:300 [0057] 黏合層:400 [0058] 第一基材層:210 [0059] 第一導電線路層:220 [0060] 第二導電線路層:230 [0061] 第二基材層:310 [0062] 第一表面:301 [0063] 第二表面:302 [0064] 第一黏合部:420 [0065] 第二黏合部:430 [0066] 第一切割面:421 [0067] 第二切割面:431 · [0068] 去除區:303 [0069] 第一去除區:3021 [0070] 第二去除區:3022 [0071] 第三去除區:3031 [0072] 第一切槽:3023 [0073] 第二切槽:3024 097114143 表單編號A0101 第16頁/共30頁 1003213041-0 1358976 [0074] [0075] [0076] [0077] [0078] [0079] [0080][0048] Single-sided substrate: 120 [0049] First conductive line: 111 [0050] Mounting area: 112, 221 [0051] Adhesive layer: 130 [0052] Cutting: 1 31, 41 0 [0053] Substrate Layer: 121 [0054] Conductive layer: 122, 320 097114143 Form No. A0101 Page 15 / Total 30 pages 1003213041-0 1358976 " 100 years. June 15th Nuclear _«百 [0055] First substrate: 200 [ 0056] Second substrate: 300 [0057] Adhesive layer: 400 [0058] First substrate layer: 210 [0059] First conductive circuit layer: 220 [0060] Second conductive circuit layer: 230 [0061] Second base Material layer: 310 [0062] First surface: 301 [0063] Second surface: 302 [0064] First adhesive portion: 420 [0065] Second adhesive portion: 430 [0066] First cutting surface: 421 [0067] Second cutting surface: 431 · [0068] Removal area: 303 [0069] First removal area: 3021 [0070] Second removal area: 3022 [0071] Third removal area: 3031 [0072] First slot: 3023 [0073] Second slot: 3024 097114143 Form number A0101 Page 16 / Total 30 page 1003213041-0 1358976 [0075] [0075] [0078] [0079]
[0081] [0082] 100年.06月ί5日修正頁 第一切割線:3025 第二切割線:3026 第三切割線:3027 第四切割線:3028 第五切割線:3029 第六切割線:3030 電路板基板:700 膠料:50 0 電路板:600[0082] 100 years. 06 months ί5 day correction page first cutting line: 3025 second cutting line: 3026 third cutting line: 3027 fourth cutting line: 3028 fifth cutting line: 3029 sixth cutting line: 3030 Board Substrate: 700 Compound: 50 0 Board: 600
097114143 表單編號A0101 第17頁/共30頁 1003213041-0097114143 Form No. A0101 Page 17 of 30 1003213041-0
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