KR20090123032A - Method of manufacturing printed circuit board embedded with semiconductor chip - Google Patents

Method of manufacturing printed circuit board embedded with semiconductor chip Download PDF

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Publication number
KR20090123032A
KR20090123032A KR1020080048900A KR20080048900A KR20090123032A KR 20090123032 A KR20090123032 A KR 20090123032A KR 1020080048900 A KR1020080048900 A KR 1020080048900A KR 20080048900 A KR20080048900 A KR 20080048900A KR 20090123032 A KR20090123032 A KR 20090123032A
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South Korea
Prior art keywords
semiconductor chip
copper foil
cavity
printed circuit
circuit board
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KR1020080048900A
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Korean (ko)
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이광배
윤관선
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대덕전자 주식회사
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Priority to KR1020080048900A priority Critical patent/KR20090123032A/en
Publication of KR20090123032A publication Critical patent/KR20090123032A/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE: A manufacturing method of a printed circuit board embedded with a semiconductor chip is provided to prevent a crack of a semiconductor chip due to a stress by mounting a semiconductor chip inside a cavity of an insulation layer. CONSTITUTION: A board comprises a copper foil(10,30) and an insulation layer(20). The copper foil is coated in both surfaces of the insulation layer. A dry film is coated on the copper foil. A copper foil circuit is selectively developing and etching the copper foil according to the circuit pattern. A semiconductor chip is surface-mounted in a fixed position on the copper foil circuit. A cavity is formed by cutting an insulation layer(40) according to the circuit pattern. The semiconductor chip is mounted inside the cavity. An insulation layer(60) and a copper foil(70) are successively laminated on the semiconductor chip.

Description

반도체 칩 내장형 인쇄회로기판 제조 방법{METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD EMBEDDED WITH SEMICONDUCTOR CHIP}METHODS OF MANUFACTURING PRINTED CIRCUIT BOARD EMBEDDED WITH SEMICONDUCTOR CHIP}

본 발명은 인쇄회로기판(PCB; printed circuit board) 제조 기술에 관한 것으로, 특히 반도체 칩(semiconductor chip)과 같은 능동 소자(active device)를 인쇄회로기판에 내장한 임베디드(Embedded) 공법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board (PCB) manufacturing technology, and more particularly, to an embedded method in which an active device such as a semiconductor chip is embedded in a printed circuit board.

전자 기기의 휴대성과 기능을 향상시키기 위해, 능동 부품(active device) 또는 수동 부품(passive device)을 기판에 내장한 내장형 기판(Embedded Printed Circuit Board) 기술이 등장하였다. In order to improve the portability and function of electronic devices, an embedded printed circuit board technology, in which an active device or a passive device is embedded in a board, has emerged.

이와 같은 내장형 기판 기술을 적용하는 경우 기판의 소형화가 가능하고, 부품의 실장 밀도가 증가하여 전자 회로의 고주파 특성이 개선되는 등의 효과가 있다. 현재의 내장형 인쇄회로기판 기술은 그 공정의 특성상 주로 수동 부품을 내장하는 기술이 근간을 이루고 있으나, 최근 들어 국내의 PCB 업계에서는 IMBRA, HIDING DIES, BBUL 등의 기술이 개발되면서 능동 부품 내장형 기판 기술에 많은 관심이 고조되고 있다.When the embedded substrate technology is applied, the substrate can be miniaturized, and the mounting density of the component is increased to improve the high frequency characteristics of the electronic circuit. The current embedded printed circuit board technology is mainly based on the technology of embedding passive components due to the characteristics of the process, but recently, in the domestic PCB industry, technology such as IMBRA, HIDING DIES and BBUL has been developed. Much interest is rising.

일반적으로 능동 소자를 기판에 내장하기 위해서는 CCL(copper cladded laminate), 혹은 성형된 프리프레그(PREPREG) 층에 캐비티(cavity)를 가공하여 제작하고, 기판에 형성한 캐비티 속에 능동 소자를 고정하여 부착한 뒤에 동박이 피복된 절연층을 적층하고, 마이크로 비아 가공 기술과 도금 기술을 이용해서 기판과 연결하고 있다. Generally, in order to embed an active element into a substrate, a cavity is manufactured by processing a CCL (copper cladded laminate) or a molded prepreg layer, and the active element is fixed and attached to the cavity formed on the substrate. Later, the insulating layer coated with copper foil was laminated | stacked, and it connects with a board | substrate using a micro via processing technique and a plating technique.

그런데, 종래 기술의 경우 반도체 칩을 내장할 캐비티 공간을 만들기 위하여 드릴링 공정을 진행하여야 하고, 내장된 반도체 칩을 반복 동작시키는 과정에서 발생하는 열 피로(thermal fatigue)가 누적되면, 캐비티 주위의 상층 레이어들과 하층 레이어들 사이에 열 팽창 수축 정도가 서로 달라 기판이 뒤틀리거나 휘는 문제가 발생하게 된다.However, in the prior art, a drilling process must be performed to create a cavity space in which a semiconductor chip is to be embedded, and when thermal fatigue generated during the repeated operation of the embedded semiconductor chip is accumulated, an upper layer around the cavity is accumulated. The degree of thermal expansion and contraction between the layers and the lower layers is different, which causes the substrate to be warped or warped.

반도체 칩을 기판에 내장하는 종래 기술로서, 기판에 반도체 칩을 직접 실장한 후에 캐비티 가공을 하지 않고 언클래드(UNCLAD) 또는 프리프레그(PREPREG)와 같은 절연층을 적층하여 내장하는 방법이 있으나, 이 경우 공정이 단순해지는 반면에 칩에 심한 스트레스를 인가하여 칩이 손상되는 문제가 발생할 수 있는 단점이 있다. As a conventional technique in which a semiconductor chip is embedded in a substrate, there is a method in which an insulating layer such as UNCLAD or prepreg is laminated without a cavity after directly mounting the semiconductor chip on the substrate. In this case, while the process is simple, there is a disadvantage in that the chip is damaged by applying a severe stress to the chip.

따라서, 본 발명의 목적은 캐비티를 형성하지 않고서도 반도체 칩에 응력이 인가되지 않도록 칩을 인쇄회로기판에 내장하는 제조 기술을 제공하는 데 있다.Accordingly, it is an object of the present invention to provide a fabrication technique in which a chip is embedded in a printed circuit board so that stress is not applied to the semiconductor chip without forming a cavity.

상기 목적을 달성하기 위하여, 본 발명은 CCL(copper clad laminates) 원판 위에 드라이 필름 도포, 사진, 현상, 식각 등의 일련의 이미지 작업을 진행하여 동박 회로와 패드를 형성한 후 원하는 위치에 반도체 칩을 표면 실장(SMT; surface mount technology) 작업을 통해 부착한다. 이어서, 칩 두께 이상의 프리프레그(PREPREG) 또는 UNCLAD (C 스테이지 상의 PREPREG)를 적층 시에 이미 실장된 반도체 칩이 관통할 수 있도록 재단한 후 이를 적층을 한다. In order to achieve the above object, the present invention proceeds a series of imaging operations such as dry film coating, photographing, developing, etching, etc. on a copper clad laminates (CCL) plate to form a copper foil circuit and a pad, and then a semiconductor chip at a desired position It is attached via surface mount technology (SMT). Subsequently, the prepreg (PREPREG) or UNCLAD (prepreg on the C stage) having a chip thickness or more is cut to allow penetration of the semiconductor chip that is already mounted at the time of lamination, and then stacked.

프리프레그 또는 UNCLAD를 미리 재단하여 캐비티를 형성한 후 반도체 칩이 실장된 기판 위에 상기 캐비티 공간으로 반도체 칩이 관통하도록 정렬하여 적층을 함으로써 반도체 칩에는 스트레스가 인가되지 않는다. 그 결과, 공정 중에 발생할 수 있는 칩의 크랙을 방지할 수 있으며, 종래 기술과 달리 불필요한 프리프레그의 두께를 줄여서 총 두께를 감소할 수 있다. 적층 완료 후에 기존의 방법대로 레이저 비아를 형성하고 동박 도금을 한 후에 외층 회로를 형성하여 칩과 PCB 기판 사이에 전기적 접속을 완료한다. The prepreg or UNCLAD is cut in advance to form a cavity, and then the semiconductor chip is aligned and stacked so that the semiconductor chip penetrates into the cavity space on the substrate on which the semiconductor chip is mounted so that no stress is applied to the semiconductor chip. As a result, it is possible to prevent cracking of the chip that may occur during the process, and unlike the prior art, it is possible to reduce the total thickness by reducing the thickness of the unnecessary prepreg. After the lamination is completed, laser vias are formed and copper foil plating is performed according to the conventional method, and an outer layer circuit is formed to complete electrical connection between the chip and the PCB substrate.

이상과 같이, 본 발명은 반도체 칩을 표면 실장한 후에, 프리프레그 또는 언클래드를 재단하여 캐비티를 형성한 후에 기판에 적층하게 되므로 반도체 칩에 전혀 스트레스를 인가하지 아니하고 프리프레그의 두께를 감소할 수 있는 장점이 있다. As described above, according to the present invention, since the semiconductor chip is surface mounted, the prepreg or the unclad is cut to form a cavity, and then laminated on the substrate, the thickness of the prepreg can be reduced without applying any stress to the semiconductor chip. There is an advantage.

본 발명은 반도체 칩을 내장한 인쇄회로기판을 제조하는 방법에 있어서, (a) 절연층을 사이에 두고 양면에 동박이 피복되어 있는 기판의 동박을 선택적으로 식 각하여 선정된 회로 패턴에 따라 동박 회로를 형성하는 단계; (b) 상기 동박 회로 위에 회로 패턴에 따른 선정된 위치에 반도체 칩을 표면 실장하는 단계; (c) 프리프레그(PREPREG) 또는 언클래드(UNCLAD) 복수 장을 겹쳐 구성한 구조물을 선정된 회로 패턴에 따라 재단하여 캐비티를 형성하는 단계; 및 (d) 상기 캐비티 내부에 상기 실장한 반도체 칩이 안치되도록 상기 재단하여 캐비티가 형성된 구조물을 정렬하여 적층하고 그 위에 절연층과 동박을 적층하여 라미네이트하는 단계를 포함하는 인쇄회로기판 제조 방법을 제공한다.The present invention relates to a method for manufacturing a printed circuit board having semiconductor chips embedded therein, the method comprising (a) selectively etching copper foil of a substrate on which copper foil is coated on both surfaces with an insulating layer interposed therebetween, according to a circuit pattern selected. Forming a circuit; (b) surface-mounting the semiconductor chip on the copper foil circuit at a predetermined position according to a circuit pattern; (c) forming a cavity by cutting a structure consisting of a plurality of prepregs or unclad sheets according to a predetermined circuit pattern; And (d) aligning and stacking the cut and cavity-structured structures so that the mounted semiconductor chip is placed inside the cavity, and laminating by laminating an insulating layer and copper foil thereon. do.

이하에서는, 첨부 도면 도1a 내지 도1d를 참조하여 본 발명의 양호한 실시예를 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 1A to 1D.

도1a를 참조하면, 프리프레그와 같은 절연층(20) 양면에 동박(10, 30)이 피복된 구조에서 시작한다. 본 발명의 양호한 실시예로서, CCL (copper clad laminates)를 사용할 수 있다. 절연층(20) 양면에 동박(10, 30)이 피복된 구조의 양면에 대해 드라이 필름(D/F; 도시하지 않음)을 도포하고, 선정된 회로 패턴을 기판에 전사하기 위하여 사진 공정, 현상 및 식각 공정을 진행하여 이미지 작업을 완성하면 도1b에 나타낸 바와 같이 기판 양면에 동박 회로를 형성한다.Referring to FIG. 1A, it starts with a structure in which copper foils 10 and 30 are coated on both sides of an insulating layer 20 such as a prepreg. As a preferred embodiment of the present invention, copper clad laminates (CCL) can be used. Photographic process and development to apply a dry film (D / F; not shown) on both sides of the structure where the copper foils 10 and 30 are coated on both sides of the insulating layer 20 and transfer the selected circuit pattern to the substrate. And the etching process is completed to form the image of copper foil on both sides of the substrate as shown in Figure 1b.

이어서, 도1b를 참조하면 선정된 회로 패턴에 따라 원하는 위치에 반도체 칩(50)을 표면 실장한다. 그리고 나면, 프리프레그 또는 UNCLAD를 여러 장 적층하여 재단을 한다. 본 발명의 특징은, 종래 기술에서와 같이 실장된 반도체 칩 위에 프리프레그 또는 언클래드를 직접 적층하거나, 기판 위에 프리프레그 또는 언클래드를 적층한 후에 캐비티를 형성하고 캐비티 공간에 칩을 삽입하는 것이 아니라, 도1c에 도시한 바와 같이 미리 여러 장을 쌓아 만든 프리프레그 또는 언클래드와 같은 절연층(40)에 대해 캐비티를 형성하고 반도체 칩(50)이 실장된 기판 위에 반도체 칩이 캐비티 사이 공간을 관통하여 돌출되도록 정렬하여 적층하고 최종적으로 프리프레그(60)와 동박(70)을 적층하는 것을 특징으로 한다.1B, the semiconductor chip 50 is surface mounted at a desired position according to the selected circuit pattern. Then, several sheets of prepreg or UNCLAD are laminated and cut. A feature of the present invention is not to deposit a prepreg or unclad directly on a semiconductor chip mounted as in the prior art, or to form a cavity after laminating a prepreg or unclad on a substrate and insert the chip into the cavity space. As shown in FIG. 1C, a cavity is formed in an insulating layer 40 such as a prepreg or an unclad stacked in advance, and a semiconductor chip penetrates a space between the cavity on a substrate on which the semiconductor chip 50 is mounted. To arrange so as to protrude so that the prepreg 60 and the copper foil 70 are finally laminated.

도1d는 반도체 칩(50)이 실장된 기판에 미리 재단된 프리프레그층과 동박층을 적층 라미네이트하여 형성한 기판의 단면을 나타낸 도면이다. 이하, 이미지 작업을 진행하고 레이저 비아를 형성하여 반도체 칩(50)과 외부 동박 회로 사이를 전기적으로 접속하는 과정은 종래 기술을 그대로 적용할 수 있다.FIG. 1D is a cross-sectional view of a substrate formed by laminating a prepreg layer and a copper foil layer previously cut on a substrate on which the semiconductor chip 50 is mounted. Hereinafter, a process of performing an image operation, forming a laser via, and electrically connecting the semiconductor chip 50 and the external copper foil circuit may apply the prior art as it is.

전술한 내용은 후술할 발명의 특허 청구 범위를 더욱 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개선하였다. 본 발명의 특허 청구 범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다.  The foregoing has somewhat broadly improved the features and technical advantages of the present invention to better understand the claims that follow. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용될 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가능하다. In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

이상과 같이, 본 발명에 따른 칩 내장형 기판 제조 기술은 반도체 칩에 대해 스트레스 충격으로부터 칩을 보호할 수 있으며, 반복되는 열 피로(thermal fatigue)에 대해서도 내성이 있도록 하여 신뢰성이 배가된 반도체 칩 내장 기판 제조를 가능하게 한다.As described above, the chip embedded substrate manufacturing technology according to the present invention can protect the chip from the stress impact on the semiconductor chip, and is resistant to repeated thermal fatigue, thereby increasing the reliability of the semiconductor chip embedded substrate. Enable manufacturing.

도1a 내지 도1d는 본 발명에 따라 반도체 칩을 내장한 인쇄회로기판을 제조하는 방법을 나타낸 도면.1A to 1D illustrate a method of manufacturing a printed circuit board incorporating a semiconductor chip according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10, 30, 70: 동박10, 30, 70: copper foil

20, 40: 절연층     20, 40: insulation layer

50: 반도체 칩        50: semiconductor chip

60: 프리프레그        60: prepreg

Claims (1)

반도체 칩을 내장한 인쇄회로기판을 제조하는 방법에 있어서, In the method for manufacturing a printed circuit board containing a semiconductor chip, (a) 절연층을 사이에 두고 양면에 동박이 피복되어 있는 기판의 동박을 선택적으로 식각하여 선정된 회로 패턴에 따라 동박 회로를 형성하는 단계;(a) selectively etching the copper foil of the substrate coated with copper foil on both surfaces with an insulating layer interposed therebetween to form a copper foil circuit according to a selected circuit pattern; (b) 상기 동박 회로 위에 회로 패턴에 따른 선정된 위치에 반도체 칩을 표면 실장하는 단계; (b) surface-mounting the semiconductor chip on the copper foil circuit at a predetermined position according to a circuit pattern; (c) 프리프레그(PREPREG) 또는 언클래드(UNCLAD) 복수 장을 겹쳐 구성한 구조물을 선정된 회로 패턴에 따라 재단하여 캐비티를 형성하는 단계; 및(c) forming a cavity by cutting a structure consisting of a plurality of prepregs or unclad sheets according to a predetermined circuit pattern; And (d) 상기 캐비티 내부에 상기 실장한 반도체 칩이 안치되도록 상기 재단하여 캐비티가 형성된 구조물을 정렬하여 적층하고 그 위에 절연층과 동박을 적층하여 라미네이트하는 단계(d) aligning and stacking the cut and cavity-structured structures so that the mounted semiconductor chip is placed inside the cavity, and laminating by laminating an insulating layer and copper foil thereon; 를 포함하는 인쇄회로기판 제조 방법.Printed circuit board manufacturing method comprising a.
KR1020080048900A 2008-05-27 2008-05-27 Method of manufacturing printed circuit board embedded with semiconductor chip KR20090123032A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103079360A (en) * 2012-12-28 2013-05-01 广州杰赛科技股份有限公司 Processing method for embedded circuit board
CN104010445A (en) * 2014-05-09 2014-08-27 东莞市五株电子科技有限公司 Dynamic compensation manufacturing method for fine circuit
CN105072824A (en) * 2015-07-27 2015-11-18 广州杰赛科技股份有限公司 Manufacture method of embedded circuit board
CN110798974A (en) * 2018-08-01 2020-02-14 宏启胜精密电子(秦皇岛)有限公司 Embedded substrate, manufacturing method thereof and circuit board with embedded substrate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103079360A (en) * 2012-12-28 2013-05-01 广州杰赛科技股份有限公司 Processing method for embedded circuit board
CN104010445A (en) * 2014-05-09 2014-08-27 东莞市五株电子科技有限公司 Dynamic compensation manufacturing method for fine circuit
CN105072824A (en) * 2015-07-27 2015-11-18 广州杰赛科技股份有限公司 Manufacture method of embedded circuit board
CN105072824B (en) * 2015-07-27 2017-12-01 广州杰赛科技股份有限公司 A kind of preparation method of embedded lines plate
CN110798974A (en) * 2018-08-01 2020-02-14 宏启胜精密电子(秦皇岛)有限公司 Embedded substrate, manufacturing method thereof and circuit board with embedded substrate
CN110798974B (en) * 2018-08-01 2021-11-16 宏启胜精密电子(秦皇岛)有限公司 Embedded substrate, manufacturing method thereof and circuit board with embedded substrate

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