TW200939439A - Lead frame and manufacturing method of circuit device using the lead frame - Google Patents

Lead frame and manufacturing method of circuit device using the lead frame Download PDF

Info

Publication number
TW200939439A
TW200939439A TW097146558A TW97146558A TW200939439A TW 200939439 A TW200939439 A TW 200939439A TW 097146558 A TW097146558 A TW 097146558A TW 97146558 A TW97146558 A TW 97146558A TW 200939439 A TW200939439 A TW 200939439A
Authority
TW
Taiwan
Prior art keywords
lead frame
support portion
hole
lead
frame
Prior art date
Application number
TW097146558A
Other languages
English (en)
Chinese (zh)
Inventor
Tetsuya Fukushima
Takashi Kitazawa
Original Assignee
Sanyo Electric Co
Sanyo Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co, Sanyo Semiconductor Co Ltd filed Critical Sanyo Electric Co
Publication of TW200939439A publication Critical patent/TW200939439A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
TW097146558A 2008-02-06 2008-12-01 Lead frame and manufacturing method of circuit device using the lead frame TW200939439A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008025930A JP5144294B2 (ja) 2008-02-06 2008-02-06 リードフレームおよびそれを用いた回路装置の製造方法

Publications (1)

Publication Number Publication Date
TW200939439A true TW200939439A (en) 2009-09-16

Family

ID=41071116

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097146558A TW200939439A (en) 2008-02-06 2008-12-01 Lead frame and manufacturing method of circuit device using the lead frame

Country Status (3)

Country Link
JP (1) JP5144294B2 (https=)
KR (1) KR20090086148A (https=)
TW (1) TW200939439A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI800266B (zh) * 2021-05-31 2023-04-21 日商Ｔｏｗａ股份有限公司 成型模、樹脂成型裝置及樹脂成型品的製造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5215980B2 (ja) * 2009-10-30 2013-06-19 株式会社三井ハイテック 半導体装置の製造方法
JP5397195B2 (ja) * 2009-12-02 2014-01-22 日立化成株式会社 光半導体素子搭載用基板の製造方法、及び、光半導体装置の製造方法
JP5613463B2 (ja) * 2010-06-03 2014-10-22 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
DE102015100025A1 (de) * 2015-01-05 2016-07-07 Osram Opto Semiconductors Gmbh Leiterrahmen
JP6695166B2 (ja) * 2016-02-23 2020-05-20 株式会社三井ハイテック リードフレーム、及び半導体パッケージの製造方法
JP6924411B2 (ja) * 2017-08-28 2021-08-25 大日本印刷株式会社 リードフレームおよび半導体装置の製造方法
TWI882639B (zh) * 2024-01-08 2025-05-01 大陸商蘇州震坤科技有限公司 減少切單時刀損耗的導線架結構

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077235A (ja) * 1999-09-06 2001-03-23 Mitsui High Tec Inc 半導体素子搭載用基板
JP3634757B2 (ja) * 2001-02-02 2005-03-30 株式会社三井ハイテック リードフレーム
JP3628971B2 (ja) * 2001-02-15 2005-03-16 松下電器産業株式会社 リードフレーム及びそれを用いた樹脂封止型半導体装置の製造方法
JP2007294715A (ja) * 2006-04-26 2007-11-08 Renesas Technology Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI800266B (zh) * 2021-05-31 2023-04-21 日商Ｔｏｗａ股份有限公司 成型模、樹脂成型裝置及樹脂成型品的製造方法

Also Published As

Publication number Publication date
JP2009188150A (ja) 2009-08-20
KR20090086148A (ko) 2009-08-11
JP5144294B2 (ja) 2013-02-13

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