TW200937667A - Package structure of chemical compound semiconductor device and fabricating method thereof - Google Patents

Package structure of chemical compound semiconductor device and fabricating method thereof Download PDF

Info

Publication number
TW200937667A
TW200937667A TW097105846A TW97105846A TW200937667A TW 200937667 A TW200937667 A TW 200937667A TW 097105846 A TW097105846 A TW 097105846A TW 97105846 A TW97105846 A TW 97105846A TW 200937667 A TW200937667 A TW 200937667A
Authority
TW
Taiwan
Prior art keywords
package structure
conductive film
die
groove
film
Prior art date
Application number
TW097105846A
Other languages
English (en)
Inventor
Pin-Chuan Chen
Shen-Bo Lin
Original Assignee
Advanced Optoelectronic Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Optoelectronic Tech filed Critical Advanced Optoelectronic Tech
Priority to TW097105846A priority Critical patent/TW200937667A/zh
Priority to US12/370,923 priority patent/US7893528B2/en
Priority to EP09153073.3A priority patent/EP2093811B1/en
Publication of TW200937667A publication Critical patent/TW200937667A/zh
Priority to US12/856,052 priority patent/US8298861B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

200937667 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種化合物半導體元件之封裝結構及其製 造方法，尤係關於一種光電半導體元件之薄型封裝結構及 其製造方法。 【先前技術】 由於光電元件中發光二極體（light emitting di〇de;LED) H 有體積小、發光效率高及壽命長等優點，因此被認為是次世代 綠色節能照明的最佳光源》另外液晶顯示器的快速發展及全彩 榮幕的流行趨勢’使白光系發光二極體除了應用於指示燈及大 型顯示幕等用途外，更切入廣大之消費性電子產品，例如：手 機及個人數位助理（PDA)。 圖1係習知表面黏著（SMD)元件之發光二極體元件之剖 面不意圖。發光一極體晶粒12係藉由固晶膠丨丨固定於絕緣層 13c上N型導電銅帛13b之表面，並藉由金屬導線15與p型 Φ 導電銅箱13a^N型導電銅箱13b電性相連，其中p型導電 銅们3a、N型導電㈣⑽及絕緣層nc構成具有電路之基 板13。另外，透明封膠材料14覆蓋於基板13、金屬導線η 及晶粒12上，可以保護整個發光二極體元件1〇不受環境及 外力之破壞。 發光一極體几件10係使用一般印刷電路板作為基板13，因 此其整體厚度因受限於基板13中絕緣層仏厚度而無法更 薄。然消費性電子產品趨向於輕、薄、短、小之外型，因此其 内部之各元件或外部殼體都需要小型化。另―方面，絕緣層… 200937667 多係散熱性較差之樹脂材料製成，因此不利於高功率發光化合 物半導體元件作為傳導熱量之散熱途徑。 圖2係美國公開專利第US20040090756號揭露一高積集封裝 結構之剖面示意圖。此種結構係在一暫時基材上塗佈絕緣層， 並且在絕緣層上設計並佈局出需要的線路。帛著嗜光二極體 曰曰粒221、222被黏著在基板23上’並利用打線技術（或覆晶⑺化 Ο ❹ c_))技術將晶粒221、222與基板23内部導線藉由金屬導線 25相互導通。晶粒221、如上方係利用模麼（m〇idi⑻製程將 傳=的環氧樹脂（epoxy)覆蓋在晶粒221、222上。為了要使整 體晶片達到薄型化，把暫時基材利用雷射或紫外光(uv)光昭射 使其與絕緣層分離，並在預留的焊墊上黏著錫球^，如此即可 =到高積集度與薄型㈣目的。唯此製程較為複雜， 增加成本。 j $ 件了 ：：述体市場上亟需要一種薄型光電化合物半導體元 改盖㈣ 厚度要更薄而能節省所佔空間，並且還要 【發明内容】 更有制用於尚功率元件之製作。 本發明係提供一種化合物半導體 造方法’該半導體元件係將外部電極㈣=…構及其製 遞電氣：因刷電路板介於晶粒及外部電極間傳 虱訊唬，因此可改善散熱不佳之問題。 1寻 本發明係提供—㈣薄型 造方法，由於使用薄型基板或金屬：之=結構及其製 了以更薄而能節省所佔曰，。 $之厚度 200937667 為達上述目的，本發明揭示一種化合物半導體元件之封 裝結構’丨包含-薄膜基板、—晶粒及—透明封膠材料。 該薄膜基板包含一第一導電臈、一第二導電膜及一絕緣介 電材料。該晶粒係固^於該第-導電膜之表面。該透明封 勝材料係覆蓋於該第—導電膜、該第二導電膜及該晶粒 上„亥第導電膜及該第二導電膜相對於該透明封膠之表 ❹ ❹ 面刀別作為電極，該絕緣介電材料介於該第一導電膜及該 第二導電膜之間。 該薄膜基板之厚度較佳地係為2〇〜5〇em。 該絕緣介電材料絲切⑽）、氮化邦叫、氮氧化石夕 (SiON) K匕鈕(Ta〇)、氧化鋁(A1〇)、氧化鈦⑺⑺、氮化 銘（AIN) It化飲（ΤιΝ)、環氧樹脂（ep()xy)、硬樹脂（smc_) 或高分子絕緣材料。 該晶粒可為發光二極體晶粒、雷射二極體或光感測晶粒。 該化合物半導體元件之料結構另包含至少—電性連接 該晶粒與該薄膜基板之金屬導線。該第一導電膜另包含一 可供該金屬導線熔接之第一打後 ^打線凹槽。又該第二導電膜另 包含-可供該金屬導㈣接之第二打線凹槽。 該化合物半導體元件之封|結構另包含複數個電性連接 該晶粒與該薄臈基板之凸塊。 該第一導電膜另包含一固晶 u日日凹槽，該晶粒係固定於該固 晶凹槽内。該固晶凹槽内批覆—反光層。 該化合物半導體元件之封裝結構 不。偁另包含一疊置於該薄膜 基板上被圖案化之絕緣材料層，发 ^其中該絕緣材料層包括一 200937667 一可供該金屬導線熔接之 供該晶粒固定之固晶凹槽及至少 打線凹槽。 本發明另揭示一種化人輪坐撞灿_ 、+ , D物半導體元件封裝結構之製造方 趙：：含：列步驟：提供一薄臈基板，其包括-第-導電 、第導電膜及—絕緣介電材料；將-晶粒固接於該 電膜上’使传該晶粒的正極電性連接至該第一導電
膜’而該晶粒的負極電性連接至該第二導電膜；以及將一 透明膠材包覆該晶粒。 該薄膜基板係由下列步驟製成··提供—薄板；於該薄板 上形成至少—溝槽以分隔該第—導電膜及該第二導電膜； 以及在該溝槽中填入一絕緣介電材料。 該溝槽係利用鑽孔製程、蝕刻製程或是金屬沖壓製程所 形成。 該製造方法另 包含於該第一導電膜形成一固
晶凹槽之步
、該製造方法另包含於該第一導電膜及該第二導電膜形成 複數個打線凹槽之步驟，其中該打線凹槽係可供至少一金 屬導線熔接之處。 邊製造方法另包含於該薄膜基板上疊置被圖案化之絕緣 材料層中該絕緣材料層包括—供該晶粒固定之固晶凹 槽及可供至少一金屬導線熔接之複數個打線凹槽。 該將該晶粒固接於該薄膜基板之步驟包含以打線接合戈 是覆晶接合方式將該晶粒電性連接至該薄膜基板。 【實施方式】 200937667 圖3A〜3C係本發明薄膜基板之製造方法之步驟示意 圖如圖3A所不，提供一厚度為20〜50/zm之薄板34， 例如：銅箱或傳導佳之金屬薄膜。再利用鑽孔製程、蝕刻 製程或是金屬㈣等製程於薄板34上形成一溝槽％，藉由 該溝槽33使兩側之第一導電膜31及第二導電膜32相互無 法導通，亦即電性獨立，如圖3B所示。並且在溝槽33中 填入絕緣介電材料35就可完成薄膜基板30之製作，例如： ❹ 氧化石夕（si〇)、氮化石夕（SiN)、氮氧化矽（si〇N)、氧化鈕 (TaO)、氧化鋁（A1〇)、氧化鈦（Ti〇)、氮化鋁氮化鈦 (TiN)、環氧樹脂（ep〇xy)、梦樹脂⑽k_)或高分子絕緣材 料等:藉此可增加第—導電膜31及第二導電膜32間絕緣 性與薄膜基板30之支撐剛性，如圖3C所示。 圖4A係本發明化合物半導體元件封裝結構之剖面示意 圖。化合物半導體元件40係利用固晶或黏晶（die b〇nding) 技術把化合物半導體晶粒43黏著在薄膜基板3〇之第一導 G 電膜3 1上，亦即晶粒43藉由固晶膠47固定於第一導電膜 3 1之表面。該化合物半導體晶粒43可為發光二極體晶粒、 雷射二極體晶粒或光感測晶粒。再經由金屬導線44使晶粒 43與薄膜基板30電性連接，如此薄膜基板3〇即成為晶粒 43及金屬導線44之封裝載體。最後再利用模壓製程使透明 封膠材料46覆蓋晶粒43、金屬導線44及薄膜基板3〇上， 從而達到防濕氣與保護的效果，該透明膠材料46可為環氧 樹脂（epoxy)或是矽氧烷（silicone)。 圖4B係圖4A之化合物半導體元件之上視圖。使透明封 200937667 膠材料46局部被移除，可以更清楚看晶粒43、金屬導線 44及薄膜基板30之連結關係，兩金屬導線44分別自晶粒 43表面向第—導電膜31及第二導電膜32延伸並連接。 圖5係係本發明另一實施例化合物半導體元件封裝結構 之剖面示意圖。化合物半導體元件50係利用覆晶製程將晶 粒43藉由凸塊（bump)54固定在薄膜基板3〇上。與圖4A 不同係該晶粒43之主動面翻轉朝向薄臈基板3〇,並利用錫 Q 球與晶粒43上之焊墊相接合而成為凸塊54,再經過迴焊後 則凸塊54與薄膜基板3〇會因錫膏融熔後又固化而電性相 導通。最後再利用模壓製程使透明封膠材料46覆蓋晶粒43 及薄膜基板30上，從而達到防濕氣與保護的效果。本實施 例之優點係電流路捏較短及散熱佳，相較於前一個實施例 並可以減少金屬導線之線弧高度（loop height)。 圖6係係本發明再一實施例化合物半導體元件封裝結構 之剖面示意圖。本實施例可更進一步減少封裝結構之厚度 〇 與增加封裝元件之亮度，其係在薄膜基板30a之第一導電 膜3Γ上形成一固晶凹槽411 ’並且在固晶凹槽411之四周 側壁與底部沈積一反光層412。可以利用光微影餘刻、電鑄 製私或疋鑽孔製程來形成該固晶凹槽411。晶粒43黏著在 該固晶凹槽411之底部，如此可形成一種類似杯狀反射腔 體。該晶粒43發出的側向光線能夠有效的經由反光層412 朝向上方反射’以增加化合物半導體元件封6〇之發光亮 度本實施例另—優.點為·當晶粒4 3被放置在固晶凹槽411 中’對於利用金屬導線44使晶粒43與薄膜基板30a間電 200937667 性連接’將會有效的降低金線的線弧高度，而可以更加達 到整體封裝結構的薄型化。 圖7係係本發明再一實施例化合物半導體元件封裝結構 之剖面示意圖。相較於上述實施例，本實施例可再進—步 減少封裝結構之厚度。於薄膜基板3〇b之第一導電膜3iM 上形成一打線凹槽4I3，可提供金屬導線44第二焊點之熔 接位置；同樣，第二導電臈32,上亦形成一打線凹槽421，
❹ 可提供另一金屬導線44第二桿點之熔接位置。由於金屬導 線44第二焊點之位置下降，因此可減少化合物 封70之封裝結構的厚度。 前述實施例係採光微影蝕刻、電鑄製程 形成固晶凹槽或打線凹槽，亦可以於薄膜基板3〇上:= 圖案化之絕緣材料層36,其係利用光微影㈣於絕緣層％ 上形成固晶凹槽41ι及打線凹槽413、421，如圖心。 如此不僅可減少化合物半導 _ h ㈣㈣讀封80之封裝結構的 2尚可以避免連接第二導電膜32之金屬導線Μ與第— 導電膜31間有不當接觸而短路。 圖9A-9D係本發明採電鑄劁 一土 形成固晶凹槽或打線凹神 例：於薄臈基板3〇上形成-圖案化之緣材料層36·: 例如.光阻材料。利用電鑄製 電…出…成長二程::;，電膜31及第二導 糊如：去光阻步物形成=37’再去除緣材料層 413、421。 成口日日凹槽411及打線凹槽 本發明之技術内 容及技術特點已揭示如上 然而熟悉本 200937667 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所揭示者’而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1係習知表面黏著（SMD)元件之發光二極體元件之剖面 示意圖； ❹ ❹ 圖2係美國公開專利第US2〇〇4〇〇9〇756號揭露—高積集封裝 結構之剖面示意圖； '、 圖3A〜3C係本發明薄膜基板之製造方法之步驟示意圖. 圖4A係本發明化合物半導體元件封裝結構之剖面;意 国係圖4A之化合物半 圖 -,一…,,〜丄％同 , 係係本發明另—實施例化合物半導體元件 之剖面示意圖； 再 之圖本發明再一實施例化合物半導體元件封裝結構 之發明再一實施例化合物半導體元件封裝結構 之施例化合物半導體元件封裝結構 圖9A-9D係本發明採電鑄製 之示意圖。 料Μ成固晶凹槽或打線凹槽
【主要元件符號說明J -12- 200937667 ❹ 10 發光二極體元件 11 固晶膠 12、 221 ' 222 晶粒 13 基板 13a P型導電銅箔 13b N型導電銅箔 13c 絕緣層 14 透明封膠材料 15 金屬導線 20 化合物半導體 23 基板 25 金屬導線 26 錫球 30、 30a〜30c 薄 31、 31’第一導電膜 32 第二導電膜 33 溝槽 34 薄板 35 絕緣介電材料 36、 36' 絕緣層 37 金屬層 40 化合物半導體元件 43 晶粒 44 金屬導線 46 透明封膠材料 47 固晶膠 50、 60、70、80 化合物半導體元件 54 凸塊 411 固晶凹槽 412 反光層 413 、421 打線凹槽 13-

Claims (1)

  1. 200937667 十、申請專利範圍： 1. 一種化合物半導體元件之封裝結構，包含： -薄膜基板’包含—第—導電臈、—第二導電媒及一 絕緣介電材料，其中該絕緣介電材料介於該第一 該第二導電膜之間； 、 一晶粒，固定於該第一導電膜之表面；以及 -透明封谬材料，係覆蓋於該第—導電膜、該第二導 電膜及該晶粒。
    2. 根據請求項丄之化合物半導體元件之封i结構其中該薄 膜基板之厚度為20〜50//m。 3. 根據請求項i之化合物半導體元件之封裝結構其中該絕 緣介電材料係氧切（Si〇)、氮切⑽）、氮氧化石夕 (SiON)氧化組（Ta〇)、氧化紹⑷〇)、氧化鈦⑺⑺、氮 化銘（A1N)、氮化鈦（TiN)、環氧樹脂一㈣、石夕樹脂 (silicone)或高分子絕緣材料。 4. 根據請求項1之化合物半導體元件之封裝結構，其中該晶 粒可為發光二極體晶粒、雷射二極體或光感測晶粒。 5. 根據喷求項i之化合物光電元件的封裝結構其另包含至 少一電性連接該晶粒與該薄膜基板之金屬導線。 6. 根據請求項κ化合物光電元件的封裝結構，其另包含複 數個電性連接該晶粒與該薄胰基板之凸塊。 7. =據請求項丨之化合物光電元件的封裝結構，其中該第一 V電膜另包含一固晶凹槽，該晶粒係固定於該固晶凹槽 内。 -14· 200937667 8. 根據請求項7之化合物光電元件的封裝結構，其中該固晶 凹槽内抵覆一反光層。 9. 氣據請求項5之化合物光電元件的封裝結構，其中該第一 導電膜另包含一可供該金屬導線熔接之第一打線凹槽。 1〇·根據請求項9之化合物光電元件的封襞結構，其中該第二 導電膜另包含一可供該金屬導線熔接之第二打線凹槽。 11·根據請求項k化合物光電元件的封裝結構，其另3包含 〇 疊置於該薄膜基板上被圖案化之絕緣材料層，其中該絕 緣材料層包括一供該晶粒固定之固晶凹槽。 12. 根據請求項5之化合物光電元件的封裝結構，其另包含 疊置於該薄膜基板上被圖案化之絕緣材料層，其中該絕 緣材料層包括一供該晶粒固定之固晶凹槽及至少—可供 該金屬導線溶接之打線凹槽。 13. —種化合物光電元件封裝結構的製造方法，其步驟包含： 提供薄膜基板，其包括一第一導電膜、一第二導電 〇 膜及一絕緣介電材料； 將一晶粒固接於該第一導電膜上，使得該晶粒的正極 電性連接至該第-導電膜，而該晶粒的負極電性連接至該 第二導電膜；以及 將一透明膠材包覆該晶粒。 K根據Μ求項13之化合物光電元件封裝結構的製造方法，其 中該薄膜基板係由下列步驟製成： 提供一薄板； 於該薄板上形成至少—溝槽时隔㉟第- $電膜及該 -15· 200937667 第一導電膜；以及 在該溝槽中填入一絕緣介電材料。 •根據請求们4之化合物光電元件封I結構的製造方法，盆 中該溝槽係利用鑽孔製程、韻刻製程或是金屬沖麼製程所 形成。 吓 16.根據請求項14之化合物光電元件封裝結構的製造方法，其 另包含於該第一導電膜形成一固晶凹槽之步驟。 八 ❹17.根據請求項16之化合物光電元件封裝結構的製造方法其 中該晶粒係固定於該固晶凹槽内 八 18·根據請求項14之化合物光電元件封裝結構的製造方法，其 另包含於該第—導電膜及該第二導電膜形成複數個打線 槽之步驟，其中該打線凹槽係可供至少—金屬導線熔接 之處。 19. 根據請求項14之化合物光電元件封裝結構的製造方法，其 另包含於該薄膜基板上疊置被圖案化之絕緣材料層，其中 Q 該絕緣材料層包括一供該晶粒固定之固晶凹槽及可供至 少一金屬導線熔接之複數個打線凹槽。 20. 根據請求項13之化合物光電元件封裝結構的製造方法，該 將該晶粒固接於該薄膜基板之步驟包含以打線接合或是 覆晶接合方式將該晶粒電性連接至該薄膜基板。 21. 根據請求項16或18之化合物光電元件封裝結構的製造方 法’其中該固晶凹槽或該打線凹槽係藉由光微影蝕刻、電 鑄製程或是鑽孔製程所形成。 •16-
TW097105846A 2008-02-20 2008-02-20 Package structure of chemical compound semiconductor device and fabricating method thereof TW200937667A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW097105846A TW200937667A (en) 2008-02-20 2008-02-20 Package structure of chemical compound semiconductor device and fabricating method thereof
US12/370,923 US7893528B2 (en) 2008-02-20 2009-02-13 Package structure of compound semiconductor device and fabricating method thereof
EP09153073.3A EP2093811B1 (en) 2008-02-20 2009-02-18 Package structure of compound semiconductor device
US12/856,052 US8298861B2 (en) 2008-02-20 2010-08-13 Package structure of compound semiconductor device and fabricating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW097105846A TW200937667A (en) 2008-02-20 2008-02-20 Package structure of chemical compound semiconductor device and fabricating method thereof

Publications (1)

Publication Number Publication Date
TW200937667A true TW200937667A (en) 2009-09-01

Family

ID=40433921

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097105846A TW200937667A (en) 2008-02-20 2008-02-20 Package structure of chemical compound semiconductor device and fabricating method thereof

Country Status (3)

Country Link
US (2) US7893528B2 (zh)
EP (1) EP2093811B1 (zh)
TW (1) TW200937667A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI424591B (zh) * 2011-08-23 2014-01-21 Jentech Prec Ind Co Ltd 發光二極體封裝結構及其製造方法
TWI425680B (zh) * 2010-10-29 2014-02-01 Advanced Optoelectronic Tech 發光二極體封裝結構

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI398933B (zh) * 2008-03-05 2013-06-11 Advanced Optoelectronic Tech 積體電路元件之封裝結構及其製造方法
KR20110018777A (ko) * 2009-08-18 2011-02-24 삼성엘이디 주식회사 발광 다이오드 패키지
US8502257B2 (en) * 2009-11-05 2013-08-06 Visera Technologies Company Limited Light-emitting diode package
TW201131708A (en) * 2010-03-08 2011-09-16 Harvatek Corp LED package structure for increasing heat-dissipating efficiency and method of manufacturing the same
US8598612B2 (en) * 2010-03-30 2013-12-03 Micron Technology, Inc. Light emitting diode thermally enhanced cavity package and method of manufacture
TWI472067B (zh) * 2010-04-28 2015-02-01 Lg Innotek Co Ltd 光學封裝及其製造方法
JP5676395B2 (ja) * 2010-08-09 2015-02-25 エルジー イノテック カンパニー リミテッド 発光素子
KR101114197B1 (ko) * 2010-08-09 2012-02-22 엘지이노텍 주식회사 발광 소자 및 이를 구비한 조명 시스템
KR101114719B1 (ko) * 2010-08-09 2012-02-29 엘지이노텍 주식회사 발광 소자 및 이를 구비한 조명 시스템
CN103022011B (zh) * 2011-09-23 2015-10-07 讯芯电子科技（中山）有限公司 半导体封装结构及其制造方法
JP5885499B2 (ja) * 2011-12-27 2016-03-15 株式会社ディスコ バイト切削方法
KR20150031849A (ko) * 2013-09-17 2015-03-25 (주)포인트엔지니어링 칩 실장용 기판 및 칩 패키지
EP3818298A4 (en) 2018-07-03 2022-03-23 Glowgadget, LLC FLEXIBLE LIGHTING PANEL AND LIGHTING BODY

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4215306B2 (ja) 1998-08-27 2009-01-28 シチズン電子株式会社 半導体のパッケージおよびその製造方法
JP3945037B2 (ja) * 1998-09-04 2007-07-18 松下電器産業株式会社 光電変換素子及びその製造方法
JP2002232018A (ja) * 2000-11-28 2002-08-16 Nippon Telegr & Teleph Corp <Ntt> 紫外光源の作製方法および紫外光源部品並びに光学装置の作製方法
DE10228634A1 (de) * 2002-06-26 2004-01-22 Osram Opto Semiconductors Gmbh Oberflächenmontierbare Miniatur-Lumineszenz-und/oder Photo-Diode und Verfahren zu deren Herstellung
JP2005535144A (ja) * 2002-07-31 2005-11-17 オスラム　オプト　セミコンダクターズ　ゲゼルシャフト　ミット　ベシュレンクテル　ハフツング 表面実装可能な半導体素子及び該半導体素子の製造のための方法
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP3910171B2 (ja) 2003-02-18 2007-04-25 シャープ株式会社 半導体発光装置、その製造方法および電子撮像装置
US7276782B2 (en) 2003-10-31 2007-10-02 Harvatek Corporation Package structure for semiconductor
DE10353679A1 (de) * 2003-11-17 2005-06-02 Siemens Ag Kostengünstige, miniaturisierte Aufbau- und Verbindungstechnik für LEDs und andere optoelektronische Module
US7183588B2 (en) * 2004-01-08 2007-02-27 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Light emission device
JP4608294B2 (ja) 2004-11-30 2011-01-12 日亜化学工業株式会社 樹脂成形体及び表面実装型発光装置並びにそれらの製造方法
US20060131708A1 (en) * 2004-12-16 2006-06-22 Ng Kee Y Packaged electronic devices, and method for making same
US7301225B2 (en) * 2006-02-28 2007-11-27 Freescale Semiconductor, Inc. Multi-row lead frame
US20090026470A1 (en) * 2007-07-23 2009-01-29 Novalite Optronics Corp. Super thin side-view light-emitting diode (led) package and fabrication method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI425680B (zh) * 2010-10-29 2014-02-01 Advanced Optoelectronic Tech 發光二極體封裝結構
TWI424591B (zh) * 2011-08-23 2014-01-21 Jentech Prec Ind Co Ltd 發光二極體封裝結構及其製造方法

Also Published As

Publication number Publication date
EP2093811B1 (en) 2017-01-11
US7893528B2 (en) 2011-02-22
US20090206358A1 (en) 2009-08-20
US20100304535A1 (en) 2010-12-02
US8298861B2 (en) 2012-10-30
EP2093811A3 (en) 2013-05-29
EP2093811A2 (en) 2009-08-26

Similar Documents

Publication Publication Date Title
TW200937667A (en) Package structure of chemical compound semiconductor device and fabricating method thereof
TWI325644B (en) Chip package and manufacturing thereof
TWI528595B (zh) 晶圓等級ｌｅｄ封裝及其製造方法
TWI313943B (en) Light emitting chip package and manufacturing thereof
TWI535077B (zh) 發光單元及其發光模組
AU2006254610B2 (en) Package structure of semiconductor light-emitting device
TW200905907A (en) Package structure of compound semiconductor device and fabrication method thereof
KR101659103B1 (ko) 반도체 소자를 위한 지지 몸체, 반도체 소자 및 지지 몸체의 제조 방법
TWI420695B (zh) 化合物半導體元件之封裝模組結構及其製造方法
TWI398933B (zh) 積體電路元件之封裝結構及其製造方法
TW200933927A (en) Light emitting diode package
TW201212303A (en) LED packaging structure and packaging method thereof
TW201208152A (en) Surface-mountable optoelectronic component and method of manufacturing a surface-mountable optoelectronic component
CN101630668A (zh) 化合物半导体元件及光电元件的封装结构及其制造方法
CN101621105A (zh) Led倒装芯片集成封装方法及采用该方法封装的led
CN101546737B (zh) 化合物半导体元件的封装结构及其制造方法
JP4288931B2 (ja) 発光装置及びその製造方法
CN103618041A (zh) 一种esd保护的led封装结构及其封装方法
TWI393273B (zh) 發光二極體組件之製造方法
TW200905912A (en) Light emitting diode packaging structure and manufacturing method thereof
TW201025676A (en) Compound semiconductor device package module structure and fabricating method thereof
TW201006000A (en) Light emitting diode and method of making the same
TWI362122B (en) Light-emitting diode package structure and method for manufacturing the same
TW201222896A (en) LED package and method of manufacturing the same
JP2006173196A (ja) 発光素子及びこれを用いた発光ダイオード