200924134 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種增層線路板之 指-種以雙介電層切之單層圖 :：：其： 方完::半嶋層封裝基板結構之増 【先前技術】 在一般多層封裝基板之製作上，其製 係由-核心基板開始，經過鐵孔、電錢金屬、塞孔: =面線=作等方式，完成一雙面結構之内層核心 板，之後再經由-線路增層製程完成—多㈣裝基 板。如第2 8圖所示，其係為一有核層封裝基板之剖 面不意圖。首先，準備一核心基板8〇，其中，該核 心基板8 〇係由一具預定厚度之芯層8 0 1及形成於 此芯層8 0 1表面之線路層8 〇 2所構成，且該芯層 8 0 1中係形成有複數個電鑛導通孔8 0 3，可藉以 連接該芯層8 0 1表面之線路層8 〇 2。 接著如第2 9圖〜第3 2圖所示，對該核心基板 8 0實施線路增層製程。首先’係於該核 心基板8 0 表面形成一第一介電層81，且該第一介電層81表 面並形成有複數個第一開口 8 2，以露出該線路層8 〇 2 ’之後’以無電電鍍或電鍍等方式於該第一介電 層8 1外露之表面形成一晶種層8 3，並於該晶種層 200924134 8 3上形成一圖案化阻層84，且其圖案化阻層84 中並有複數個第二開口 8 5，以露出部份欲形成圖案 化線路之晶種層8 3 ;接著，利用電錢之方式於該第 二開口 8 5中形成一第一圖案化線路層8 6及複數個 導電盲孔8 7，並使其第一圖案化線路層8 $得以透 過該複數個導電盲孔8 7與該核心基板8 0之線路層 8 0 2做電性導通，然後再進行移除該圖案化阻層8 4與蝕刻，待完成後係形成一第一線路增層結構8 a。 同樣地，該法係可於該第一線路增層結構8a之最外 層表面再運用相同之方式形成一第二介電層88及一 第二圖案化線路層8 9之第二線路增層結構8b，以逐 步增層方式形成一多層封裝基板。然而，此種製作方 法有佈線密度低、層數多及流程複雜等缺點。 另外，亦有利用厚銅金屬板當核心材料之方法， 可於經過钱刻及塞孔等方式完成一内層核心板後:再 經由一線路增層s程以完成一多層封裝基板。如第3 3圖〜第3 5圖所示，其係為另—有核層封裝基板之 剖面示意圖。首先，準備一核心基板g 〇，該核心基 板9〇係由-具職厚度之金屬層利用㈣與樹脂ς 孔9 〇 1以及鑽孔與電料孔9 Q 2等方式形成 層銅核心基板9 〇 ;之後，利用上述線路增層 於該核％基板9 〇表面形成一第一介電層9工及 ::案化線路層9 2 ’藉此構成一具第一線路增層社 構9 a。該法亦與上述方法相同，係可再利用一次線： 200924134 增層方式於該第一線路增層結構9 a之最外層表面形 成一第二介電層9 3及一第二圖案化線路層9 4，藉 此構成一具第二線路增層結構9b，以逐步增層方式形 成一多層封裝基板。然而，此種製作方法不僅其銅核 心基板製作不易，且亦與上述方法相同，具有佈線密 度低及流程複雜等缺點。故，一般習用者係無法符合 使用者於實際使用時之所需。 【發明内容】 本發明之主要目的係在於，可完成一半導體多層 封裝基板結構，可有效改善超薄核層基板板彎翹問題 及簡化傳統增層線路板之製作流程。 本發明之次要目的係在於，可依實際需求形成單 數多層之封裝基板，並可有效達到降低成品板厚度及 減少製作成本之目的。 為達以上之目的，本發明係一種增層線路板之製 作方法，首先，係以光學微影及蝕刻之方式製作單層 線路，藉此以做為增層結構之電性連接墊，之後再於 其接塾面以壓合之方式形成一三層結構之電路板，並 且可進一步以該三層結構電路板之上、下層分別做為 增層結構之電性連接墊，亦或係作為置晶側與球側之 完整線路，而在連接其置晶側、球側及中間各層之方 式則係以複數個電鍍盲孔或埋孔所導通，藉此以完成 一無核層多層封裝基板。 200924134 【實施方式】 請參閱『第1圖〜第24圖』所示，係分別為本 發明之製作流程示意圖、本發明之雙面基板剖面示意 圖、本發明具圖案化及電性連接之三層基板（一）剖 面示意圖、本發明具圖案化及電性連接之三層基板 (二）剖面示意圖、本發明具圖案化及電性連接之三 層基板（三）剖面示意圖、本發明具圖案化及電性連 接之三層基板（四）剖面示意圖、本發明具圖案化及 電性連接之三層基板（五）剖面示意圖、本發明且圖 案化及電性連接之三層基板（六）剖面示意圖、科 明具圖案化及電性連接之三層基板（七）刮面示、 士發明具圖案化及電性連接之三層基板（八）丨面示 ^圖、本發明具圖案化及電性連接之三層基板（九） 剖面示意圖、本發明具圖案化及電性連接之三層基板 (十）剖面示意圖、本發明具圖案化及電性連接之三 層基板（十一）剖面示意圖、本發明之置晶側與_ 線路層（-A)剖面示意圖、本發明之置晶側與球侧 ，路層（二A)剖面示意圖、本發明之置晶側與球側 、.路層（—A )剖面示意圖 '本發明之上下兩層線路 增層結構（一）剖面示意圖、本發明之上下兩 增層 盖 丨 π ^ e 、、口 （一）。彳面不思圖、本發明之上下兩層線路 «層結構（三）剖面示意圖、本發明之上下兩 ==構（四）剖面示意圖、本發明之上下兩層線路 曰層…構（五）剖面示意圖、本發明之上下兩層線路 200924134 六;剖面示意圖、本發明之上下兩層線路 “::L t示意圖及本發明之上下兩層線路 "…構（八）剖面示意圖。如圖所* 種增層線路板之製作方法，其至少包括下列::係- -包mr基板11:如第2圖所示，選擇 第—介電層30、-第-金屬層3 1及一第 一金屬層3 2之雙面基板1 ; (B)貼合第一、二阻層12:如第3圖所示， 为別於該雙面基板之第一金屬層3 1上貼合一第一阻 層3 3，以及該雙面基板之第二金屬層3 2上以& = 覆蓋狀貼合一第二阻層34; ' (C )形成複數個第一開口 13:如第4圖所示， 以曝光及顯影之方式在該第—阻層3 3上形成複數個 第一開口 3 5，以顯露其下之第一金屬層3工； (D)移除第一金屬層14 ··如第5圖所示，以 蝕刻之方式移除該第一開口 3 5下方之第一金屬層3 (E )形成第一線路層1 5 :如第6圖所示，移 除該第一阻層及該第二阻層，使該第一金屬層形成— 具有單面線路電性連接墊之第一線路層3 6 ; (F)形成二層結構之電路基板16:如第7圖 所示，於該第一線路層3 6及該第一介電層3 〇上直 接壓合一與該第一介電層30相同之第二介電層37 及一第三金屬層3 8，以形成一三層結構之電路基板 200924134 2a，其中，該第一線路層3 6及該第一介電層3 〇上 亦可採取貼合該第二介電層3 7後，再形成該 屬層3 8 ; ^ (G) 形成複數個第二、三開口I?:如第8圖 所示，以雷射鑽孔之方式分別於該第二金屬層3 2與 該第一介電層30上形成複數個第二開口39，以顯 露其下之第一線路層3 6之第一面3 6a，以及於該第 三金屬層3 8與該第二介電層3 7上形成複數個第乂三 開口 4 0，以顯露該第一線路層3 6之第二面3 6b， 2中，該複數個第二、三開口 3 9、4 〇係先做開銅 窗後再經由雷射鑽孔、亦或係直接以雷射鑽孔之方式 形成； (H) 無電電鍍或電鍍第四、五金屬層1 8 :如 第9圖所示，以無電電鍍或電鍍之方式分別於複數個 第二開口中及該第二金屬層3 2上形成一第四金屬層 4 1，以及於複數個第三開口中及該第三金屬層3 8 上形成一第五金屬層42，其中，該第四金屬層41 及該第五金屬層4 2係做為與該第一線路層3 6之電 性連接用，且層與層之間之連接係由電鍍之複數個第 一、二雷射盲孔48、50所導通； (I )貼合第三、四阻層1 9 :如第1 〇圖所示， 分別於該第四金屬層4 1上貼合一第三阻層4 3，以 及於該第五金屬層42上貼合一第四阻層44; 10 200924134 (J)形成複數個第四、五開口 20 :如第1工 圖所示，以曝光及顯影之方式分別在該第三阻層 上形成複數個第四開σ 4 5，以顯露其下之第四金屬 層4 1 ’以及在該第四阻層4 4上形成複數個第五 口46，以頒露其下之第五金屬層42 ; 一 ，(κ)移除第二至五金屬層21 :如第12圖所 不，以蝕刻之方式分別移除該第四開口 4 5下方之第 二金屬層3 2與第四金屬層4 i，以及移除該第五開 口46下方之第三金屬層38與第五金屬層42; (L)疋成二層具圖案化線路及電性連接之三層 基板2 2 .如第1 3 g所示，分別移除該第三阻層， 使該第一、四金屬層形成一第二線路層4 7 ,以及移 除該第四阻層’使該第三、五金屬層形成—第三線路 層4 9，至此完成一三層具圖案化線路及電性連接之 三層基板2b，並可選擇直接進行步驟（M)或步 (N )； (Μ)進行置晶側與球側線路層製作2 3 :進行 一置晶側與球側線路層製作，其至少包含下列步驟： (ml)塗覆第-、二防焊層231 :如第工 4圖所示，分別於該第二線路層4 7上塗覆一層絕緣 保護用之第—防焊層5 1，以及於該第三線路層4 9 上亦塗覆一層絕緣保護用之第二防焊層5 2 ; (m2)形成複數個第六、七開口 232 :如 第1 5圖所不，以曝光及顯影之方式分別在該第一防 200924134 焊$ 5 1上形成複數個第六開口 5 3，以及在該第二 防焊層5 2 _L形成複數個第七開口 5 4。藉此以顯露 線路增層結構作為電性連接墊；以及 (m 3 )完成具完整圖案化之置晶側與球側線 ^層233 :如第Ug所示，分別於複數個第六開 3中形成第一阻障層ς 5，以及於複數個第七 =口 5 4中形成一第二阻障層56，以完成一具完整 案化之置晶側與球側線路層3，其中，該第一、二 阻障層5 5、5 6係可為錦金層。 (Ν)進订上'下兩層之線路增層結構製作2 4 : ^於·驟（L)之三層基板上直接進行上、下兩 層之線路增層結構製作，其至少包含下列步驟： (nl)貼合第三、四介電層241:如第！ 二別於該第二線路層47與顯露之第一介 於‘ 直接歷合或貼合一第三介電層5 7，以及 壓=二線路層4 9與顯露之第二介電層3 7上直接 σ或貼合一第四介電層5 8 ; 第18』：2)形成複數個第八、九開口242:如 所示，以雷射鑽孔之方式分別於該第三介電 :上形成複數個第八開口 5 g，以顯露其下之第 :第Γ層4 7 ’以及於該第四介電層5 8上形成複數 =開：60’以顯露其下之第三線路層4= 〆複數個第八、九開口 q Q β Π 後再經由雷射鑽孔、亦或#以^先做開銅窗 A诉直接以雷射鑽孔之方式形 12 200924134 成； (n3)形成第一、二晶種層243 :如 9圖所示，以無電電鍍或電鍍之方式分別於該第第^ 電層5 7與複數個第八開口 5 9表面形成一第一曰 * Sr 層6 1，以及於該第四介電層5 8與複數個第九p 口 60表面形成一第二晶種層62，其中，該第一 ^口 晶種層6 1、6 2係可為金屬銅層； 一 如第2 〇 第五阻層 六阻層6 (n4)貼合第五、六阻層244: 圖所示’分別於該第一晶種層6 i上貼合— β 3，以及於該第二晶種層6 2上貼合一第 4 ; (η5)形成複數個第十、十一開口. 如第2 1圖所示，以曝光及顯影之方式分別於該第五 阻層6 3上形成複數個第十開口 65，並顯露該第— 晶種層61，卩及於該第六阻層64上形成複數個第 十一開口 6 6，並顯露該第二晶種層6 2 ; (η6)無電電鍍或電鍍第六、七金屬層24 6 .如第2 2圖所示，以無電電鍍或電鍍之方式分别 於複數個第十開口 6 5，形成-第六金屬層6 7，以 及於複數個第十一開口 6 6中形成一第七金屬層6 8 ; (η7)移除第五、六阻層247:如第23 圖所示，移除該第五阻層及該第六阻層，以分別顯露 其下之第—、二晶種層6 1、Θ 2 ;以及 13 200924134 η 8)形成具圖案化線路及電性連接之五層 基板2 4 8 :如第2 4圖所示，以蝕刻之方式分別移 除該顯露之第一晶種層，並使該第三介電層5 7上之 第一 aa種層及第六金屬層形成一第四線路層69，以 及移除該顯露之第二晶種層，並使該第四介電層5 8 上之第二晶種層及第七金屬層形成一第五線路層7 0。於此，獲得上下各一層之線路增層結構，形成一 具圖案化線路及電性連接之五層基板4。 /請進-步請參閱『第2 5圖〜第2 7圖』所示， 係分別為本發明之置晶側與球側線路層（一B)剖面 不意圖、本發明之本發明之置晶側與球側線路層（二 B)剖面示意圖及本發明之置晶側與球側： B )剖面示意圖。如圖所示，本發明亦可在此五^ 構上繼續增加線路增層結構，以形成具 曰: 之封裝基板；亦或可直接進行該步驟（Μ)=Γ丨 與球側線路層製作，如第25〜27圖所示彳二 該第四線路層泠豫 a 刀另J於 T、iR 覆—層絕緣㈣用之第三防焊 曰7 1，以及於該第五線路層7 〇上亦 保護用之第四防焊層7 2 ;然後 /、、、邑緣200924134 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a single-layer diagram of a double-dielectric layer cut of a type of layer-added wiring board::: Its: square finish:: half-layer The structure of the package substrate [Prior Art] In the fabrication of a general multi-layer package substrate, the system is started from the -core substrate, through the iron hole, the money metal, the plug hole: = the upper line = for the other way, complete a double-sided The inner core plate of the structure is then completed via a line-addition process - multiple (four) substrates. As shown in Fig. 28, it is not intended to be a cross-section of a nucleated layer package substrate. First, a core substrate 8 is prepared, wherein the core substrate 8 is composed of a core layer 810 having a predetermined thickness and a circuit layer 8 〇2 formed on the surface of the core layer 810, and the core A plurality of electrical ore vias 803 are formed in the layer 810 to connect the circuit layer 8 〇2 on the surface of the core layer 810. Next, as shown in Figs. 29 to 32, a line build-up process is performed on the core substrate 80. First, a first dielectric layer 81 is formed on the surface of the core substrate 80, and a plurality of first openings 8 2 are formed on the surface of the first dielectric layer 81 to expose the circuit layer 8 〇 2 ' Forming a seed layer 83 on the exposed surface of the first dielectric layer 8 1 by electroless plating or electroplating, and forming a patterned resist layer 84 on the seed layer 200924134 8 3 , and patterning resistance thereof a plurality of second openings 85 are formed in the layer 84 to expose a portion of the seed layer 8 3 to form a patterned line; then, a first patterning is formed in the second opening 85 by means of electricity money. The circuit layer 86 and the plurality of conductive vias 87 are electrically connected to the circuit layer 8 0 of the core substrate 80 through the plurality of conductive vias 8 7 through the plurality of conductive vias 8 7 Then, the patterned resist layer 84 is removed and etched, and a first line build-up structure 8a is formed after completion. Similarly, the method can form a second dielectric layer 88 and a second patterned layer of a second patterned layer 8 in the same manner on the outermost surface of the first line build-up structure 8a. 8b, forming a multi-layer package substrate in a step-by-layer manner. However, such a manufacturing method has disadvantages such as low wiring density, a large number of layers, and a complicated process. In addition, there is also a method of using a thick copper metal plate as a core material, after completing an inner core plate by means of money etching and plugging, and then forming a multi-layer package substrate through a line build-up process. As shown in Fig. 3 3 to Fig. 5, it is a schematic cross-sectional view of another core-package substrate. First, a core substrate 〇 is prepared, which is formed of a metal layer having a thickness of a thickness of four (ii) and a resin boring hole 9 〇1 and a hole and an electric hole 9 Q 2 to form a layer copper core substrate 9 After that, a first dielectric layer 9 is formed on the surface of the core substrate 9 by using the above-mentioned circuit, and a: a circuit layer 9 2 ' is formed by the above-mentioned circuit to form a first line build-up structure 9 a . The method is the same as the above method, and the primary line can be reused: 200924134 The layering method forms a second dielectric layer 913 and a second patterned circuit layer on the outermost surface of the first line build-up structure 9a. Thus, a second line build-up structure 9b is formed to form a multi-layer package substrate in a step-by-layer manner. However, such a manufacturing method is not only difficult to fabricate the copper core substrate, but also has the disadvantages of low wiring density and complicated process, as in the above method. Therefore, the general practitioner cannot meet the needs of the user in actual use. SUMMARY OF THE INVENTION The main object of the present invention is to complete a semiconductor multilayer package substrate structure, which can effectively improve the bending problem of the ultra-thin core substrate plate and simplify the fabrication process of the conventional build-up circuit board. The secondary object of the present invention is to form a single-layer multi-layer package substrate according to actual needs, and to effectively reduce the thickness of the finished board and reduce the manufacturing cost. In order to achieve the above object, the present invention is a method for fabricating a layered wiring board. First, a single layer line is formed by optical lithography and etching, thereby making an electrical connection pad as a layered structure, and then Forming a three-layer structure circuit board on the contact surface thereof, and further, the upper and lower layers of the three-layer structure circuit board are respectively used as the electrical connection pads of the build-up structure, or The complete circuit of the crystal side and the ball side, and the manner of connecting the crystallizing side, the ball side and the middle layer are connected by a plurality of plating blind holes or buried holes, thereby completing a coreless layer multi-layer package substrate. 200924134 [Embodiment] Please refer to FIG. 1 to FIG. 24, which are schematic diagrams of the manufacturing process of the present invention, a schematic cross-sectional view of the double-sided substrate of the present invention, and three layers of the present invention with patterning and electrical connection. Schematic diagram of a substrate (a), a schematic diagram of a three-layer substrate (2) having a patterned and electrically connected structure according to the present invention, a schematic view of a three-layer substrate (3) having a patterned and electrically connected structure according to the present invention, and a patterning of the present invention And a three-layer substrate (four) schematic view of the electrical connection, a three-layer substrate with a patterned and electrically connected structure according to the present invention, and a three-layer substrate (six) profile of the present invention and patterned and electrically connected Schematic, three-layer substrate with pattern and electrical connection of Keming (7) Scratch surface, three-layer substrate with patterned and electrically connected invention (8) 丨 示 、 、 、 Three-layer substrate (9), schematic cross-sectional view, three-layer substrate (10) schematic diagram of the present invention with patterned and electrically connected, and three-layer substrate with patterned and electrically connected according to the present invention (Eleven a schematic cross-sectional view, a schematic view of the crystallographic side and the _ circuit layer (-A) of the present invention, a crystallographic side and a ball side of the present invention, a schematic diagram of a cross-section of the road layer (IIA), a crystallographic side and a ball side of the present invention, The schematic diagram of the road layer (-A) is a cross-sectional view of the two-layer line-adding structure (1) above and below the present invention, and two layers of the upper layer of the present invention, 丨 π ^ e , and mouth (1).彳 不 、 、 、 、 、 « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « Schematic diagram of cross-section, the upper two-layer circuit of the present invention 200924134; cross-sectional schematic view, the schematic diagram of the two layers of the upper and lower layers of the present invention: ": Lt and the upper and lower layers of the present invention" (8). * A method for fabricating a layered wiring board, which comprises at least the following:: - a package mr substrate 11: as shown in Fig. 2, a first dielectric layer 30, a - metal layer 3 1 and a first The double-sided substrate 1 of the metal layer 3 2; (B) the first and second resist layers 12 are bonded: as shown in FIG. 3, a first one is attached to the first metal layer 3 1 different from the double-sided substrate The resist layer 3 3 and the second metal layer 32 of the double-sided substrate are attached with a second resist layer 34 in a & = cover; ' (C ) forms a plurality of first openings 13: as shown in FIG. 4 a plurality of first openings 35 are formed on the first resist layer 33 by exposure and development to expose the first metal layer 3 underneath; (D) shifting First metal layer 14 · As shown in FIG. 5, the first metal layer 3 (E ) under the first opening 35 is removed by etching to form the first circuit layer 15 : as shown in FIG. 6 Removing the first resist layer and the second resist layer to form the first metal layer - the first circuit layer 3 6 having a single-sided line electrical connection pad; (F) forming the circuit substrate 16 of the two-layer structure As shown in FIG. 7, a second dielectric layer 37 and a third portion which are identical to the first dielectric layer 30 are directly bonded to the first circuit layer 36 and the first dielectric layer 3 The metal layer 3 8 is formed to form a three-layered circuit substrate 200924134 2a, wherein the first circuit layer 36 and the first dielectric layer 3 can also be attached to the second dielectric layer 3 7 And forming the genus layer 3 8 ; ^ (G) forming a plurality of second and third openings I?: as shown in Fig. 8, respectively, in the manner of laser drilling, the second metal layer 3 2 and the first A plurality of second openings 39 are formed on a dielectric layer 30 to expose a first surface 36a of the first circuit layer 36, and the third metal layer 38 and the second dielectric layer 3 7 Forming a plurality of third open 40, in order to reveal the second surface 3 6b, 2 of the first circuit layer 36, the plurality of second and third openings 3 9 and 4 are first opened by a copper window and then drilled through a laser. Or directly formed by laser drilling; (H) Electroless plating or electroplating of the fourth and fifth metal layers 18: as shown in Fig. 9, respectively, in electroless plating or electroplating in a plurality of second openings And forming a fourth metal layer 411 on the second metal layer 3 2 and forming a fifth metal layer 42 in the plurality of third openings and the third metal layer 38, wherein the fourth metal layer 41 and the fifth metal layer 42 are used for electrical connection with the first circuit layer 36, and the connection between the layers is performed by a plurality of first and second laser blind holes 48. 50 is conductive; (I) bonding the third and fourth resist layers 19: as shown in FIG. 1 , a third resist layer 4 3 is attached to the fourth metal layer 4 1 , and A fifth resist layer 44 is adhered to the five metal layer 42; 10 200924134 (J) forming a plurality of fourth and fifth openings 20: as shown in the first drawing, respectively, in the third resistive layer by exposure and developmentForming a plurality of fourth openings σ 4 5 to expose the fourth metal layer 4 1 ′ and forming a plurality of fifth openings 46 on the fourth resist layer 4 4 to expose the fifth metal layer underneath 42; one, (κ) removing the second to fifth metal layers 21: as shown in FIG. 12, removing the second metal layer 3 2 and the fourth metal layer under the fourth opening 45, respectively, by etching 4 i, and removing the third metal layer 38 and the fifth metal layer 42 under the fifth opening 46; (L) forming a two-layer patterned circuit and electrically connecting the three-layer substrate 2 2 . As shown in FIG. 3 g, the third resist layer is removed, the first and fourth metal layers are formed into a second circuit layer 47, and the fourth resist layer is removed to form the third and fifth metal layers. The third circuit layer 4, 9 has completed a three-layer patterned substrate and electrically connected three-layer substrate 2b, and can directly perform step (M) or step (N); (Μ) for the crystallizing side and the ball Side circuit layer fabrication 2 3: performing a crystal side and ball side circuit layer fabrication, which comprises at least the following steps: (ml) coating the first and second solder resist layers 231: as shown in Fig. 4, respectively The second circuit layer 47 is coated with a first solder mask layer 5 for insulation protection and a second solder resist layer 5 2 for insulating protection is also applied to the third circuit layer 49; (m2) Forming a plurality of sixth and seventh openings 232: as shown in FIG. 15 , forming a plurality of sixth openings 5 3 on the first anti-200924134 welding $ 5 1 by exposure and development, respectively, and in the second The solder resist layer 5 2 —L forms a plurality of seventh openings 5 4 . Thereby, the exposed layer build-up structure is used as the electrical connection pad; and (m 3 ) the completed patterned crystallized side and the ball side line layer 233 are formed as shown in the Ug, respectively, in the plurality of sixth openings 3 Forming a first barrier layer ς 5, and forming a second barrier layer 56 in the plurality of seventh=ports 5 4 to complete a completely planarized side and ball side wiring layer 3, wherein The first and second barrier layers 5 5 and 5 6 may be a gold layer. (Ν) ordering the second layer of the line build-up structure 2 4: ^ on the three-layer substrate of the (L) directly on the upper and lower layers of the line build-up structure, which at least includes the following steps : (nl) Fit the third and fourth dielectric layers 241: as in the first! Secondly, the second circuit layer 47 and the exposed first are between 'directly contacting or bonding a third dielectric layer 57, and the voltage=two circuit layer 49 and the exposed second dielectric layer 3 7 Directly σ or conforming to a fourth dielectric layer 5 8 ; 18′′: 2) forming a plurality of eighth and nine openings 242: as shown, respectively, in the manner of laser drilling to the third dielectric: Forming a plurality of eighth openings 5g thereon to expose the second: the second layer 4 7 ' and forming a complex number on the fourth dielectric layer 58 = 60: to reveal the third circuit layer below 4= 〆Multiple eighth and ninth openings q Q β Π and then through laser drilling, or # to open the copper window A first to directly drill the way of laser drilling 12 200924134 into; (n3) Forming the first and second seed layers 243: forming a first 曰* Sr layer on the surface of the first electrical layer 57 and the plurality of eighth openings 59 by electroless plating or electroplating, as shown in FIG. And forming a second seed layer 62 on the surface of the fourth dielectric layer 58 and the plurality of ninth p ports 60, wherein the first seed layer 6 1 , 6 2 may be metal Copper layer; as in the second The resistive layer six resistive layer 6 (n4) is bonded to the fifth and sixth resistive layers 244: as shown in the figure, 'the respective first seed layer 6 i is bonded to -β 3 , and the second seed layer 6 2 Bonding a fourth; (η5) forming a plurality of tenth and eleventh openings. As shown in FIG. 2, a plurality of tenth openings are formed on the fifth resist layer 63 by exposure and development, respectively. 65, and revealing the first seed layer 61, forming a plurality of eleventh openings 6 6 on the sixth resist layer 64 and revealing the second seed layer 6 2; (η6) electroless plating or electroplating The sixth and seventh metal layers 24 6 . As shown in FIG. 2 , the sixth metal layer 6 7 is formed in the plurality of tenth openings 65 by electroless plating or electroplating, respectively, and in the plurality of eleventh Forming a seventh metal layer 6 8 in the opening 66; (n7) removing the fifth and sixth resist layers 247: as shown in FIG. 23, removing the fifth resist layer and the sixth resist layer to respectively reveal The second, second seed layer 6 1 , Θ 2 ; and 13 200924134 η 8) form a patterned circuit and electrically connected five-layer substrate 2 4 8 : as shown in Figure 24, to etch Way to remove the reveal separately a first seed layer, and the first aa seed layer and the sixth metal layer on the third dielectric layer 57 form a fourth circuit layer 69, and the exposed second seed layer is removed, and The second seed layer and the seventh metal layer on the fourth dielectric layer 58 form a fifth circuit layer 70. Here, the line build-up structure of each of the upper and lower layers is obtained, and a five-layer substrate 4 having a patterned line and an electrical connection is formed. Please refer to the "25th to 7th" diagrams, which are the cross-sections of the crystal side and the ball side circuit layer (B) of the present invention, respectively, and the present invention is not intended. Schematic cross-section of the crystal side and ball side circuit layer (B) and the crystal side and the ball side of the present invention: B) Schematic diagram of the cross section. As shown in the figure, the present invention can also continue to add a line build-up structure to form a package substrate having the same: or directly perform the step (Μ)=Γ丨 and ball-side circuit layer fabrication. As shown in Figures 25 to 27, the fourth circuit layer is a 刀 a 另 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 第三 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及The fourth solder mask 7 2 is also protected; then /, ,,
T別在該第三防焊層7 1上形成複數個第十方J 及在，防焊層”上形成複數二二 口 7 4 ’以顯露線路增層結構作 -開 分別於複數個第十二開口73十形成-第二^接著 5，以及於複數個第十二 一阻障層7 開口74中形成-第四阻障 14 200924134 層7 6。至此，完成一無核層多層封裝基板5。 其中’該第一〜四介電層30、37、57、5 8 係可為 ABF ( Ajinomoto Build-up Film)、笨環丁稀 (Benz〇CyCl〇_buthene，BCB )、雙馬來亞醯胺_三氮雜 笨樹脂（Bismaleimide Triazine，BT)、環氧樹脂板 (FR4、FR5 )、聚酿亞胺（p〇lyimide，P!)、聚四氟乙 烯（P〇ly(tetra-fl〇r〇ethylene)，PTFE)或環氧樹脂及玻 璃纖維所組成之一者；該第一〜六阻層3 3、3 4、 4 3、4 4、6 3、Θ 4亦可以印刷或旋轉塗佈之方 式為之乾膜或溼膜之高感光性光阻；該第一〜七金屬 層31、32、38、41、42、67、68係可 為銅或其它等效金屬；該第一〜五金屬層3 i、3 2、 38、41、42及該第一、二晶種層61、62之 移除方法係可為蝕刻或其它等效方法；該第一〜六阻 二33 34、43、44、63、Θ4之移除方法 係可為剝離或其它等效方法。 ，當本發明於運用時，係先以光學微影及蝕刻之方 式製作單層線路，藉此以做為增層結構之電性連接 墊“之後再於其接墊面以壓合之方式形成一三層結構 電路板，並且可進一步以該三層結構電路板之上、 3*層分別做為增層結構之電性連接塾，亦或係作為置 Ba側與球側之完整線路，1^在連接其置晶側、球侧及 中間各層之方式則係以複數個電鍍盲孔或埋孔所導 通藉此’使用本發明高密度之增層線路板製作方法， 15 200924134 係可完成-半㈣多層封裝基板結構，可有效改 f核層基板板彎_題及簡化傳統增層線路板之^作 流程，係一個可依實際需求形成單數多層之封裝義 板，進而可有效達到降低成品板厚度及減少製作 之目的。 综上所述，本發明係一種增層線路板之製作方 法，可有效改善習用之種種缺點，係可完成一半導體 夕層封裝基板結構，包括雙介電層支撐之單層圖案化 線路層及已完成圖案化線路製程之置晶側與球側線路 層，可有效改善超薄核層基板板彎翹問題及簡化傳統 增層線路板之製作流程，係一個可依實際需求形成單 數多層之封裝基板，並可有效達到降低成品板厚度及 減J製作成本之目的，進而使本發明之産生能更進 步、更實用、更符合使用者之所須，確已符合發明專 利申晴之要件，爰依法提出專利申請。 准以上所述者’僅為本發明之較佳實施例而已， 當不能以此限定本發明實施之範圍；故，凡依本發明 申請專利範圍及發明說明書内容所作之簡單的等效變 化與修飾，皆應仍屬本發明專利涵蓋之範圍内。 16 200924134 【圖式簡單說明】 第1圖’係本發明之製作流程示意圖。 第2圖，係本發明之雙面基板剖面示意圖。 第3圖，係本發明具圖案化及電性連接之三層基板 (")剖面不意圖。 第4圖，係本發明具圖案化及電性連接之三層基板 (二） 剖面示意圖。 第5圖，係本發明具圖案化及電性連接之三層基板 (三） 剖面示意圖。 第6圖，係本發明具圖案化及電性連接之三層基板 (四） 剖面示意圖。 第7圖，係本發明具圖案化及電性連接之三層基板 (五） 剖面示意圖。 第8圖，係本發明具圖案化及電性連接之三層基板 (六） 剖面示意圖。 第9圖，係本發明具圖案化及電性連接之三層基板 (七） 剖面示意圖。 第1 0圖，係本發明具圖案化及電性連接之三層基板 (八） 剖面示意圖。 第1 1圖，係本發明具圖案化及電性連接之三層基板 (九） 剖面示意圖。 17 200924134 第1 2圖，係本發明具圖案化及電性連接之三層基板 (十）剖面示意圖。 第1 3圖，係本發明具圖案化及電性連接之三層基板 (Η—)剖面示意圖。 第1 4圖，係本發明之置晶側與球側線路層（一 A) 剖面示意圖。 第1 5圖，係本發明之置晶側與球側線路層（二A) 剖面示意圖。 第1 6圖，係本發明之置晶側與球側線路層（三A) 剖面示意圖。 第1 7圖，係本發明之上下兩層線路增層結構（一） 剖面示意圖。 第1 8圖，係本發明之上下兩層線路增層結構（二） 剖面示意圖。 第1 9圖，係本發明之上下兩層線路增層結構（三） 剖面示意圖。 第2 0圖，係本發明之上下兩層線路增層結構（四） 剖面示意圖。 第2 1圖，係本發明之上下兩層線路增層結構（五） 剖面示意圖。 第2 2圖，係本發明之上下兩層線路增層結構（六） 剖面示意圖。 18 200924134 第2 3圖，係本發明之上下兩層線路增層結構（七） 剖面示意圖。 第2 4圖，係本發明之上下兩層線路增層結構（八） 剖面示意圖。 第2 5圖，係本發明之置晶侧與球侧線路層（一 剖面示意圖。 第2 6圖，係本發明之置晶側與球側線路層（二b ) 剖面示意圖。 第2 7圖，係本發明之置晶側與球側線路層（三 剖面不意圖。 第2 8圖’係習用有核層封裝基板之剖面示意圖。 第2 9圖，係習用之實施線路增層（一）剖面示意圖 第30圖，係習用之實施線路增層（二）剖面示意圖 第31圖，係習用之實施線路增層（三）剖面示意圖 第32圖’係習用之實施線路增層（四）剖面示意圖 第33圖，係另一習用有核層封裝基板之剖面示意圖 第34圖’係習用之第'線路增層結構剖面示意圖£ 第35圖，係習用之第二路增層結構音 【主要元件符號說明】 ί @ ° (本發明部分） 步驟（A)〜（N) 11〜24 19 200924134 步驟（ml)〜（m3) 231〜233 步驟（nl)〜（n8) 241〜248 雙面基板1 三層基板2a、2b 置晶側與球側線路層3 五層基板4 無核層多層封裝基板5 第一介電層3 0 第一金屬層3 1 第二金屬層3 2 第一、二阻層33、34 第一開口 3 5 第一線路層3 6 第一、二面 3 6a、36b 第二介電層3 7 第三金屬層3 8 第二、三開口 39、40 第四、五金屬層4 1、4 2 第三、四阻層43、44 第四、五開口45、46 20 200924134 第二、三線路層47、49 第一、二電鍍盲孔48、50 第一、二防焊層51、52 第六、七開口 53、54 第一、二阻障層55、56 第三、四介電層57、58 第八、九開口 5 9、6 0 第一、二晶種層6 1、6 2 第五、六阻層6 3、64 第十、十一開口 6 5、6 6 第六、七金屬層67、68 第四、五線路層6 9、70 第三、四防焊層71、72 第十二、十三開口73、74 第三、四阻障層7 5、7 6 (習用部分） 第一、二線路增層結構8 a、8 b 核心基板8 0 芯層8 0 1 線路層8 0 2 21 200924134 電鍍導通孔8 0 3 第一、二介電層8 1、8 8 第一、二開口 82、85 晶種層8 3 圖案化阻層8 4 第一、二圖案化線路層8 6、8 9 導電盲孔8 7 第一、二線路增層結構9 a、9 b 核心基板9 0 樹脂塞孔9 0 1 電鍍通孔9 0 2 第一、二介電層9 1、9 3 第一、二圖案化線路層9 2、9 4 22T is formed on the third solder resist layer 7 1 and a plurality of tenth squares J and a plurality of second and second ports 7 4 ' are formed on the solder resist layer" to reveal the line build-up structure - the plurality of The twelve openings 73 are formed - the second ^ 5, and the fourth block 14 is formed in the opening 74 of the twelfth barrier layer 7 - the fourth barrier 14 200924134 layer 7 6 . Thus, a coreless multilayer package substrate is completed 5. The 'the first to fourth dielectric layers 30, 37, 57, 58 can be ABF (Ajinomoto Build-up Film), Benz〇CyCl〇_buthene (BCB), double Malay Bismaleimide Triazine (BT), epoxy resin board (FR4, FR5), polystyrene (P!), polytetrafluoroethylene (P〇ly (tetra-) Fl〇r〇ethylene), PTFE) or one of epoxy resin and glass fiber; the first to sixth resist layers 3 3, 3 4, 4 3, 4 4, 6 3, Θ 4 can also be printed or The spin coating is a high-sensitivity photoresist of a dry film or a wet film; the first to seventh metal layers 31, 32, 38, 41, 42, 67, 68 may be copper or other equivalent metal; First to fifth metal The method of removing the layers 3 i, 3 2, 38, 41, 42 and the first and second seed layers 61, 62 may be etching or other equivalent method; the first to sixth resistance two 33 34, 43, 44, 63, Θ4 removal method can be stripping or other equivalent method. When the invention is applied, a single layer line is first formed by optical lithography and etching, thereby using as a layered structure. The electrical connection pad is then formed into a three-layer structure circuit board by pressing on the surface of the pad, and can further be used as a build-up structure on the three-layer structure circuit board and the 3* layer respectively. The connection is either a complete line connecting the side of the Ba and the side of the ball. The way to connect the side of the crystal, the side of the ball and the middle of the layer is controlled by a plurality of plated blind holes or buried holes. Using the high-density layer-added circuit board manufacturing method of the present invention, 15 200924134 can complete the semi-four-layer multi-layer package substrate structure, which can effectively change the f-core substrate board bending and simplify the process of the conventional layer-added circuit board. A package board that can form a single multi-layer according to actual needs, thereby effectively reducing Product and the purpose of reducing the plate thickness of the production. In summary, the present invention is a method for fabricating a build-up circuit board, which can effectively improve various disadvantages of the conventional use, and can complete a semiconductor layer package substrate structure, including a single-layer patterned circuit layer supported by a double dielectric layer and The crystallized side and the ball side circuit layer of the patterned circuit process have been completed, which can effectively improve the bending problem of the ultra-thin core substrate board and simplify the manufacturing process of the conventional layered circuit board, and is a package capable of forming a single multi-layer according to actual needs. The substrate can effectively achieve the purpose of reducing the thickness of the finished board and reducing the manufacturing cost of the J, thereby making the invention more progressive, more practical and more suitable for the user, and indeed meets the requirements of the invention patent Shen Qing, File a patent application. The above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto; therefore, the simple equivalent changes and modifications made in accordance with the scope of the present invention and the contents of the description of the invention All should remain within the scope of the invention patent. 16 200924134 [Simplified description of the drawings] Fig. 1 is a schematic view showing the production process of the present invention. Fig. 2 is a schematic cross-sectional view showing a double-sided substrate of the present invention. Fig. 3 is a cross-sectional view of a three-layer substrate (") having a patterned and electrically connected structure according to the present invention. Fig. 4 is a schematic cross-sectional view showing a three-layer substrate (2) having a pattern and an electrical connection according to the present invention. Fig. 5 is a schematic cross-sectional view showing a three-layer substrate (3) having a pattern and an electrical connection according to the present invention. Figure 6 is a schematic cross-sectional view showing a three-layer substrate (4) having a pattern and an electrical connection according to the present invention. Figure 7 is a schematic cross-sectional view of a three-layer substrate (5) having a patterned and electrically connected structure according to the present invention. Figure 8 is a schematic cross-sectional view of a three-layer substrate (6) having a patterned and electrically connected structure according to the present invention. Figure 9 is a schematic cross-sectional view of a three-layer substrate (7) having a patterned and electrically connected structure according to the present invention. Fig. 10 is a schematic cross-sectional view showing a three-layer substrate (8) having a pattern and an electrical connection according to the present invention. Fig. 1 is a schematic cross-sectional view showing a three-layer substrate (9) having a pattern and an electrical connection according to the present invention. 17 200924134 Figure 12 is a schematic cross-sectional view of a three-layer substrate (10) having a patterned and electrically connected structure according to the present invention. Figure 13 is a schematic cross-sectional view of a three-layer substrate (Η-) having a patterned and electrically connected structure according to the present invention. Fig. 14 is a schematic cross-sectional view showing the crystallographic side and the ball side wiring layer (A) of the present invention. Fig. 15 is a schematic cross-sectional view showing the crystallographic side and the ball side wiring layer (IIA) of the present invention. Fig. 16 is a schematic cross-sectional view showing the crystallographic side and the ball side wiring layer (3A) of the present invention. Figure 17 is a schematic cross-sectional view of the two-layer line build-up structure (1) above and below the present invention. Figure 18 is a schematic cross-sectional view of the two-layer line build-up structure (2) above and below the present invention. Figure 19 is a schematic cross-sectional view of the three-layer line build-up structure (3) above and below the present invention. Figure 20 is a schematic cross-sectional view of the two-layer line build-up structure (4) above and below the present invention. Figure 21 is a schematic cross-sectional view of the two-layer line build-up structure (5) above and below the present invention. Figure 2 is a schematic cross-sectional view of the two-layer line build-up structure (6) above and below the present invention. 18 200924134 Figure 2 3 is a schematic cross-sectional view of the two-layer line build-up structure (7) above and below the present invention. Figure 24 is a schematic cross-sectional view of the two-layer line build-up structure (8) above and below the present invention. Figure 25 is a schematic view of a crystal side and a ball side circuit layer of the present invention (a cross-sectional view. Fig. 26 is a schematic cross-sectional view of the crystal side and the ball side circuit layer (2b) of the present invention. The crystal side and the ball side circuit layer of the present invention (the three sections are not intended. Fig. 28 is a schematic cross-sectional view of a conventional nuclear layer package substrate. Fig. 29 is a conventional implementation of line buildup (1) Figure 30 of the cross-section diagram, which is the schematic diagram of the cross-section of the circuit (2), which is the schematic diagram of the conventional application of the line-enhanced (2) cross-section (3) Schematic diagram of the cross-section of the line (Fig. 32) Figure 33 is a schematic cross-sectional view of another conventional nucleated layer package substrate. Figure 34 is a schematic diagram of a section of the 'additional line' of the conventional structure. Figure 35 is a second-layer structure of the structure. Description] ί @ ° (part of the invention) Step (A) ~ (N) 11~24 19 200924134 Step (ml) ~ (m3) 231~233 Step (nl) ~ (n8) 241~248 Double-sided substrate 1 III Layer substrate 2a, 2b crystal side and ball side circuit layer 3 five-layer substrate 4 coreless layer Layer package substrate 5 first dielectric layer 30 first metal layer 3 1 second metal layer 3 2 first, second resistance layer 33, 34 first opening 3 5 first circuit layer 3 6 first, two sides 3 6a 36b second dielectric layer 3 7 third metal layer 3 8 second and third openings 39, 40 fourth and fifth metal layers 4 1 , 4 2 third and fourth resistive layers 43 and 44 fourth and fifth openings 45, 46 20 200924134 Second and third circuit layers 47, 49 First and second plating blind holes 48, 50 First and second solder masks 51, 52 Sixth, seven openings 53, 54 First and second barrier layers 55, 56 Third, fourth dielectric layer 57, 58 eighth, nine openings 5 9, 6 0 first, two seed layers 6 1 , 6 2 fifth, six resistive layers 6 3, 64 tenth, eleven openings 6 5 6 6 sixth and seventh metal layers 67, 68 fourth and fifth circuit layers 6 9 and 70 third and fourth solder resist layers 71, 72 twelfth and thirteenth openings 73, 74 third and fourth barrier layers 7 5, 7 6 (customized part) First and second line build-up structure 8 a, 8 b core substrate 8 0 core layer 8 0 1 circuit layer 8 0 2 21 200924134 electroplated via 8 0 3 first and second dielectric layer 8 1 , 8 8 first and second openings 82, 85 seed layer 8 3 patterned resist layer 8 4 2, patterned circuit layer 8 6 , 8 9 conductive blind hole 8 7 first and second line build-up structure 9 a, 9 b core substrate 9 0 resin plug hole 9 0 1 plated through hole 9 0 2 first, second media Electrical layer 9 1 , 9 3 first and second patterned circuit layers 9 2, 9 4 22