CN101527266B - Manufacture method for layer-adding circuit board - Google Patents
Manufacture method for layer-adding circuit board Download PDFInfo
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- CN101527266B CN101527266B CN2008100835369A CN200810083536A CN101527266B CN 101527266 B CN101527266 B CN 101527266B CN 2008100835369 A CN2008100835369 A CN 2008100835369A CN 200810083536 A CN200810083536 A CN 200810083536A CN 101527266 B CN101527266 B CN 101527266B
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Abstract
The invention discloses a manufacture method for a layer-adding circuit board, which comprises the following steps that: a single layer circuit is manufactured by optical lithography and etching method and is taken as an electrically connected pad of a layer-adding structure, and a circuit board with a three-layer structure is formed on the connected pad surface in a pressing mode; a second layer-adding circuit is formed on the first layer-adding circuit structure, and a metal layer with the prior non-patterned circuit is formed into a third layer-adding circuit so as to form a four-layer substrate with a patterned circuit and electric connection; and the upper layer and the lower layer of the four-layer substrate are further taken as the electrically connected pads of the layer-adding structure respectively, or taken as a complete circuit between the wafer placing side and the ball side. Therefore, the method can effectively improve the problem of bow and twist of an ultrathin seed-layer substrate, simplify the manufacture flows of the conventional layer-adding circuit boards, and effectively reduce the thickness and the manufacturing cost of production boards.
Description
Technical field:
The present invention relates to a kind of manufacture method of build-up circuit board, refer to that especially a kind of single layer pattern line construction that supports with two dielectric layers is the manufacture method that the build-up circuit board of semiconductor layer multilayer packaging substrate structure is accomplished on the basis.
Background technology:
In the making of general layer multilayer packaging substrate; Its production method is normally begun by a core substrate; Through modes such as boring, plated metal, consent and two-sided circuit making, accomplish the inner layer core plate of a two-sided structure, increase a layer processing procedure via a circuit more afterwards and accomplish a layer multilayer packaging substrate.Shown in figure 32, it is one the generalized section of stratum nucleare base plate for packaging to be arranged.At first; Prepare a core substrate 81, wherein, this core substrate 81 is made up of the sandwich layer 811 of a tool predetermined thickness and 812 of line layers being formed at these sandwich layer 811 surfaces; And be formed with several in this sandwich layer 811 and electroplate via 813, can use the line layer 812 that connects these sandwich layer 811 surfaces.
Then as Figure 33～and shown in Figure 36, these core substrate 81 enforcement circuits are increased a layer processing procedure.At first, be to form one first dielectric layers 82 in this core substrate 81 surfaces, and this first dielectric layer, 82 surfaces and be formed with several first openings 83, to expose this line layer 812; Afterwards; Form a crystal seed layer 84 with modes such as electroless-plating and plating in the surface that this first dielectric layer 82 exposes; And on this crystal seed layer 84, form patterning resistance layer 85, and in its patterning resistance layer 85 and several second openings 86 are arranged, to expose the crystal seed layer 84 that desire partly forms patterned circuit; Then; Utilize plating mode in this second opening 86, to form one first patterned line layer 87 and several conductive blind holes 88; And make its first patterned line layer 87 be able to see through these several conductive blind holes 88 to do with the line layer 812 of this core substrate 81 and electrically conduct; And then remove this patterning resistance layer 85 and etching, form one first circuit layer reinforced structure 8a after waiting to accomplish.Likewise; This method can be transported the second circuit layer reinforced structure 8b that forms one second dielectric layer 89 and one second patterned line layer 90 in a like fashion again in the outermost surface of this first circuit layer reinforced structure 8a, forms a layer multilayer packaging substrate progressively to increase a layer mode.Yet this kind manufacture method has that wiring density is low, the number of plies reaches shortcomings such as flow process complicacy more.
In addition, the method for thick copper metallic plate when core material of utilizing also arranged, can after accomplishing an inner layer core plate, increase layer processing procedure to accomplish a layer multilayer packaging substrate via a circuit again through modes such as etching and consents.Like Figure 37～shown in Figure 39, it has the generalized section of stratum nucleare base plate for packaging for another.At first, prepare a core substrate 91, the individual layer copper core substrate that this core substrate 91 utilizes etching and filling holes with resin 911 and modes such as boring and electroplating ventilating hole 912 to form for the metal level by a tool predetermined thickness; Afterwards, utilize above-mentioned circuit to increase a layer mode, form one first dielectric layer 92 and one first patterned line layer 93, constitute a tool first circuit layer reinforced structure 9a by this in these core substrate 91 surfaces.This method is also identical with said method; Can utilize a circuit to increase layer mode again and form one second dielectric layer 94 and one second patterned line layer 95 in the outermost surface of this first circuit layer reinforced structure 9a; Constitute a tool second circuit layer reinforced structure 9b by this, form a layer multilayer packaging substrate progressively to increase a layer mode.Yet this kind manufacture method not only its copper core substrate making is difficult for, and also identical with said method, has wiring density and hangs down shortcomings such as reaching the flow process complicacy.So it is required when reality is used generally can't to meet the user.
Summary of the invention:
Technical problem to be solved by this invention is: to the deficiency of above-mentioned prior art; A kind of manufacture method of build-up circuit board is provided; A kind of semiconductor layer multilayer packaging substrate structure of accomplishing can effectively be improved ultra-thin stratum nucleare substrate plate prying problem and simplify the making flow process of traditional build-up circuit board.
In order to solve the problems of the technologies described above, the technical scheme that the present invention adopted is: a kind of manufacture method of build-up circuit board, and this method comprises the following step at least:
(A) selection one comprises the double-sided substrate of one first dielectric layer, a first metal layer and one second metal level;
(B) respectively form first and second resistance layer on first and second metal level respectively at this double-sided substrate;
(C) on this first resistance layer, form several first openings, appear the first metal layer under it;
(D) remove the first metal layer of this first opening below;
(E) remove this first resistance layer and this second resistance layer, first line layer that formation one has as electric connection pad;
(F) on this first line layer and this first dielectric layer, form one second dielectric layer and one the 3rd metal level, form the circuit substrate of a three-decker;
(G) on the 3rd metal level and this second dielectric layer, form several second openings, appear first of first line layer under it;
(H) form one the 4th metal level in several second openings and on this first line layer and the 3rd metal level;
(I) respectively at respectively forming third and fourth resistance layer on the 4th, two metal levels;
(J) on the 3rd resistance layer, form several the 3rd openings, appear the 4th metal level under it;
(K) remove the 3rd metal level and the 4th metal level of the 3rd opening below;
(L) remove the 3rd resistance layer and the 4th resistance layer, make this third and fourth metal level formation one tertiary circuit layer of patterning, so far accomplish three laminar substrates of a two-layer tool patterned circuit and electric connection;
(M) pressing 1 the 3rd dielectric layer and one the 5th metal level again on this tertiary circuit layer and this second dielectric layer;
(N) respectively at forming several the 4th openings on this second metal level and this first dielectric layer; Appear its second of first line layer of patterning down; And on the 5th metal level and the 3rd dielectric layer, form several the 5th openings, appear its following tertiary circuit layer of patterning;
(O) form one the 6th metal level on this second metal level respectively at reaching in several the 4th openings, and form one the 7th metal level in several the 5th openings and on the 5th metal level;
(P) respectively at one the 5th, the six resistance layers of respectively fitting on the 6th, seven metal levels;
(Q) upward form several the 6th openings respectively at the 5th resistance layer, appear the 6th metal level under it, and go up several minion mouths of formation, appear the 7th metal level under it in the 6th resistance layer;
(R) remove second metal level and the 6th metal level of the 6th opening below respectively, and the 5th metal level and the 7th metal level that remove this minion mouth below;
(S) remove the 5th resistance layer respectively, forming second line layer of patterning, and remove the 6th resistance layer, to form the 4th line layer of patterning.So far accomplish four laminar substrates of one or four layers of tool patterned circuit and electric connection, and select directly to carry out step (T) or step (U);
(T) carry out putting brilliant side and ball side line layer electric connection pad and make, it comprises the following step at least:
(t1), and on the 4th line layer and the 3rd dielectric layer, apply one second welding resisting layer respectively at coating one first welding resisting layer on this second line layer and this first dielectric layer;
(t2) on this first and second welding resisting layer, respectively form several the 8th, nine openings respectively, appear the circuit layer reinforced structure by this as electric connection pad; And
(t3) respectively at respectively forming first and second barrier layer in several the 8th, nine openings;
(U) carry out upper and lower two-layer circuit layer reinforced structure and make, it comprises the following step at least:
(u1) respectively at one the 4th dielectric layer of fitting on this second line layer and this first dielectric layer, and one the 5th dielectric layer of on the 4th line layer and the 3rd dielectric layer, fitting;
(u2) respectively at forming several the tenth openings on the 4th dielectric layer, appear second line layer under it, and on the 5th dielectric layer, form several the 11 openings, appear the 4th line layer under it;
(u3) form one first crystal seed layer respectively at the 4th dielectric layer and several the tenth open surfaces, and form one second crystal seed layer in the 5th dielectric layer and several the 11 open surfaces;
(u4) respectively at respectively forming one the 7th, eight resistance layers on this first and second crystal seed layer;
(u5) upward form several twelvemo mouths respectively at the 7th resistance layer, and appear this first crystal seed layer, and go up several the 13 openings of formation, and appear this second crystal seed layer in the 8th resistance layer;
(u6), and form one the 9th metal level on second crystal seed layer in several the 13 openings respectively at formation one the 8th metal level on first crystal seed layer in several twelvemo mouths;
(u7) remove the 7th, eight resistance layers, and appear first and second crystal seed layer under it respectively; And
(u8) remove first crystal seed layer that this appears respectively, and on the 4th dielectric layer, form one the 5th line layer, and remove second crystal seed layer that this appears, and on the 5th dielectric layer, form one the 6th line layer.
At first; On a two-sided substrate, make an individual layer circuit with photolithography and etching mode; By this with electric connection pad as layer reinforced structure; Form first build-up circuit in this individual layer circuit connection gasket with the pressing mode more afterwards, forming the circuit board of a tool three-layer metal structure, and wherein two series of strata have been accomplished patterned circuit and have been seen through several and electroplate blind holes and produce electric connection.Then; On this first build-up circuit structure, form second build-up circuit again; Make the metal level of former not patterned circuit form the 3rd build-up circuit simultaneously; Four laminar substrates that become a tool patterned circuit and electrically conduct, and can be further with the upper and lower layer of this four laminar substrate respectively as the electric connection pad of layer reinforced structure, also or be as putting the complete line of brilliant side and ball side; Connecting its mode of putting brilliant side, ball side and middle each layer then is to electroplate blind hole or the conducting of buried via hole institute with several, by this to accomplish a non-core layer multi-layer encapsulation substrate.
So, the present invention can effectively improve ultra-thin stratum nucleare substrate plate prying problem and simplify the making flow process of traditional build-up circuit board, can form the base plate for packaging of even numbers multilayer according to actual demand, and can effectively reduce the finished product plate thickness and reduce cost of manufacture.
Description of drawings:
Fig. 1 is a making schematic flow sheet of the present invention.
Fig. 2 is a double-sided substrate generalized section of the present invention.
Fig. 3 is a two-layer substrate generalized section one of the present invention.
Fig. 4 is a two-layer substrate generalized section two of the present invention.
Fig. 5 is a two-layer substrate generalized section three of the present invention.
Fig. 6 is a two-layer substrate generalized section four of the present invention.
Fig. 7 is three laminar substrate generalized sections one of the present invention.
Fig. 8 is three laminar substrate generalized sections two of the present invention.
Fig. 9 is three laminar substrate generalized sections three of the present invention.
Figure 10 is three laminar substrate generalized sections four of the present invention.
Figure 11 is three laminar substrate generalized sections five of the present invention.
Figure 12 is three laminar substrate generalized sections six of the present invention.
Figure 13 is three laminar substrate generalized sections seven of the present invention.
Figure 14 is four laminar substrate generalized sections one of the present invention.
Figure 15 is four laminar substrate generalized sections two of the present invention.
Figure 16 is four laminar substrate generalized sections three of the present invention.
Figure 17 is four laminar substrate generalized sections four of the present invention.
Figure 18 is four laminar substrate generalized sections five of the present invention.
Figure 19 is four laminar substrate generalized sections six of the present invention.
Figure 20 is four laminar substrate generalized sections seven of the present invention.
Figure 21 is brilliant side and the ball side line layer generalized section one of putting of the present invention.
Figure 22 is brilliant side and the ball side line layer generalized section two of putting of the present invention.
Figure 23 is that brilliant side and ball side line layer generalized section three are put in enforcement of the present invention.
Figure 24 is a two-layer circuit layer reinforced structure generalized section one up and down of the present invention.
Figure 25 is a two-layer circuit layer reinforced structure generalized section two up and down of the present invention.
Figure 26 is a two-layer circuit layer reinforced structure generalized section three up and down of the present invention.
Figure 27 is a two-layer circuit layer reinforced structure generalized section four up and down of the present invention.
Figure 28 is a two-layer circuit layer reinforced structure generalized section five up and down of the present invention.
Figure 29 is a two-layer circuit layer reinforced structure generalized section six up and down of the present invention.
Figure 30 is a two-layer circuit layer reinforced structure generalized section seven up and down of the present invention.
Figure 31 is a two-layer circuit layer reinforced structure generalized section eight up and down of the present invention.
Figure 32 is the generalized section of existing stratum nucleare base plate for packaging.
Figure 33 is that the existing circuit of implementing increases layer generalized section one.
Figure 34 is that the existing circuit of implementing increases layer generalized section two.
Figure 35 is that the existing circuit of implementing increases layer generalized section three.
Figure 36 is that the existing circuit of implementing increases layer generalized section four.
Figure 37 is the generalized section of another existing stratum nucleare base plate for packaging.
Figure 38 is the existing first circuit layer reinforced structure generalized section.
Figure 39 is existing the second road layer reinforced structure generalized section.
Label declaration:
Step (A)～(U) 10～30
Step (t1)～(t3) 291～293
Step (u1)～(u8) 301～308
Double-sided substrate 1 three laminar substrate 2a, 2b
3 four layers of non-core layer multi-layer encapsulation substrate 4 of four laminar substrates
Six laminar substrates, 5 first dielectric layers 31
First and second metal level 32,33 first and second resistance layers 34,35
First opening, 36 first line layers 37
First and second face 37a, 37b second dielectric layer 38
The 3rd metal level 39 second openings 40
The 4th metal level 41 first laser blind holes 46
Third and fourth resistance layer 42,43 the 3rd openings 44
The 5th metal level 48 fourth, fifth openings 49,50
Six, seven metal levels, 51,52 second and third laser blind holes 53,54
Five, six hinder layer 55,56 the 6th, minion mouth 57,58
The second, four line layers, 59,60 first and second welding resisting layers 61,62
Eight, nine openings, 63,64 first and second barrier layers 65,66
Fourth, fifth dielectric layer, 67,68 the tenth, 11 openings 69,70
First and second crystal seed layer 71,72 the 7th, eight resistance layers 73,74
Eight, nine metal levels, 77,78 the 12,13 openings 75,76
Five, six line layers 79,80
First and second circuit layer reinforced structure 8a, 8b
First and second dielectric layer 82,89 first and second openings 83,86
Conductive blind hole 88 core substrates 91
First and second patterned line layer 87,90
First and second circuit layer reinforced structure 9a, 9b
Filling holes with resin 911 electroplating ventilating holes 912
First and second dielectric layer 92,94
First and second patterned line layer 93,95
Embodiment:
See also Fig. 1～shown in Figure 31, be respectively four laminar substrate generalized sections seven of making schematic flow sheet of the present invention, double-sided substrate generalized section of the present invention, two-layer substrate generalized section of the present invention, two-layer substrate generalized section of the present invention two, two-layer substrate generalized section of the present invention three, two-layer substrate generalized section of the present invention four, three laminar substrate generalized sections one of the present invention, three laminar substrate generalized sections two of the present invention, three laminar substrate generalized sections three of the present invention, three laminar substrate generalized sections four of the present invention, three laminar substrate generalized sections five of the present invention, three laminar substrate generalized sections six of the present invention, three laminar substrate generalized sections seven of the present invention, four laminar substrate generalized sections one of the present invention, four laminar substrate generalized sections two of the present invention, four laminar substrate generalized sections three of the present invention, four laminar substrate generalized sections four of the present invention, four laminar substrate generalized sections five of the present invention, four laminar substrate generalized sections six of the present invention, tool patterning of the present invention and electric connection, brilliant side and ball side line layer generalized section one, brilliant side and ball side line layer generalized section two, brilliant side and ball side line layer generalized section three, up and down two-layer circuit layer reinforced structure generalized section of the present invention, up and down two-layer circuit layer reinforced structure generalized section of the present invention two, up and down two-layer circuit layer reinforced structure generalized section of the present invention three, up and down two-layer circuit layer reinforced structure generalized section of the present invention four, up and down two-layer circuit layer reinforced structure generalized section of the present invention five, up and down two-layer circuit layer reinforced structure generalized section of the present invention six, two-layer circuit layer reinforced structure generalized section seven up and down of the present invention and the two-layer circuit layer reinforced structure generalized section eight up and down of the present invention of putting of the present invention of putting of the present invention of putting of the present invention.As shown in the figure: the present invention is a kind of manufacture method of build-up circuit board, and it comprises the following steps: at least
(A) select double-sided substrate 10: as shown in Figure 2, select one comprise one first dielectric layer 31, a first metal layer 32 and one second metal level 33 double-sided substrate 1;
(B) first and second resistance layer 11 of fitting: as shown in Figure 3, respectively at the one first resistance layer 34 of fitting on the first metal layer 32 of this double-sided substrate, and on second metal level 33 of this double-sided substrate to cover the shape one second resistance layer 35 of fitting fully;
(C) form several first openings 12: as shown in Figure 4, on this first resistance layer 34, form several first openings 36 with exposure and visualization way, to appear the first metal layer 32 under it;
(D) remove the first metal layer 13: as shown in Figure 5, remove the first metal layer 32 of these first opening, 36 belows with etching mode;
(E) formation first line layer 14: as shown in Figure 6, remove this first resistance layer and this second resistance layer, first line layer 37 that this first metal layer formation one is had as electric connection pad;
(F) circuit substrate 15 of formation three-decker: as shown in Figure 7; The directly pressing or second dielectric layer 38 and one three metal level 39 identical with this first dielectric layer 31 of fitting on this first line layer 37 and this first dielectric layer 31 form the circuit substrate 2a of a three-decker;
(G) form several second openings 16: as shown in Figure 8; On the 3rd metal level 39 and this second dielectric layer 38, form several second openings 40 with the laser drill mode; To appear first 37a of first line layer 37 under it; Wherein, these several second opening 40 can be done out earlier behind the copper window via laser drill again, also or directly form with the laser drill mode;
(H) electroless-plating and plating the 4th metal level 17: as shown in Figure 9; In several second openings and on this first line layer 37 and the 3rd metal level 39, form one the 4th metal level 41 with electroless-plating and plating mode; Wherein, The 4th metal level 41 be as with the electric connection usefulness of this first line layer 37, and be connected 46 conductings of several first laser blind holes between layer and the layer by plating;
(I) third and fourth resistance layer 18 of fitting: shown in figure 10, respectively at one the 3rd resistance layer 42 of fitting on the 4th metal level 41, and on this second metal level 33 to cover shape one the 4th resistance layer 43 of fitting fully;
(J) form several the 3rd openings 19: shown in figure 11, on the 3rd resistance layer 42, form several the 3rd openings 44 with exposure and visualization way, to appear the 4th metal level 41 under it;
(K) remove third and fourth metal level 20: shown in figure 12, remove the 3rd metal level 39 and the 4th metal level 41 of the 3rd opening 44 belows with etching mode;
(L) three laminar substrates 21 of two-layer tool patterned circuit of completion and electric connection: shown in figure 13; Remove the 3rd resistance layer the 42 and the 4th resistance layer 43; Make this third and fourth metal level form a tertiary circuit layer 45, so far accomplish three laminar substrate 2b of a two-layer tool patterned circuit and electric connection;
(M) pressing the 3rd dielectric layer and the 5th metal level 22: shown in figure 14, pressing 1 the 3rd dielectric layer 47 and one the 5th metal level 48 again on this tertiary circuit layer 45 and this second dielectric layer 38;
(N) form several fourth, fifth openings 23: shown in figure 15; Form several the 4th openings 49 with the laser drill mode respectively on this second metal level 33 and this first dielectric layer 31; To appear its following second 37b of first line layer 37 of patterning; And on the 5th metal level 48 and the 3rd dielectric layer 47, form several the 5th openings 50; To appear its down tertiary circuit layer 45 of patterning, wherein, these several fourth, fifth opening 49,50 can be done out earlier behind the copper window via laser drill again, also or directly form with the laser drill mode;
(O) electroless-plating and plating the 6th, seven metal levels 24: shown in figure 16; Form one the 6th metal level 51 with electroless-plating and plating mode on this second metal level 33 respectively at reaching in several the 4th openings; And formation one the 7th metal level 52 in several the 5th openings and on the 5th metal level 48; Wherein, the layer with the layer between be connected by the plating 53,54 conductings of several second and third laser blind holes;
(P) the 5th, the six resistance layers 25 of fitting: shown in figure 17, respectively at one the 5th resistance layer 55 of fitting on the 6th metal level 51, and one the 6th resistance layer 56 of on the 7th metal level 52, fitting;
(Q) form several the 6th, minion mouth 26: shown in figure 18; Hinder several the 6th openings 57 of formation on the layer 55 with exposure and visualization way respectively at the 5th; To appear the 6th metal level 51 under it; And on the 6th resistance layer 56, form several minion mouths 58, to appear its 7th metal level 52 down;
(R) remove second, five, six, seven metal levels 27: shown in figure 19; Remove second metal level 33 and the 6th metal level 51 of the 6th opening 57 belows and the 5th metal level 48 and the 7th metal level 52 that remove these minion mouth 58 belows respectively with etching mode;
(S) four laminar substrates 28 of four layers of tool patterned circuit of completion and electric connection: shown in figure 20; Remove the 5th resistance layer respectively; Make this second, six metal levels formation one second line layer 59 of patterning; And remove the 6th resistance layer, make the 5th, seven metal levels formation one the 4th line layer 60 of patterning.So far accomplish four laminar substrates 3 of one or four layers of tool patterned circuit and electric connection, and can select directly to carry out step (T) or step (U);
(T) put brilliant side and ball side line layer electric connection pad and make 29: carry out putting brilliant side and ball side line layer electric connection pad and make, it comprises the following step at least:
(t1) apply first and second welding resisting layer 291: shown in figure 21; Apply first welding resisting layer 61 that one deck insulation protection is used respectively on this second line layer 59 and this first dielectric layer 31, and on the 4th line layer 60 and the 3rd dielectric layer 47, also apply second welding resisting layer 62 that one deck insulation protection is used;
(t2) form several the 8th, nine openings 292: shown in figure 22, on this first welding resisting layer 61, form several octavo mouths 63 respectively with exposure and visualization way, and on this second welding resisting layer 62, form several the 9th openings 64.By this to appear the circuit layer reinforced structure as electric connection pad;
That (t3) accomplishes the tool complete patternization puts brilliant side and ball side line layer 293: shown in figure 23, respectively at forming one first barrier layer 65 in several octavo mouths 63, and in several the 9th openings 64 formation one second barrier layer 66.In this, what obtain the tool complete patternization puts brilliant side and ball side line layer, forms one or four layers of non-core layer multi-layer encapsulation substrate 4, and wherein, this first and second barrier layer 65,66 can be nickel-gold layer.
(U) carry out upper and lower two-layer circuit layer reinforced structure and make 30: also can on four laminar substrates of this step (S), directly carry out upper and lower two-layer circuit layer reinforced structure and make, it comprises the following step at least:
(u1) applying fourth, fifth dielectric layer 301: shown in figure 24; Respectively at the directly pressing or one the 4th dielectric layer 67 of fitting on this second line layer 59 and this first dielectric layer 31, and on the 4th line layer 60 and the 3rd dielectric layer 47 directly the pressing or one the 5th dielectric layer 68 of fitting;
(u2) form several the tenth, 11 openings 302: shown in figure 25; With the laser drill mode respectively at forming several the tenth openings 69 on the 4th dielectric layer 67; Appearing second line layer 59 under it, and on the 5th dielectric layer 68, form several the 11 openings 70, to appear the 4th line layer 60 under it; Wherein, this several the tenth, 11 openings the 69, the 70th are done out earlier behind the copper window via laser drill again, also or are directly formed with the laser drill mode;
(u3) form first and second crystal seed layer 303: shown in figure 26; Form one first crystal seed layer 71 with electroless-plating and plating mode respectively at the 4th dielectric layer 67 and several the tenth opening 69 surfaces; And in the 5th dielectric layer 68 and several the 11 opening 70 surface formation one second crystal seed layers 72; Wherein, this first and second crystal seed layer 71,72 can be metal copper layer;
(u4) the 7th, the eight resistance layers 304 of fitting: shown in figure 27, respectively at one the 7th resistance layer 73 of fitting on this first crystal seed layer 71, and one the 8th resistance layer 74 of on this second crystal seed layer 72, fitting;
(u5) form several the 12,13 openings 305: shown in figure 28; Hinder several twelvemo mouths 75 of formation on the layer 73 with exposure and visualization way respectively at the 7th; And appear this first crystal seed layer 71; And on the 8th resistance layer 74, form several the 13 openings 76, and appear this second crystal seed layer 72;
(u6) electroless-plating and plating the 8th, nine metal levels 306: shown in figure 29; With electroless-plating and plating mode; Respectively at formation one the 8th metal level 77 on first crystal seed layer 71 in several twelvemo mouths, and form one the 9th metal level 78 on second crystal seed layer 72 in several the 13 openings;
(u7) remove the 7th, eight resistance layers 307: shown in figure 30, remove the 7th resistance layer and the 8th resistance layer, to appear first and second crystal seed layer 71,72 under it respectively; And
(u8) six laminar substrates 308 of formation tool patterned circuit and electric connection: shown in figure 31; Remove first crystal seed layer that this appears respectively with etching mode; And make first crystal seed layer and the 8th metal level on the 4th dielectric layer 67 form one the 5th line layer 79; And remove second crystal seed layer that this appears, and make second crystal seed layer and the 9th metal level on the 5th dielectric layer 68 form one the 6th line layer 80.In this, obtain the circuit layer reinforced structure of each one deck up and down, form six laminar substrates 5 of a tool patterned circuit and electric connection.
The present invention also can continue to increase the circuit layer reinforced structure on the structure of this six laminar substrate, to form the base plate for packaging of the more even numbers multilayers of tool; Also or put brilliant side and the ball side line layer electric connection pad that can directly carry out this step (T) make.
Wherein, This first～five dielectric layer 31,38,47,67,68 can be ABF (Ajinomoto Build-up Film), benzocyclobutene (Benzocyclo-buthene; BCB), two Maleimides-triazine resin (Bismaleimide Triazine; BT), epoxy resin board (FR4, FR5), polyimides (Polyimide, PI), polytetrafluoroethylene (Poly (tetra-floroethylene), PTFE) or epoxy resin and glass fiber one of form; This dry film that the first～eight resistance layer 34,35,42,43,55,56,73,74 can also print or the rotary coating mode is done or the high sensing optical activity photoresistance of wet film; This first～nine metal level 32,33,39,41,48,51,52,77,78 can be copper or other equivalent metal; The method that removes of this first～seven metal level 32,33,39,41,48,51,52 and this first and second crystal seed layer 71,72 can be etching or other equivalent method; The method that removes of this first～eight resistance layer 34,35,42,43,55,56,73,74 can be to be peeled off or other equivalent method.
When the present invention in when utilization; Be on a two-sided substrate, to make an individual layer circuit with photolithography and etching mode earlier; By this with electric connection pad as layer reinforced structure; Form first build-up circuit in this individual layer circuit connection gasket with the pressing mode more afterwards, forming the circuit board of a tool three-layer metal structure, and wherein two series of strata have been accomplished patterned circuit and have been seen through several and electroplate blind holes and produce electric connection.Then; On this first build-up circuit structure, form second build-up circuit again; Make the metal level of former not patterned circuit form the 3rd build-up circuit simultaneously, four laminar substrates that become a tool patterned circuit and electrically conduct, and can be further with the upper and lower layer of this four laminar substrate respectively as the electric connection pad of layer reinforced structure; Also or be, then be with several plating blind hole or the conducting of buried via hole institute connecting its mode of putting brilliant side, ball side and middle each layer as putting the complete line of brilliant side and ball side.By this; Use the highdensity build-up circuit board manufacturing method of the present invention; The multilayered semiconductor package substrate construction of made; Can effectively improve ultra-thin stratum nucleare substrate plate prying problem and simplify the making flow process of traditional build-up circuit board, can form the base plate for packaging of even numbers multilayer, and then can effectively reach the purpose that reduces the finished product plate thickness and reduce cost of manufacture according to actual demand.
In sum; The present invention can effectively improve the various shortcoming of prior art, can accomplish semiconductor layer multilayer packaging substrate structure, comprises two-layer tool patterned circuit and has accomplished even numbers sandwich constructions such as brilliant side of putting of patterned circuit processing procedure and ball side line layer; Can effectively improve ultra-thin stratum nucleare substrate plate prying problem and simplify the making flow process of traditional build-up circuit board; Be a base plate for packaging that can form the even numbers multilayer, and can effectively reach the purpose that reduces the finished product plate thickness and reduce cost of manufacture, and then make the present invention can more progressive, more practical, more meet user institute palpus according to actual demand; Really meet the important document of application for a patent for invention, proposed patent application in accordance with the law.
Claims (18)
1. the manufacture method of a build-up circuit board, it is characterized in that: this method comprises the following step at least:
(A) selection one comprises the double-sided substrate of one first dielectric layer, a first metal layer and one second metal level;
(B) respectively form first and second resistance layer on first and second metal level respectively at this double-sided substrate;
(C) on this first resistance layer, form several first openings, appear the first metal layer under it;
(D) remove the first metal layer of this first opening below;
(E) remove this first resistance layer and this second resistance layer, first line layer that formation one has as electric connection pad;
(F) on this first line layer and this first dielectric layer, form one second dielectric layer and one the 3rd metal level, form the circuit substrate of a three-decker;
(G) on the 3rd metal level and this second dielectric layer, form several second openings, appear first of first line layer under it;
(H) form one the 4th metal level in several second openings and on this first line layer and the 3rd metal level;
(I) respectively at respectively forming third and fourth resistance layer on the 4th, two metal levels;
(J) on the 3rd resistance layer, form several the 3rd openings, appear the 4th metal level under it;
(K) remove the 3rd metal level and the 4th metal level of the 3rd opening below;
(L) remove the 3rd resistance layer and the 4th resistance layer, make this third and fourth metal level formation one tertiary circuit layer of patterning, so far accomplish three laminar substrates of a two-layer tool patterned circuit and electric connection;
(M) pressing 1 the 3rd dielectric layer and one the 5th metal level again on this tertiary circuit layer and this second dielectric layer;
(N) respectively at forming several the 4th openings on this second metal level and this first dielectric layer; Appear its second of first line layer of patterning down; And on the 5th metal level and the 3rd dielectric layer, form several the 5th openings, appear its following tertiary circuit layer of patterning;
(O) form one the 6th metal level on this second metal level respectively at reaching in several the 4th openings, and form one the 7th metal level in several the 5th openings and on the 5th metal level;
(P) respectively at one the 5th, the six resistance layers of respectively fitting on the 6th, seven metal levels;
(Q) upward form several the 6th openings respectively at the 5th resistance layer, appear the 6th metal level under it, and go up several minion mouths of formation, appear the 7th metal level under it in the 6th resistance layer;
(R) remove second metal level and the 6th metal level of the 6th opening below respectively, and the 5th metal level and the 7th metal level that remove this minion mouth below;
(S) remove the 5th resistance layer respectively; Forming second line layer of patterning, and remove the 6th resistance layer, to form the 4th line layer of patterning; So far accomplish four laminar substrates of one or four layers of tool patterned circuit and electric connection, and select directly to carry out step (T) or step (U);
(T) carry out putting brilliant side and ball side line layer electric connection pad and make, it comprises the following step at least:
(t1), and on the 4th line layer and the 3rd dielectric layer, apply one second welding resisting layer respectively at coating one first welding resisting layer on this second line layer and this first dielectric layer;
(t2) on this first and second welding resisting layer, respectively form several the 8th, nine openings respectively, appear the circuit layer reinforced structure by this as electric connection pad; And
(t3) respectively at respectively forming first and second barrier layer in several the 8th, nine openings;
(U) carry out upper and lower two-layer circuit layer reinforced structure and make, it comprises the following step at least:
(u1) respectively at one the 4th dielectric layer of fitting on this second line layer and this first dielectric layer, and one the 5th dielectric layer of on the 4th line layer and the 3rd dielectric layer, fitting;
(u2) respectively at forming several the tenth openings on the 4th dielectric layer, appear second line layer under it, and on the 5th dielectric layer, form several the 11 openings, appear the 4th line layer under it;
(u3) form one first crystal seed layer respectively at the 4th dielectric layer and several the tenth open surfaces, and form one second crystal seed layer in the 5th dielectric layer and several the 11 open surfaces;
(u4) respectively at respectively forming one the 7th, eight resistance layers on this first and second crystal seed layer;
(u5) upward form several twelvemo mouths respectively at the 7th resistance layer, and appear this first crystal seed layer, and go up several the 13 openings of formation, and appear this second crystal seed layer in the 8th resistance layer;
(u6), and form one the 9th metal level on second crystal seed layer in several the 13 openings respectively at formation one the 8th metal level on first crystal seed layer in several twelvemo mouths;
(u7) remove the 7th, eight resistance layers, and appear first and second crystal seed layer under it respectively; And
(u8) remove first crystal seed layer that this appears respectively, and on the 4th dielectric layer, form one the 5th line layer, and remove second crystal seed layer that this appears, and on the 5th dielectric layer, form one the 6th line layer.
2. the manufacture method of build-up circuit board according to claim 1, it is characterized in that: said the first～seven metal level is the copper layer.
3. the manufacture method of build-up circuit board according to claim 1 is characterized in that: said the first～three dielectric layer is ABF, benzocyclobutene, two Maleimide-triazine resin, epoxy resin board, polyimides, polytetrafluoroethylene or one of them composition that epoxy resin is added the composition of glass fiber.
4. the manufacture method of build-up circuit board according to claim 1 is characterized in that: said the first～six resistance layer is the dry film of doing with applying, printing or rotary coating or the high sensing optical activity photoresistance of wet film.
5. the manufacture method of build-up circuit board according to claim 1 is characterized in that: said several first and third, six and the minion mouth form with exposure or visualization way.
6. the manufacture method of build-up circuit board according to claim 1, it is characterized in that: the method that removes of said the first～seven metal level is etching.
7. the manufacture method of build-up circuit board according to claim 1 is characterized in that: the method that removes of said the first～six resistance layer is for peeling off.
8. the manufacture method of build-up circuit board according to claim 1 is characterized in that: said second and third dielectric layer forms with direct pressing or laminating type.
9. the manufacture method of build-up circuit board according to claim 2 is characterized in that: said several second, four and five openings are to do out earlier behind the copper window via laser drill again, also or directly form with the laser drill mode.
10. the manufacture method of build-up circuit board according to claim 1, it is characterized in that: the generation type of said the 4th, six and seven metal levels is electroless-plating and plating.
11. the manufacture method of build-up circuit board according to claim 1 is characterized in that: said several the 8th, nine openings form with exposure or visualization way.
12. the manufacture method of build-up circuit board according to claim 1; It is characterized in that: said step (U) is one or six laminar substrates after accomplishing; And can on this six laminar substrate, continue to increase the making of circuit layer reinforced structure, also or the making that repeats to put brilliant side and ball side line layer.
13. the manufacture method of build-up circuit board according to claim 1 is characterized in that: said the 8th, nine metal levels are the copper layer, and the mode that itself and this first and second crystal seed layer forms is all electroless-plating and plating.
14. the manufacture method of build-up circuit board according to claim 1 is characterized in that: said the 7th, eight resistance layers are the dry film of doing with applying, printing or rotary coating or the high sensing optical activity photoresistance of wet film.
15. the manufacture method of build-up circuit board according to claim 1; It is characterized in that: said four, five dielectric layers are ABF, benzocyclobutene, two Maleimide-triazine resin, epoxy resin board, polyimides, polytetrafluoroethylene or one of them composition that epoxy resin is added the composition of glass fiber, and it forms with direct pressing or laminating type.
16. the manufacture method of build-up circuit board according to claim 2; It is characterized in that: said several the tenth, 11 openings are to do out earlier behind the copper window via laser drill again, also or directly form with the laser drill mode, and these several the 12,13 openings then form with exposure or visualization way.
17. the manufacture method of build-up circuit board according to claim 1 is characterized in that: the method that removes of said the 7th, eight resistance layers is for peeling off.
18. the manufacture method of build-up circuit board according to claim 1 is characterized in that: the method that removes of said first and second crystal seed layer is etching.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100835369A CN101527266B (en) | 2008-03-06 | 2008-03-06 | Manufacture method for layer-adding circuit board |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100835369A CN101527266B (en) | 2008-03-06 | 2008-03-06 | Manufacture method for layer-adding circuit board |
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| CN101527266A CN101527266A (en) | 2009-09-09 |
| CN101527266B true CN101527266B (en) | 2012-03-07 |
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| CN2008100835369A Expired - Fee Related CN101527266B (en) | 2008-03-06 | 2008-03-06 | Manufacture method for layer-adding circuit board |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102378502B (en) * | 2010-08-13 | 2013-11-27 | 欣兴电子股份有限公司 | Circuit board and manufacturing method thereof |
| CN102137551B (en) * | 2011-03-16 | 2012-07-25 | 蔡新民 | Production method of high-frequency four-layer circuit board |
| CN103646880A (en) * | 2013-09-29 | 2014-03-19 | 华进半导体封装先导技术研发中心有限公司 | Packaging technology based on board-level functional substrate and packaging structure |
| CN103745936B (en) * | 2014-02-08 | 2016-08-17 | 华进半导体封装先导技术研发中心有限公司 | The manufacture method of fan-out square chip level package |
| CN107666771A (en) * | 2016-07-29 | 2018-02-06 | 同扬光电（江苏）有限公司 | Circuit board structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1335743A (en) * | 2000-07-26 | 2002-02-13 | 赵远涛 | Technological process of making printed circuit board |
| CN1379616A (en) * | 2001-04-02 | 2002-11-13 | 日东电工株式会社 | Multi layer circuit board and its manufacturing method |
| CN1474642A (en) * | 1997-10-14 | 2004-02-11 | Ҿ쳵���ʽ���� | Multilayer printed circuit board and its producing method,filling resin composition for through hole |
| CN1675760A (en) * | 2002-08-09 | 2005-09-28 | 揖斐电株式会社 | Multilayer printed wiring board |
| CN1292462C (en) * | 2002-11-19 | 2006-12-27 | 精工爱普生株式会社 | Multi-layer distribution board and mfg method, electronic device and electronic apparatus |
-
2008
- 2008-03-06 CN CN2008100835369A patent/CN101527266B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1474642A (en) * | 1997-10-14 | 2004-02-11 | Ҿ쳵���ʽ���� | Multilayer printed circuit board and its producing method,filling resin composition for through hole |
| CN1335743A (en) * | 2000-07-26 | 2002-02-13 | 赵远涛 | Technological process of making printed circuit board |
| CN1379616A (en) * | 2001-04-02 | 2002-11-13 | 日东电工株式会社 | Multi layer circuit board and its manufacturing method |
| CN1675760A (en) * | 2002-08-09 | 2005-09-28 | 揖斐电株式会社 | Multilayer printed wiring board |
| CN1292462C (en) * | 2002-11-19 | 2006-12-27 | 精工爱普生株式会社 | Multi-layer distribution board and mfg method, electronic device and electronic apparatus |
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