1357646 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種增層線路极 指一種以雙介電層支擇之單 彻多㈣基板結構之增層線:板= 【先前技術】 係二基板之製作上’其製作方式通常 係由核匕基板開始，經過鑽孔、電鍵金屬、 雙面線路製作等方式，完成一 土孔及 柘，夕a $ z丄 雙面、，，口構之内層核心 板。二二路增層製程完成-多層封裝基 ^ 3 2圖所示’其係為一有核層封裝基 面=。首先’準備一核心基板81，其中，該核 ^ 1係由一具預定厚度之芯層8 i工及形成於 Q心層8 ί1表面之線路層8 1 2所構成，且該名層 811中係形成有複數個電鍍導通孔8 連接該芯層811表面之線路層812。 措 接著如第圖3 3〜第3 6圖所示，對該核心基板 8 1實施線路增層製程。首先，係於該核心基板8 1 表面形成一第-介電層8 2，且該第一介電層8 2表 面亚形成有複數個第一開口 8 3，以露出該線路層8 1 2，之後，以無電電鍍與電鍍等方式於該第一介電 層8 2外露之表面形成一晶種層8 4，並於該晶種層 1357646 84上形成一圖案化阻層8 中並有複數個第-開二5 f其圓案化阻層85 化線路…：： 露出部份欲形成圖案 二開π86中形二=幸=錢之方式於該第 導電盲列并 圖案化線路層87及複數個 ，並使其第一圖案化線路層8 7得 過該複數個導電盲孔88與該核心基板81357646 IX. Description of the Invention: [Technical Field] The present invention relates to a build-up line pole which refers to a build-up line of a single-to-multiple (four) substrate structure selected by a double dielectric layer: plate = [Prior Art 】 The production of the two substrates is generally made by the core substrate, through the drilling, key metal, double-sided circuit production, etc., to complete a soil hole and 柘, 夕 a $ z丄 double-sided,, The inner core board of the mouth. The two-way build-up process is completed - the multi-layer package base ^ 3 2 is shown as a nucleated layer package substrate =. First, a core substrate 81 is prepared, wherein the core layer 1 is composed of a core layer 8 of a predetermined thickness and a circuit layer 8 1 2 formed on the surface of the Q core layer 8 ί1, and the layer 811 is A wiring layer 812 is formed in which a plurality of plating vias 8 are connected to the surface of the core layer 811. Next, as shown in Figs. 33 to 36, a line build-up process is performed on the core substrate 81. First, a first dielectric layer 82 is formed on the surface of the core substrate 81, and a plurality of first openings 83 are formed on the surface of the first dielectric layer 8 2 to expose the circuit layer 8 1 2, Thereafter, a seed layer 84 is formed on the exposed surface of the first dielectric layer 8 2 by electroless plating and electroplating, and a patterned resist layer 8 is formed on the seed layer 1357646 84 and has a plurality of First-open two 5 f, its rounded resist layer 85 line...:: exposed part to form a pattern two open π86 medium shape two = fortunate = money way in the first conductive blind column and patterned circuit layer 87 and plural And causing the first patterned circuit layer 87 to pass through the plurality of conductive vias 88 and the core substrate 8
8上二電性導通，然後再進行移除該圖 ： =刻=完成後係形成一第一線路增層結構J 矣 …去係可於該第-線路增層結構8a之最外 :表::運用相同之方式形成-第二介電層89l 案化線路層9(}之第二線路增層結構8b，以逐 形成一多層封裝基板。然而，此種製作方 法有佈線讀低、層數Μ流程㈣等缺點。 另外，亦有利用厚銅金屬板當核心材料之方法， 2經過钱刻及塞孔等方式完成一内層核心板後，再 ，路增層製程以完成—多層封裝基板。如第3 7圖〜第39圖所示’其係為另一有核層封裝基板之 意圖。首先’準備一核心基板91，該核心基 =1係由一具預定厚度之金屬層利用姓刻與樹脂塞 1 1以及鑽孔與電鍍通孔9丄2等方式形成之單 層銅核〜基板9 1 ;之後，利用上述線路增層方式， 於§玄核心基板9 1表面形成一第一介電層92及一第 一圖案化線路層9 3 ’藉此構成-具第一線路增層結 6 1357646 構9 a。該法亦與上述方法相同，係可再利用— 增層方式於該第-線路増層結構9a之最 面 成一第二介電層94及—第二圖案化線路層95面= 此構成n線路增層結構9 b，以逐步增層方： ==T。然而’此種製作方法不僅心 基板1作不g，且亦與上述方法相同，具有佈線密 又低：流程複雜等缺點。故’-般習用者係無法符人 使用者於實際使用時之所需β ° 【發明内容】 本發明之主要目的係在於，可完成—半導體多」 封裝基板結構’可有效改善超薄核層基板板f趣… 及簡化傳統增層線路板之製作流程。 齡少^發明之次要目的係在於，可依實際需求形成18 is electrically conductive, and then the figure is removed: = engraved = completed to form a first line build-up structure J 矣 ... can be at the outermost of the first-line build-up structure 8a: Table: : forming the second wiring layer 8b of the second dielectric layer 891 in the same manner to form a multilayer wiring substrate. However, this manufacturing method has a wiring read low layer. There are some disadvantages such as the number of processes (4). In addition, there are also methods of using thick copper metal plates as core materials, 2 after completing an inner core plate by means of money engraving and plugging, and then adding a layer to complete the process - multi-layer package substrate As shown in Figures 37 to 39, 'it is intended to be another core-layer package substrate. First, 'prepare a core substrate 91, which is made up of a metal layer of a predetermined thickness. a single-layer copper core-substrate 9 1 formed by engraving with the resin plug 1 1 and the hole and the plated through hole 9丄2; and then forming a first surface on the surface of the core substrate 9 1 by the above-mentioned line build-up method The dielectric layer 92 and a first patterned circuit layer 9 3 'by forming a first line buildup layer The junction 6 1357646 is 9 a. The method is also the same as the above method, and is re-usable - forming a second dielectric layer 94 and a second patterned circuit layer at the outermost surface of the first-layer germanium layer structure 9a. 95 face = This constitutes the n-line build-up structure 9 b to gradually increase the layer: == T. However, this method of fabrication is not only the core substrate 1 is not g, but also the same as the above method, with dense wiring and low: The process is complicated and so on. Therefore, the 'normal use' is not required for the user to use it in actual use. [Invention] The main purpose of the present invention is to enable the "semiconductor multi-package substrate structure" to be effective. Improve the ultra-thin nuclear substrate board f... and simplify the production process of the traditional layered circuit board. The second purpose of the invention is that it can be formed according to actual needs.
二之封裝基板，並可有效達到降低成品板 減少製作成本之目的。 作方：達5%目的：本發明係-種增層線路板之製 糸以光學微影及姓刻之方式於一雙面 土反上製作—單層線路，藉此以做為增層結構之電性 S墊’之後再於該單層線路連接墊以壓合之方式形 ，增層線路，以形成一具三層金屬結構之電路 j其中兩層係已完成圖案化線路且已透過複數個 技2孔而產生電性連接。接著，再於該第—增層線 上形成第二增層線路，同時使原未圖案化線路 7 1357646 ::屬層形成第三增廣線路，成為一具圖案化線路且 了性導通之四層基板，並可進-步以該四層基板之 、下層分別做為增層結構之電性連接塾，亦或係作 為置晶側與球側之完整線路，而在連接其置晶側、球 側及中，各層之方式則係以複數個電錢盲孔或埋孔所 導通，藉此以完成一無核層多層封裝基板。 【實施方式】 • 請參閱『第1圖〜第3 !圖』所示，係分別為本 發明之製作流程示意圖、本發明之雙面基板剖面示意 圖、本發明之兩層基板（一）剖面示意圖、本發明之 兩層基板（二）剖面示意圖、本發明之兩層基板（三） 剖面示意圖 '本發明之兩層基板（四）剖面示意圖、 本發明之二層基板（五）剖面示意圖、本發明之三層 基板（六）剖申示意圖、本發明之三層基板（七）剖 面示意圖、本發明之三層基板（八）剖面示意圖、本 ® 發明之三層基板（九）剖面示意圖、本發明之三層基 板（十）剖面示意圖、本發明之三層基板（十一）剖 面示意圖、本發明之四層基板（一）剖面示.意圖、本 發明之四層基板（二）剖面示意圖、本發明之四層基 板（三）剖面示意圖、本發明之四層基板（四）剖面 示意圖、本發明之四層基板（五）剖面示意圖、本發 明之四層基板（六）剖面示意圖、本發明具圖案化及 電性連接之四層基板（七）剖面示意圖、本發明之置 1357646 晶側與球側線路層（一）剖面示意圖、本發明之置晶 側與球側線路層（二）剖面示意圖、本發明之置晶側 本發明之上下兩層 本發明之上下兩層 本發明之上下兩層 本發明之上下兩層 本發明之上下兩層 本發明之上下兩層 與球側線路層（三）剖面示意圖、本發明之上下兩層 線路增層結構（一）剖面示意圖The package substrate of the second can effectively reduce the production cost by reducing the finished board. The prescription: up to 5% purpose: the system of the present invention is made of optical lithography and surnamed on the opposite side of a double-sided soil to make a single-layer circuit, thereby serving as a layered structure. The electrical S-pad' is then formed in a press-fit manner on the single-layer line connection pad to form a circuit having a three-layer metal structure, wherein two layers have completed the patterned circuit and have passed through a plurality of 2 holes to make an electrical connection. Then, a second build-up line is formed on the first build-up line, and the original unpatterned line 7 1357646 :: genus layer forms a third augmented line, and becomes a patterned line and is electrically connected. The substrate can be further stepped on the lower layer of the four-layer substrate as an electrical connection port of the build-up structure, or as a complete line of the crystallized side and the ball side, and connected to the crystallizing side and the ball In the side and the middle, the manner of each layer is conducted by a plurality of electric money blind holes or buried holes, thereby completing a coreless multi-layer package substrate. [Embodiment] FIG. 1 is a schematic view showing a manufacturing process of the present invention, a schematic cross-sectional view of a double-sided substrate of the present invention, and a schematic cross-sectional view of a two-layer substrate (1) of the present invention. A schematic view of a two-layer substrate (2) of the present invention, a two-layer substrate of the present invention (three), a schematic cross-sectional view of a two-layer substrate (four) of the present invention, and a schematic diagram of a two-layer substrate (f) of the present invention. The three-layer substrate of the invention (six) is a schematic cross-sectional view, the three-layer substrate of the present invention (seven), the cross-sectional view of the three-layer substrate (eight) of the present invention, and the three-layer substrate (nine) of the present invention. The three-layer substrate (th) of the present invention is a schematic cross-sectional view of the three-layer substrate (11) of the present invention, and the four-layer substrate (1) of the present invention is shown in cross section. The cross-sectional view of the four-layer substrate (3) of the present invention, the cross-sectional view of the four-layer substrate (four) of the present invention, and the cross-sectional view of the four-layer substrate (f) of the present invention, the present invention Schematic diagram of a four-layer substrate (six), a schematic diagram of a four-layer substrate (seven) having a patterned and electrically connected structure according to the present invention, a schematic diagram of a 1357646 crystal side and a ball-side wiring layer (a) of the present invention, and a schematic view of the present invention Schematic diagram of the crystallized side and ball side circuit layer (2), the crystallized side of the present invention, the upper and lower layers of the present invention, the upper and lower layers of the present invention, the upper and lower layers, the upper and lower layers of the present invention, the upper and lower layers, the upper and lower layers of the present invention Schematic diagram of the upper and lower layers and the ball-side circuit layer (3) of the present invention, and the cross-sectional structure of the two layers of the upper and lower layers of the present invention (1)
線路增層結構（二）剖面示意圖 線路增層結構（三）刳面示意圖 線路增層結構（四）剖面示意圖 線路增層結構（五）剖面示意圖 線路增層結構（六）剖面示意圖 線路增層結構（七）剖面示意圖及本發明之上下兩層 線路增層結構（.八）剖面示意圖。如圖所示：本發明 係-種增層線路板之製作方法，其至少包括下列步驟： (Α)選擇雙面基板1 〇 :如第2圖所示，選擇 -包含-第-介電層3 1、一第一金屬層3 2及一第 二金屬層33之雙面基板1; (Β )貼合第一、二阻層1 1 :如第3圖所示， 分別於該雙面基板之第一金屬層3 2上貼合一第一阻 層3 4，以及於該雙面基板之第二金屬層3 3上以完 全覆蓋狀貼合一第二阻層3 5 ; (c)形成複數個第一開口12:如第4圖所示， 以曝光及顯影之方式在該第—阻層3 4上形成複數個 第一開口 3 6，以顯露其下之第一金屬層3 2 ; (D)移除第一金屬層1 3 :如第5圖所示，以 1357646 之方式移除該第—開σ36下方之[金屬層3 (Ε )形成第一線路層丄4 :如第6圖所示， 除該第-阻層及該第二阻層，使該第一金屬層：成： 具有作為電性連接墊之第一線路層3 7 ; (F )形成三層結構之電路基板丄5 : 所不，於該第一線路層3 7及該第一介電層3 接壓合或貼合一與該第一介電層3 1相同之第—^直 層38及一第三金屬層39,形成一三層二， 基板2a; “。構之電路 (G) 形成複數個第二開口 i 6 :如第8圖所示， 以雷射鑽孔之方式於該第三金屬層3 9與該第二介電 層3 8上形成複數個第二開口 4 〇，以顯露其下之第 -線路層37之第-面37a，其中，該複數個第二開 口 4 0係可先做開銅窗後再經由雷射鑽孔、亦或係直 接以雷射鑽孔之方式形成； (H) 無電電鍵與電鑛第四金屬層1 7 ·•如.第g 圖所示，以無電電鍍與電鍍之方式於複數個第二開口 中及該第一線路層3 7與該第三金屬層3 9上形成一 第四金屬層4 1 ，其中，該第四金屬層4丄係做為與 δ亥第一線路層3 7之電性連接用，且層與層之間之連 接係由電鐘之複數個第一雷射盲孔4 6所導通； 10 1357646 ，二2貼合第三、四阻層1 8 :如第i 〇圖所示 第四金屬層41上貼合一第三阻層42以 層4 J ;—金屬層3 3上以完全覆蓋狀貼合—第四阻 干，以成複數個第三開口 19 :如第11圖所 =個第之方式在該第三阻層42上形成複 ^ 4 4，以顯露其下之第四金屬層4工； 示，除第三、四金屬層20 :如第12圖所 二式移除該第三開口44下方之第三金 屬屬39與第四金屬層41; 某板完成兩層具圖案化線路及電性連接之三層 土板2 1 :如第1 3圖所示，移除該第 四阻層，使爷坌- 丨且層及J第 m 金屬層形成一第三線路層45， 成一兩層具圖案化線路及電性連接之三層基板 jΜ )一壓合第三介電層及第五金屬層2 2 :如第 "所不’於該第三線路層4 5及該第二介電声3 8上再壓合-第三介電層〇及-第五金屬層48 (Ν)形成複數個第四 '五開口 2 3 :如 雷射鑽孔之方式分別於該第二金屬層” 一:第-介電層3 1上形成複數個第四開口4 9，以 顯路其下已圖案化之第一線路層3 7之第 7 1357646 b’以及於該第五金屬層4 8與該第三介電層4 7上形 成複數個第五開口 5〇，以顯露其下已圖案化之第三 線路層4 5，其中，該複數個第四、五開口 4 9、5 0係可先做開鋼窗後再經由雷射鑽孔、亦或係直接以 雷射鑽孔之方式形成； (〇）無電電錄與電鑛第六、七金屬層2 4 :如 第1 6圖所示，以無電電鍍與電鍍之方式分別於複數 • 個第四開口中及該第二金屬層3 3上形成一第六金屬 層51，以及於複數個第五開口中及該第五金屬層4 8上形成一第七金屬層5 2，其中，層與層之間之連 接係由電鍍之複數個第二、三雷射盲孔5 3、5 4所 導通； (P) 貼合第五、六阻層2 5 :如第1 7圖所示， 为別於5亥第六金屬層5 1上貼合一第五阻層5 5，以 • 及於該第七金屬層·52上貼合一第六阻層56 ; (Q) 形成複數個第六、七開口 2 6 :如第1 8 圖所示，以曝光及顯影之方式分別於該第五阻層5 5 上形成複數個第六開口. 5 7，以顯露其下之第六金屬 層5 1，以及於該第六阻層5 6上形成複數個第七開 口 58 ’以顯露其下之第七金屬層52 ; (R) 移除第二、五、六、七金屬層27:如第 1 9圖所示，以蝕刻之方式分別移除該第六開口 5 7 下方之第二金屬層33與第六金屬層51，以及移除 12 1357646 該第七開口 5 8下方之第五金屬層4 8與第七金屬層 5 2； " (S) 完成四層具圖案化線路及電性連接之四層 基板2 8 :如第2 0圖所示，分別移除該第五阻層， 使該第二、六金屬層形成一已圖案化之第二線路層5 9 ’以及移除該第六阻層’使該第五、七金屬層形成 -已圖案化之第四線路層6 〇。至此完成一四層且圖 # 案化線路及電性連接之四層基板3，並可選擇直接進 行步驟（T)或步驟（u); (T) 進行置晶側與球側線路層電性連接塾製作 2 9 .進行-置晶側與球側線路層電性連接塾製作， 其至少包含下列步驟： 上U室覆第-、二防焊層2 9工：如第： 1圖所不，分別於該第二線路層5 g與該第一介電力 • 31上塗覆一層絕緣保護用之第-防焊層61，以; 於該第四線路層60與該第三介電層47上亦塗覆一 層絕緣保護用之第二防焊層6 2 . 乂 （ t 2 )形成複數個第八、九開口 2 9 2 :女 第2 2圖所示，以曝光及蔡 ^ 焊層6 1上形成複數個第八：：別在。亥第1 防焊層6 2上形成複數個苐以亥第- 線路増層結構作為電性連開口64。错此以㈣ 13 (t 3 )完成具完整圖案化之置晶側與球側線 口曰2 9 3 .如第2 3圖所示，分別於複數個第八開 6 3中形成一第一阻障層6 5 ,以及於複數個第九 ::口 6 4中形成一第二阻障層“。於此，獲得具完 :圖案化之置晶側與球側線路層，形成一四層益核層 =層封裝基板4，其中，該第—、二阻障層6 5、6 6係可為鎳金層。 (u )進行上、下兩層之線路增層結構製作3 〇 : :可於該步驟（s )之四層基板上直接進行上、下兩 曰之線路增層結構製作，其至少包含下列步驟： (u 1 )貼合第四、五介電層3 〇 i :如第2 t所示’分別於該第二線路層59與該第一介電層 ^直接壓合或貼合—第四介電層“，以及於該 ί四'=路層6 G與該第三介電層4 7上直接壓合或貼 合一第五介電層6 8 ; “2)形成複數個第十、十一開口 3〇2 : 二:圖所示’以雷射鑽孔之方式分別於該第四介 電層β 7上形成複數個第十 第二線路層59,以及二==’以顯露其下之 數個第十-開口 70，:二:電層68上形成複 η ., ，”、員路其下之第四線路層6 0,其中’該複數個第十、十—開口6 做開銅窗後再經由雷射鑽 ’、无 之方式形成； ㈣亦或係錢以f射鑽孔 14 (U 3 )形成第一、二晶種層3 ο 3 :如第2 6圖所示，以無電電鍍與電鍍之方式分別於該第四介 電層6 7與複數個第十開口 6 9表面形成一第—晶種 層7 1，以及於該第五介電層6 8與複數個第十一開 口 70表面形成一第二晶種層72，其中，該第一、 二晶種層7 1、7 2係.可為金屬銅層； (u 4 )貼合第七、八阻層3 〇 4 :如第2 7 圖所不，分別於該第一晶種層7丄上貼合一第七阻層 7 3，以及於該第二晶種層7 2上貼合一第八阻層7 4 ； a (u5)形成複數個第十二、十三開口3〇5: 如第2 8圖所示，以曝光及顯影之方式分別於該第七 阻層7 3上形成複數個第十二開口 7 5，並顯露該第 一晶種層7 1，以及於該第八阻層7 4上形成複數個 第十二開口 7 6，並顯露該第二晶種層7 2 ; (u6)無電電鍍與電鍍第八、九金屬層3〇 6 :如第2 9圖所示，以無電電鍍與電鍍之方式，分 別於複數個第十二開口中之第一晶種層7丄上形成— 第八金屬層77，以及於複數個第十三開口中之第二 晶種層72上形成一第九金屬層78; (u 7 )移除第七、八阻層3 〇 7 :如第3 〇 圖所示，移除該第七阻層及該第八阻層，以分別顯露 其下之第一、二晶種層7 1、72 ;以及 15 I u 8 )形成具圖案化線路及電性連接之六層 基板3 0 8 :如第3 1圖所示，以蝕刻之方式分別移 除该顯露之第一晶種層，並使該第四介電層6 7上之 第一晶種層及第八金屬層形成一第五線路層7 9，以 及移除該顯露之第二晶種層，並使該第五介電層6 8 上之第二晶種層及第九金屬層形成一第六線路層8 〇 °於此，獲得上下各一層之線路增層結構，形成一 具圖案化線路及電性連接之六層基板5。 本發明亦可在此六層基板之結構上繼續增加線路 增層結構，以形成具更多雙數多層之封裝基板；亦或 可直接進行該步驟（T)之置晶側與球側線路層電性 連接墊製作。 其中，該第--五介電層31、38、47、6 7、6 8 係可為 ABF ( Ajinomoto Build-up Film )、苯 環丁烯（Benzocyci0_buthene，BCB)、雙馬來亞醯胺· 二氮雜笨樹脂（Bismalejmide Triazine，bt )、環氧樹月匕 板（FR4、FR5 )、聚醯亞胺（Polyimide，ρι)、聚四氟 乙烯（P0丨y(tetra-f丨0roethy丨ene)，PTFE).或環氧樹脂及 玻璃纖維所組成之一者；該第--八阻層3 4、3 5 :2、4 3、5 5、5 6、7 3、7 4亦可以印刷或 旋轉塗佈之方式所為之乾膜或溼膜之高感光性先阻； 該第一〜九金屬層32、33、39、4ι、: 5 1、5 2、7 7、7 8係可為銅或其它等效金屬； 該第一〜七金屬層3 2、3 3、3 9、4丄、4 8、 5 1、5 2及該第一、二晶種層7丄、7 2之移除方 法係可為蝕刻或其它等效方法；該第-〜八阻層3 4、3 5 :42、43、55、56、73、7:之 移除方法係可為剝離或其它等效方法。 當本發明於運用時，係先以光學微影及姓刻之方 ^一雙面基板上製作—單層線路，藉此以做為増層 :構：：性連接墊’之後再於該單層線路連接墊以壓 St成第一增層線路，以形成-具三層金屬結 带，且其中兩層係已完成圖案化線路且已透 過後數個電鑛盲孔而產生電性連接。接著，再於4 一增層線路結構上形二增層線路 ^ 2線路之金屬層形成第三增層線路，成】= 電性導通之四層基板，並可進-步以該 2=罢下層分別做為增層結構之電性連接塾’亦 ===側之完整線路:而在連接其置晶 埋孔所基，s “ /之方式則係以複數個電鍍盲孔或 製作方夺^藉此，使用本發明高密度之增層線路板 ^效改盖之半導體多層封裝基板結構，係可 路板之^ =核層基板板資勉問題及簡化傳統增層線 之封穿流程，係—個可依實際需求形成雙數多層 製作成目：而可有效達到降低成品板厚度及減少 1357646 綜上所述，本發明係一種，可有效改善習用之種 種缺點，係可完成一半導體多層封裝基板結構，包括 兩層具圖案化線路及已完成圖案化線路製程之置晶側 與球側線路層等雙數多層結構，可有效改善超薄核層 基板板彎翹問題及簡化傳統增層線路板之製作流程， 係一個可依實際需求形成雙數多層之封裝基板，並可 有效達到降低成品板厚度及減少製作成本之目的，進 而使本發明之産生能更進步、更實用、更符合使用者 之所須，確已符合發明專利申請之要件，爰依法提出 專利申請。 惟以上所述者，僅為本發明之較佳實施例而已’ 當不能以此限定本發明實施之範圍；故，凡依本發明 申清專利範圍及發明說明書内容所作之簡單的等效變 化與修飾’皆應仍屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 第1圖’係本發明之製作流程示意圖。 第2圖’係本發明之雙面基板刮面示意圖。 第3圖’係本發明之兩層基板（一）剖面示意圖。 第4圖’係本發明之兩層基板（二）剖面示意圖。 第5圖’係本發明之兩層基板（三）剖面示意圖。 第6圖’係本發明之兩層基板（四）剖面示意圖。 第7圖’係本發明之三層基板（五）剖面示意圖。 第8圖’係本發明之三層基板（六）剖面示意圖。 第9圖’係本發明之三層基板（七）剖面示意圖。 第1 0圖’係本發明之三層基板（八）剖面示意圖° 第1 1圖’係本發明之三層基板（九）剖面示意圖。 第1 2圖’係本發明之三層基板（十）剖面示意圖。 第1 3圖’係本發明之三層基板（十一）剖面示意圖。 第1 4圖’係本發明之四層基板（一）剖面示意圖。 第1 5圖’係本發明之四層基板（二）剖面示意圖。 第1 6圖’係本發明之四層基板（三）剖面示意圖。 第1 7圖’係本發明之四層基板（四）剖面示意圖。 第1 8圖’係本發明之四層基板（五）剖面示意圖。. 第1 9圖’係本發明之四層基板（六）.剖面示意圖。 1357646 第2 0圖’係本發明之四層基板（七）剖面示意圖。 第2 1圖，係本發明之置晶側與球側線路層（一）剖 面示意圖。 第2 2圖，係本發明之置晶侧與球側線路層（二）剖 面示意圖。 第2 3圖，係本發明之實施置晶側與球側線路層（三） 剖面示意圖。 第2 4圖’係本發明之上下兩層線路增層結構（一） 剖面示意圖。 第2 5圖’係本發明之上下兩層線路增層結構（二） 剖面示意圖。 第2 6圖，係本發明之上下兩層線路增層結構（三） 剖面示意圖。 第2 7圖’係本發明之上下兩層線路增層結構（四） 剖面示意圖。 第2 8圖，係本發明之上下兩層線路增層結構（五） 剖面示意圖。 第2 9圖’係本發明之上下兩層線路增層結構（六） 剖面示意圖。 第3 0圖，係本發明之上下兩層線路增層結構（七） 剖面示意圖。 第3 1圖，係本發明之上下兩層線路增層結構（八） 20 1357646 剖面示意圖。 第3 2圖，係習用有核層封裝基板之剖面示意圖。 第3 3圖，係習用之實施線路增層（一）剖面示意圖。Line build-up structure (2) Cross-section diagram Line build-up structure (3) 刳 示意图 线路 线路 线路 线路 ( ( 四 四 四 四 四 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路(7) Schematic diagram of the section and a schematic diagram of the section of the two-layer line-added structure (.8) above and below the present invention. As shown in the figure: the present invention is a method for manufacturing a build-up wiring board, which comprises at least the following steps: (Α) selecting a double-sided substrate 1 〇: as shown in FIG. 2, selecting-including-first-dielectric layer 3, a double-sided substrate 1 of a first metal layer 3 2 and a second metal layer 33; (Β) bonding the first and second resist layers 1 1 : as shown in FIG. 3, respectively, on the double-sided substrate a first resist layer 34 is attached to the first metal layer 3 2 , and a second resist layer 3 5 is attached to the second metal layer 3 3 of the double-sided substrate in a completely covered manner; (c) forming a plurality of first openings 12: as shown in FIG. 4, a plurality of first openings 3 6 are formed on the first resist layer 34 by exposure and development to reveal the first metal layer 3 2 therebelow; (D) removing the first metal layer 13: as shown in FIG. 5, removing the [metal layer 3 (Ε) under the first opening σ36 in the manner of 1357646 to form the first wiring layer 丄4: as in the sixth As shown in the figure, in addition to the first resist layer and the second resist layer, the first metal layer is formed as: a first circuit layer 3 7 as an electrical connection pad; (F) a circuit substrate forming a three-layer structure丄5: No, in the first circuit layer 3 7 and the first dielectric layer 3 is bonded or bonded to a first straight layer 38 and a third metal layer 39 which are the same as the first dielectric layer 3 1 to form a three-layer two, substrate 2a The circuit (G) forms a plurality of second openings i 6 : as shown in FIG. 8 , on the third metal layer 39 and the second dielectric layer 38 by laser drilling Forming a plurality of second openings 4 〇 to expose a first surface 37a of the underlying circuit layer 37, wherein the plurality of second openings 40 are first opened by a copper window and then laser-drilled, Or it can be formed directly by laser drilling; (H) No electric key and electric metal fourth metal layer 1 7 ·• As shown in Figure g, in electroless plating and electroplating in multiples Forming a fourth metal layer 4 1 in the opening and the first circuit layer 37 and the third metal layer 39, wherein the fourth metal layer 4 is used as the first circuit layer 37 For electrical connection, and the connection between the layers is connected by a plurality of first laser blind holes 46 of the electric clock; 10 1357646, two 2 attached third and fourth resist layers 18: as i The fourth metal layer 41 shown in the figure Laying a third resist layer 42 to the layer 4 J; the metal layer 3 3 is completely covered - the fourth barrier is formed to form a plurality of third openings 19: as shown in FIG. 11 Forming a fourth surface on the third resist layer 42 to expose the fourth metal layer 4 underneath; except for the third and fourth metal layers 20: removing the third opening as shown in FIG. 44 below the third metal genus 39 and the fourth metal layer 41; a board completes two layers of patterned lines and electrically connected three layers of soil 2 1 : as shown in Figure 13, remove the fourth resistance a layer, a layer of the third layer 45 formed by the layer of the layer of the 第 及 and the layer of the J m, forming a three-layer substrate with a patterned circuit and an electrical connection, a third dielectric layer and a third dielectric layer The fifth metal layer 2 2 is re-compressed on the third circuit layer 45 and the second dielectric sound 38 as described above - the third dielectric layer and the fifth metal layer 48 (Ν Forming a plurality of fourth 'five openings 2 3 : forming a plurality of fourth openings 4 9 on the second metal layer "1" on the first dielectric layer 3 1 such as laser drilling The patterned first circuit layer 3 7 7 1357646 b' and forming a plurality of fifth openings 5 于 on the fifth metal layer 408 and the third dielectric layer 407 to expose the patterned third circuit layer 45, wherein A plurality of fourth and fifth openings 4 9 and 5 0 can be formed by opening a steel window and then drilling through a laser, or directly by laser drilling; (〇) no electric record and electric mine Six or seven metal layers 2 4 : as shown in FIG. 16 , a sixth metal layer 51 is formed on the plurality of fourth openings and the second metal layer 3 3 by electroless plating and electroplating, respectively, and Forming a seventh metal layer 52 in the plurality of fifth openings and the fifth metal layer 48, wherein the connection between the layers is performed by electroplating a plurality of second and third laser blind holes 5 3 (5) affixing the fifth and sixth resistive layers 2 5 : as shown in FIG. 7 , a fifth resistive layer 5 5 is attached to the fifth metal layer 5 1 of the 5th, And a sixth resist layer 56 is attached to the seventh metal layer 52; (Q) forming a plurality of sixth and seventh openings 2 6 : as shown in FIG. 18, respectively, by exposure and development In the fifth a plurality of sixth openings are formed on the layer 5 5 . 5 7 to expose the sixth metal layer 5 1 , and a plurality of seventh openings 58 ′ are formed on the sixth resist layer 56 to reveal the next a seven metal layer 52; (R) removing the second, fifth, sixth, and seventh metal layers 27: as shown in FIG. 9, removing the second metal layer 33 under the sixth opening 57 by etching And the sixth metal layer 51, and removing the first metal layer 4 8 and the seventh metal layer 5 2 under the seventh opening 58 from the 12 1357646; " (S) completing the four-layer patterned circuit and electrical connection a four-layer substrate 2 8 : as shown in FIG. 20, respectively removing the fifth resist layer, forming the second and sixth metal layers to form a patterned second circuit layer 5 9 ' and removing the first The six-resist layer 'forms the fifth and seventh metal layers to form a patterned fourth wiring layer 6 〇. So far, complete a four-layer and four-layer substrate 3 of the circuit and the electrical connection, and choose to directly perform the step (T) or the step (u); (T) perform the electroplating side and the ball side circuit layer electrical properties. Connection 塾 制作 2 9 . Performing - the connection between the crystallized side and the ball - side circuit layer, which comprises at least the following steps: Upper U-coating - and second solder mask 2 9: As shown in Figure 1: Applying a first solder resist layer 61 for insulating protection to the second dielectric layer 5 g and the first dielectric layer 31, respectively, on the fourth circuit layer 60 and the third dielectric layer 47. A second solder mask 6 2 for insulating protection is also applied. 乂( t 2 ) forms a plurality of eighth and nine openings 2 9 2 : female 2nd 2, for exposure and soldering layer 6 1 Form a plural number eight:: No. A plurality of tantalum-line layer structures are formed on the first solder resist layer 6 2 as the electrical connection opening 64. In this case, the (4) 13 (t 3 ) completes the crystallized side and the ball side line port 曰 2 9 3 with complete patterning. As shown in Fig. 2, a first resistance is formed in the plurality of eighth openings 6 3 respectively. a barrier layer 6 5 and a second barrier layer are formed in the plurality of ninth::ports 6 4 . Here, the finished: patterned crystal side and ball side circuit layer are formed to form a four layer benefit The core layer=layer package substrate 4, wherein the first and second barrier layers 65, 6 6 may be a nickel gold layer. (u) The line layer structure of the upper and lower layers is made 3 〇: : The circuit of the upper and lower lines is directly formed on the four-layer substrate of the step (s), and the method further comprises the following steps: (u 1 ) bonding the fourth and fifth dielectric layers 3 〇i: 2 t is shown in the second circuit layer 59 and the first dielectric layer ^ directly pressed or bonded - the fourth dielectric layer", and the 四 four '= road layer 6 G and the third A fifth dielectric layer 6 8 is directly pressed or bonded on the dielectric layer 47; "2" forms a plurality of tenth and eleventh openings 3〇2: two: as shown in the figure by laser drilling Forming a plurality of numbers on the fourth dielectric layer β 7 Ten second circuit layers 59, and two ==' to reveal a plurality of tenth-openings 70 underneath, two: the electrical layer 68 forms a complex η., ", the fourth circuit layer 6 under the clerk 0, where 'the plural tenth, tenth - opening 6 is opened by a copper window and then through a laser drill', and there is no way to form; (4) or the money is formed by the f-hole 14 (U 3 ) to form the first, The second seed layer 3 ο 3 : as shown in FIG. 26 , a seed layer 7 is formed on the surface of the fourth dielectric layer VII and the plurality of tenth openings 619 by electroless plating and electroplating, respectively. And forming a second seed layer 72 on the surface of the fifth dielectric layer 68 and the plurality of eleventh openings 70, wherein the first and second seed layers 7 1 and 7 2 are metal. a copper layer; (u 4 ) bonding the seventh and eighth resist layers 3 〇 4 : as shown in FIG. 7 , respectively, a seventh resist layer 7 3 is attached to the first seed layer 7 ,, and The second seed layer 7 2 is adhered to an eighth resist layer 7 4 ; a (u5) forms a plurality of twelfth and thirteenth openings 3〇5: as shown in FIG. 28, for exposure and development Forming a plurality of twelfth openings 7 5 on the seventh resist layer 73 And exposing the first seed layer 71, and forming a plurality of twelfth openings 7 6 on the eighth resist layer 74, and exposing the second seed layer 7 2; (u6) electroless plating and electroplating Eighth, nine metal layers 3〇6: as shown in FIG. 29, formed on the first seed layer 7丄 of the plurality of twelfth openings by electroless plating and electroplating respectively—the eighth metal layer 77, and forming a ninth metal layer 78 on the second seed layer 72 of the plurality of thirteenth openings; (u 7) removing the seventh and eighth resist layers 3 〇7: as shown in FIG. Removing the seventh resist layer and the eighth resist layer to respectively expose the first and second seed layers 7 1 , 72 and 15 I u 8 ) to form a patterned circuit and an electrical connection Layer substrate 3 0 8 : as shown in FIG. 31 , the exposed first seed layer is removed by etching, and the first seed layer and the eighth layer on the fourth dielectric layer 6 7 are removed The metal layer forms a fifth wiring layer 7.9, and the exposed second seed layer is removed, and the second seed layer and the ninth metal layer on the fifth dielectric layer 6.8 form a sixth line. Layer 8 〇° here, Have vertical line-up structure of each layer, the substrate 5 is formed a six patterned circuit and electrically connected to it. The invention can also continue to increase the line build-up structure on the structure of the six-layer substrate to form a package substrate with more double-numbered layers; or directly perform the silicon-side and ball-side circuit layers of the step (T) Made of sexual connection pads. Wherein, the first-fifth dielectric layer 31, 38, 47, 67, 6 8 can be ABF (Ajinomoto Build-up Film), benzocyclobutene (Benzocyci0_buthene, BCB), bismaleimide Bismalejmide Triazine (bt), Epoxy Moon Board (FR4, FR5), Polyimide (ρι), Polytetrafluoroethylene (P0丨y (tetra-f丨0roethy丨ene) ), PTFE). or one of epoxy resin and glass fiber; the first-eight-barrier layer 3 4, 3 5 : 2, 4 3, 5 5, 5 6 , 7 3, 7 4 can also be printed Or the high sensitivity first resistance of the dry film or the wet film by the method of spin coating; the first to the nine metal layers 32, 33, 39, 4, and 5 1 , 5 2, 7 7 and 7 8 may be Copper or other equivalent metal; the first to seventh metal layers 3 2, 3 3, 3 9 , 4 丄, 4 8 , 5 1 , 5 2 and the first and second seed layers 7 丄, 7 2 The method may be etching or other equivalent method; the removal method of the first to eighth resist layers 34, 3 5: 42, 43, 55, 56, 73, 7 may be stripping or other equivalent methods. . When the present invention is applied, it is first made on the double-sided substrate by optical micro-shadow and the surname of the square layer, thereby using the layer as the layer: the structure: the sexual connection pad' and then the single The layer connection pads are pressed into the first build-up line to form a three-layer metal strip, and two of the layers have completed the patterned circuit and have been electrically connected through the subsequent plurality of electric ore blind holes. Then, forming a third build-up line on the metal layer of the second build-up line on the 4th build-up line structure, forming a fourth layer of substrates electrically connected, and stepping into the step 2 The lower layer is used as the electrical connection of the build-up structure 亦 'also === the complete line of the side: while connecting the base of the buried hole, s " / the way is to use a plurality of plating blind holes or production Therefore, the semiconductor multi-layer package substrate structure modified by the high-density layer-added circuit board of the present invention is used for the problem of the core board substrate and the sealing process of the conventional build-up line. The system can be formed into a plurality of layers according to actual needs: it can effectively reduce the thickness of the finished board and reduce the number of 1357646. In summary, the present invention is one of the following, which can effectively improve various disadvantages of the conventional ones, and can complete a semiconductor multilayer package. The substrate structure comprises two layers of patterned circuits and a double-layered structure such as a crystallized side and a ball-side circuit layer of the completed patterned circuit process, which can effectively improve the bending problem of the ultra-thin core substrate plate and simplify the traditional build-up circuit board. Production process, It is a package substrate which can form a plurality of layers according to actual needs, and can effectively reduce the thickness of the finished board and reduce the manufacturing cost, thereby making the invention more progressive, more practical and more suitable for the user. Having met the requirements of the invention patent application, the patent application is filed according to law. However, the above description is only for the preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto; The simple equivalent changes and modifications made by the patent scope and the contents of the description of the invention are still within the scope of the invention. [Simplified illustration of the drawings] Fig. 1 is a schematic diagram of the production process of the invention. 3 is a schematic cross-sectional view of a two-layer substrate (1) of the present invention. FIG. 4 is a schematic cross-sectional view of a two-layer substrate (2) of the present invention. FIG. 6 is a schematic cross-sectional view of a two-layer substrate (four) of the present invention. FIG. 7 is a three-layer substrate of the present invention. Figure 8 is a schematic cross-sectional view of a three-layer substrate (six) of the present invention. Figure 9 is a schematic cross-sectional view of a three-layer substrate (seven) of the present invention. Figure 10 is a three-layer substrate of the present invention ( VIII) Schematic diagram of the section. Fig. 11 is a schematic cross-sectional view of the three-layer substrate (nine) of the present invention. Fig. 1 2 is a schematic cross-sectional view of the three-layer substrate (ten) of the present invention. Schematic diagram of a three-layer substrate (11). Figure 14 is a schematic cross-sectional view of a four-layer substrate (1) of the present invention. Figure 15 is a schematic cross-sectional view of a four-layer substrate (2) of the present invention. A schematic view of a four-layer substrate (III) of the present invention. Fig. 17 is a schematic cross-sectional view of a four-layer substrate (four) of the present invention. Fig. 18 is a schematic cross-sectional view of a four-layer substrate (f) of the present invention. Figure 19 is a schematic view of a four-layer substrate (six) of the present invention. 1357646 Fig. 20 is a schematic cross-sectional view of a four-layer substrate (seven) of the present invention. Fig. 2 is a schematic cross-sectional view showing the crystal side and the ball side wiring layer (1) of the present invention. Fig. 2 is a schematic cross-sectional view showing the crystal side and the ball side wiring layer (2) of the present invention. Fig. 2 is a schematic cross-sectional view showing the crystallizing side and the ball side wiring layer (3) in the practice of the present invention. Figure 24 is a schematic cross-sectional view of the two-layer line build-up structure (1) above and below the present invention. Figure 25 is a schematic cross-sectional view of the two-layer line build-up structure (2) above and below the present invention. Figure 26 is a schematic cross-sectional view of the three-layer line build-up structure (3) above and below the present invention. Figure 27 is a schematic cross-sectional view of the two-layer line build-up structure (4) above and below the present invention. Figure 28 is a schematic cross-sectional view of the two-layer line build-up structure (5) above and below the present invention. Figure 29 is a schematic cross-sectional view of the two-layer line build-up structure (6) above and below the present invention. Figure 30 is a schematic cross-sectional view of the two-layer line build-up structure (7) above and below the present invention. Figure 31 is a schematic cross-sectional view of the two-layer line build-up structure (8) 20 1357646 of the present invention. Figure 3 is a schematic cross-sectional view of a conventional nuclear-coated substrate. Figure 3 is a schematic diagram of the cross-section of the circuit (1).
第3 4圖，係習用之實施線路增層（二）剖面示意圖。 第3 5圖，係習用之實施線路增層（三）剖面示意圖。 第3 6圖’係習用之實施線路增層（四）剖面示意圖。 第3 7圖’係另—f用有核層封裝基板之剖面示意圖。 第3 8圖’係習用之第—線路増層結構剖面示意圖。 第3 9圖，係習用之第 【主要元件符號說明】 (本發明部分） 路增層結構剖面示意圖 〇Figure 34 is a schematic diagram of the cross-section of the circuit (2). Figure 35 is a schematic diagram of the cross-section of the circuit (3). Figure 3 is a schematic view of the cross-section of the circuit (4). Figure 37 is a schematic cross-sectional view of a nucleated layer package substrate. Figure 3 is a schematic view of the structure of the first layer of the circuit. Figure 39, the first part of the application [Explanation of the main components symbol] (part of the invention) Schematic diagram of the road layer structure 〇
步驟（A)〜（u) 11〜3〇 步驟（tl)〜（t3) 291 步驟（ul)〜（ug) 3〇工 雙面基板1 〜2 9 3 〜3 0 8 三層基板2 a、2 b 四層基板3 四層無核層多層封裝基板4 六層基板5 第一介電層3 1 第一、二金屬層32、33 1357646 第一、二阻層34、35 第一開口 3 6 第一線路層3 7 第一、二面 37a、37b 第二介電層3 8 第三金屬層3 9 第二開口 4 〇 第四金屬層4 1 第一雷射盲孔4 6 第三、四阻層42、43 第三開口 4 4 第三線路層4 5 第三介電層4 7 第五金屬層4 8 第四、五開口 49、50 第六、七金屬層51、52 第二、三雷射盲孔53、54 第五、六阻層5 5、56 第六、七開口 57、58 第二、四線路層59、60 22 1357646 第一、二防焊層61、62 第八、九開口 6 3、6 4 第一、二阻障層65、66 第四、五介電層67、68 第十、十一開口 69、70 第一、二晶種層71、72 第七、八阻層73、74 第十二、十三開口 75、76 第八、九金屬層77、78 第五、六線路層79、80 (習用部分） 第一、二線路增層結構8 a、8 b 核心基板8 1 芯層8 1 1 線路層8 1 2 電鍍導通孔8 1 3 第一、二介電層8 2、8 9 第一、二開口83、86 晶種層8 4 圖案化阻層8 5 23 1357646 第一、二圖案化線路層87、90 導電盲孔8 8 第一、二線路增層結構9 a、9 b 核心基板9 1 樹脂塞孔9 1 1 電鍍通孔9 1 2 第一、二介電層92、94 第一、二圖案化線路層9 3、9 5Step (A)~(u) 11~3〇Step (tl)~(t3) 291 Step (ul)~(ug) 3 Completion of double-sided substrate 1~2 9 3~3 0 8 Three-layer substrate 2 a, 2 b four-layer substrate 3 four-layer coreless multi-layer package substrate 4 six-layer substrate 5 first dielectric layer 3 1 first and second metal layers 32, 33 1357646 first and second resist layers 34, 35 first opening 3 6 First circuit layer 3 7 first, two sides 37a, 37b second dielectric layer 3 8 third metal layer 3 9 second opening 4 〇 fourth metal layer 4 1 first laser blind hole 4 6 third, fourth Resistor layer 42, 43 third opening 4 4 third circuit layer 4 5 third dielectric layer 4 7 fifth metal layer 4 8 fourth, fifth opening 49, 50 sixth, seventh metal layer 51, 52 second, third Laser blind holes 53, 54 fifth and sixth resistive layers 5 5, 56 sixth, seventh openings 57, 58 second and fourth circuit layers 59, 60 22 1357646 first and second solder resist layers 61, 62 eighth, nine Openings 6 3, 6 4 first and second barrier layers 65, 66 fourth and fifth dielectric layers 67, 68 tenth, eleven openings 69, 70 first and second seed layers 71, 72 seventh, eight resistance Layers 73, 74 twelfth, thirteenth openings 75, 76 eighth, nine metal layers 77, 78 fifth, Circuit layer 79, 80 (conventional part) First and second line build-up structure 8 a, 8 b Core substrate 8 1 Core layer 8 1 1 Circuit layer 8 1 2 Plating via 8 1 3 First and second dielectric layers 8 2, 8 9 first and second openings 83, 86 seed layer 8 4 patterned resist layer 8 5 23 1357646 first and second patterned circuit layers 87, 90 conductive blind holes 8 8 first and second line build-up structure 9 a, 9 b core substrate 9 1 resin plug hole 9 1 1 plated through hole 9 1 2 first and second dielectric layers 92, 94 first and second patterned circuit layers 9 3, 9 5
24twenty four